JP5254049B2 - パターン形成方法及び半導体装置の製造方法 - Google Patents

パターン形成方法及び半導体装置の製造方法 Download PDF

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Publication number
JP5254049B2
JP5254049B2 JP2009003910A JP2009003910A JP5254049B2 JP 5254049 B2 JP5254049 B2 JP 5254049B2 JP 2009003910 A JP2009003910 A JP 2009003910A JP 2009003910 A JP2009003910 A JP 2009003910A JP 5254049 B2 JP5254049 B2 JP 5254049B2
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Japan
Prior art keywords
pattern
boundary layer
mask material
forming
material layer
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JP2009003910A
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English (en)
Japanese (ja)
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JP2009218574A5 (enExample
JP2009218574A (ja
Inventor
英民 八重樫
悟 志村
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2009003910A priority Critical patent/JP5254049B2/ja
Priority to TW098104546A priority patent/TWI404141B/zh
Priority to KR1020090011979A priority patent/KR101000947B1/ko
Priority to US12/370,768 priority patent/US8273661B2/en
Publication of JP2009218574A publication Critical patent/JP2009218574A/ja
Publication of JP2009218574A5 publication Critical patent/JP2009218574A5/ja
Priority to US13/591,281 priority patent/US20120312472A1/en
Application granted granted Critical
Publication of JP5254049B2 publication Critical patent/JP5254049B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009003910A 2008-02-15 2009-01-09 パターン形成方法及び半導体装置の製造方法 Active JP5254049B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009003910A JP5254049B2 (ja) 2008-02-15 2009-01-09 パターン形成方法及び半導体装置の製造方法
TW098104546A TWI404141B (zh) 2008-02-15 2009-02-12 圖案形成方法、半導體裝置之製造方法及半導體裝置之製造裝置
KR1020090011979A KR101000947B1 (ko) 2008-02-15 2009-02-13 패턴 형성 방법, 반도체 장치의 제조 방법 및 반도체 장치의 제조 장치
US12/370,768 US8273661B2 (en) 2008-02-15 2009-02-13 Pattern forming method, semiconductor device manufacturing method and semiconductor device manufacturing apparatus
US13/591,281 US20120312472A1 (en) 2008-02-15 2012-08-22 Semiconductor device manufacturing apparatus

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008034230 2008-02-15
JP2008034230 2008-02-15
JP2009003910A JP5254049B2 (ja) 2008-02-15 2009-01-09 パターン形成方法及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2009218574A JP2009218574A (ja) 2009-09-24
JP2009218574A5 JP2009218574A5 (enExample) 2012-02-23
JP5254049B2 true JP5254049B2 (ja) 2013-08-07

Family

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JP2009003910A Active JP5254049B2 (ja) 2008-02-15 2009-01-09 パターン形成方法及び半導体装置の製造方法

Country Status (4)

Country Link
US (2) US8273661B2 (enExample)
JP (1) JP5254049B2 (enExample)
KR (1) KR101000947B1 (enExample)
TW (1) TWI404141B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100098843A (ko) * 2009-03-02 2010-09-10 삼성전자주식회사 패턴 형성 방법
JP5589692B2 (ja) 2010-09-08 2014-09-17 富士通セミコンダクター株式会社 半導体装置の製造方法
US8138097B1 (en) 2010-09-20 2012-03-20 Kabushiki Kaisha Toshiba Method for processing semiconductor structure and device based on the same
US9233840B2 (en) * 2010-10-28 2016-01-12 International Business Machines Corporation Method for improving self-assembled polymer features
KR101871748B1 (ko) 2011-12-06 2018-06-28 삼성전자주식회사 반도체 소자의 패턴 형성 방법
CN104576515B (zh) * 2013-11-15 2017-10-13 北京京东方光电科技有限公司 图案化石墨烯薄膜及阵列基板的制作方法、阵列基板
JP6126570B2 (ja) * 2013-12-13 2017-05-10 富士フイルム株式会社 パターン形成方法、電子デバイスの製造方法
JP6272949B2 (ja) * 2016-06-06 2018-01-31 東京エレクトロン株式会社 パターン形成方法
CN106707715B (zh) * 2017-01-11 2019-05-21 中国科学院长春光学精密机械与物理研究所 一种半导体器件及其制作方法
US10734238B2 (en) * 2017-11-21 2020-08-04 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for critical dimension control
KR102431218B1 (ko) * 2018-10-01 2022-08-09 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 기둥상 반도체 장치의 제조 방법
CN113677825B (zh) * 2019-04-16 2023-10-24 应用材料公司 沟槽中薄膜沉积的方法
US11629402B2 (en) 2019-04-16 2023-04-18 Applied Materials, Inc. Atomic layer deposition on optical structures

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207339A (ja) * 1984-03-30 1985-10-18 Matsushita Electronics Corp パタ−ン形成方法
JPS6449231A (en) * 1987-08-20 1989-02-23 Fujitsu Ltd Manufacture of semiconductor device
JPH0670954B2 (ja) * 1988-01-26 1994-09-07 日本電気株式会社 半導体装置の製造方法
US5618383A (en) * 1994-03-30 1997-04-08 Texas Instruments Incorporated Narrow lateral dimensioned microelectronic structures and method of forming the same
US6143126A (en) * 1998-05-12 2000-11-07 Semitool, Inc. Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on an integrated circuit
JP3474865B2 (ja) * 2001-04-20 2003-12-08 株式会社東芝 半導体装置の製造方法
US6833232B2 (en) * 2001-12-20 2004-12-21 Dongbu Electronics Co., Ltd. Micro-pattern forming method for semiconductor device
US6858361B2 (en) * 2002-03-01 2005-02-22 David S. L. Mui Methodology for repeatable post etch CD in a production tool
US7064078B2 (en) * 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
KR100640640B1 (ko) * 2005-04-19 2006-10-31 삼성전자주식회사 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법
US7560390B2 (en) * 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
KR100640657B1 (ko) * 2005-07-25 2006-11-01 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
KR101200938B1 (ko) * 2005-09-30 2012-11-13 삼성전자주식회사 반도체 장치의 패턴 형성 방법
KR100714305B1 (ko) * 2005-12-26 2007-05-02 삼성전자주식회사 자기정렬 이중패턴의 형성방법
KR100672123B1 (ko) 2006-02-02 2007-01-19 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
US7745339B2 (en) 2006-02-24 2010-06-29 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US7314810B2 (en) * 2006-05-09 2008-01-01 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
KR100781542B1 (ko) * 2006-06-08 2007-12-03 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법

Also Published As

Publication number Publication date
US20120312472A1 (en) 2012-12-13
TW201003780A (en) 2010-01-16
KR101000947B1 (ko) 2010-12-13
US8273661B2 (en) 2012-09-25
KR20090088823A (ko) 2009-08-20
US20090209109A1 (en) 2009-08-20
JP2009218574A (ja) 2009-09-24
TWI404141B (zh) 2013-08-01

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