JP5073181B2 - 半導体メモリ素子の漏洩電流制御装置 - Google Patents
半導体メモリ素子の漏洩電流制御装置 Download PDFInfo
- Publication number
- JP5073181B2 JP5073181B2 JP2005189487A JP2005189487A JP5073181B2 JP 5073181 B2 JP5073181 B2 JP 5073181B2 JP 2005189487 A JP2005189487 A JP 2005189487A JP 2005189487 A JP2005189487 A JP 2005189487A JP 5073181 B2 JP5073181 B2 JP 5073181B2
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- control signal
- semiconductor memory
- leakage current
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
20 サブワードライン駆動部
30、31、32、33、34、35 電流遮断駆動素子
40 リフレッシュカウンタ
50 リフレッシュブロック検出部
60 制御信号入力部
70 ラッチ部
80 ロジック部
90 電圧制御部
91、92、93、94、95、96 ビットライン電圧制御部
100 ビットラインプリチャージ部
101 プリチャージ部
Claims (6)
- ブロック選択信号の活性化の可否に従い駆動制御信号を制御する制御信号生成部と、
プリチャージ区間の間、前記駆動制御信号にターンオンされてビットラインの電圧レベルを接地電圧レベルに遷移させ、前記ビットラインからワードラインに形成される電流経路を遮断する複数個の電流遮断駆動素子と、
を備え、
前記制御信号生成部は、前記ブロック選択信号の活性化時に前記電流遮断駆動素子がターンオンされるように前記駆動制御信号を出力する駆動素子と、
前記駆動素子の出力を反転するインバータと、
を備えることを特徴とする半導体メモリ素子の漏洩電流制御装置。 - アクティブモード時、前記駆動制御信号が活性化されてセンスアンプの動作有効区間の一部において、前記ビットラインをビットラインプリチャージ電圧レベルに制御することを特徴とする請求項1に記載の半導体メモリ素子の漏洩電流制御装置。
- 前記駆動素子は、ロジックハイ信号と前記ブロック選択信号のNAND演算を行なうNANDゲートであることを特徴とする請求項1に記載の半導体メモリ素子の漏洩電流制御装置。
- 前記複数個の電流遮断駆動素子のそれぞれは、接地電圧端と前記ビットラインとの間に連結され、ゲート端子を介して反転された前記駆動制御信号が印加されるNMOSトランジスタを備えることを特徴とする請求項1に記載の半導体メモリ素子の漏洩電流制御装置。
- 前記ブロック選択信号に応じ選択された一つの当該ワードラインを基準に上/下に備えられた複数個のセンスアンプが駆動されることを特徴とする請求項1に記載の半導体メモリ素子の漏洩電流制御装置。
- ブロック選択信号の活性化の可否に従い駆動制御信号を制御する制御信号生成部と、
プリチャージ区間の間、リフレッシュ動作に伴い前記ブロック選択信号が活性化された場合には、前記駆動制御信号によりターンオフされてビットラインにプリチャージ電圧を供給する一方、リフレッシュ動作が行われず前記ブロック選択信号が非活性化された場合には、前記駆動制御信号によりターンオンされて前記ビットラインの電圧レベルを接地電圧レベルに遷移させ、前記ビットラインからワードラインに形成される電流経路を遮断する複数個の電流遮断駆動素子と、
を備えることを特徴とする半導体メモリ素子の漏洩電流制御装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2004-084639 | 2004-10-22 | ||
KR1020040084639A KR100649834B1 (ko) | 2004-10-22 | 2004-10-22 | 반도체 메모리 소자의 누설 전류 제어 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006120301A JP2006120301A (ja) | 2006-05-11 |
JP5073181B2 true JP5073181B2 (ja) | 2012-11-14 |
Family
ID=36206031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005189487A Expired - Fee Related JP5073181B2 (ja) | 2004-10-22 | 2005-06-29 | 半導体メモリ素子の漏洩電流制御装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20060087898A1 (ja) |
JP (1) | JP5073181B2 (ja) |
KR (1) | KR100649834B1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7068556B2 (en) * | 2004-03-09 | 2006-06-27 | Lattice Semiconductor Corporation | Sense amplifier systems and methods |
KR100656434B1 (ko) * | 2005-11-09 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 누설 전류 감소 회로 |
KR101215641B1 (ko) * | 2006-12-26 | 2012-12-26 | 에스케이하이닉스 주식회사 | 반도체 장치의 전류저감회로 |
US7944747B2 (en) * | 2008-03-17 | 2011-05-17 | Samsung Electronics Co., Ltd. | Flash memory device and method for programming flash memory device having leakage bit lines |
KR100958805B1 (ko) * | 2008-09-03 | 2010-05-24 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 전원 공급 장치 및 방법 |
JP5621704B2 (ja) * | 2011-05-11 | 2014-11-12 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
US8599633B2 (en) * | 2012-05-06 | 2013-12-03 | Elite Semiconductor Memory Technology Inc. | Method for reducing standby current of semiconductor memory device |
TWI466115B (zh) * | 2012-07-20 | 2014-12-21 | Elite Semiconductor Esmt | 減少半導體記憶裝置待機電流之方法 |
US8947968B2 (en) * | 2013-07-08 | 2015-02-03 | Arm Limited | Memory having power saving mode |
US10236036B2 (en) * | 2017-05-09 | 2019-03-19 | Micron Technology, Inc. | Sense amplifier signal boost |
US10566036B2 (en) | 2018-06-15 | 2020-02-18 | Micron Technology, Inc. | Apparatuses and method for reducing sense amplifier leakage current during active power-down |
US11568948B2 (en) | 2021-02-12 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and method of operating same |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2617617B2 (ja) * | 1990-11-16 | 1997-06-04 | 九州日本電気株式会社 | 半導体メモリ |
JPH05128858A (ja) * | 1991-11-05 | 1993-05-25 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
JP2816512B2 (ja) | 1992-07-27 | 1998-10-27 | 三菱電機株式会社 | 半導体記憶装置 |
JPH07272483A (ja) | 1994-04-01 | 1995-10-20 | Hitachi Ltd | 半導体メモリ |
JP2983875B2 (ja) * | 1994-04-15 | 1999-11-29 | 松下電器産業株式会社 | 半導体記憶装置 |
KR0152168B1 (ko) * | 1994-04-15 | 1998-10-01 | 모리시다 요이치 | 반도체 기억장치 |
JP4084428B2 (ja) * | 1996-02-02 | 2008-04-30 | 富士通株式会社 | 半導体記憶装置 |
KR100234365B1 (ko) * | 1997-01-30 | 1999-12-15 | 윤종용 | 반도체 메모리장치의 리프레쉬 방법 및 회로 |
US6111802A (en) * | 1997-05-19 | 2000-08-29 | Fujitsu Limited | Semiconductor memory device |
US5898633A (en) | 1997-05-21 | 1999-04-27 | Motorola, Inc. | Circuit and method of limiting leakage current in a memory circuit |
US6317370B2 (en) * | 1998-01-12 | 2001-11-13 | Micron Technology, Inc. | Timing fuse option for row repair |
US5909388A (en) * | 1998-03-31 | 1999-06-01 | Siemens Aktiengesellschaft | Dynamic random access memory circuit and methods therefor |
JP3863313B2 (ja) * | 1999-03-19 | 2006-12-27 | 富士通株式会社 | 半導体記憶装置 |
JP3624811B2 (ja) * | 2000-09-05 | 2005-03-02 | セイコーエプソン株式会社 | 半導体装置、そのリフレッシュ方法、メモリシステムおよび電子機器 |
JP2002208298A (ja) * | 2001-01-10 | 2002-07-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2003188351A (ja) | 2001-12-17 | 2003-07-04 | Hitachi Ltd | 半導体集積回路 |
JP4229230B2 (ja) * | 2003-05-06 | 2009-02-25 | インターナショナル・ビジネス・マシーンズ・コーポレーション | ダイナミック型半導体記憶装置及びそのビット線プリチャージ方法 |
US6954397B2 (en) * | 2003-07-24 | 2005-10-11 | Texas Instruments Incorporated | Circuit for reducing standby leakage in a memory unit |
-
2004
- 2004-10-22 KR KR1020040084639A patent/KR100649834B1/ko not_active IP Right Cessation
-
2005
- 2005-06-09 US US11/148,567 patent/US20060087898A1/en not_active Abandoned
- 2005-06-29 JP JP2005189487A patent/JP5073181B2/ja not_active Expired - Fee Related
-
2008
- 2008-03-07 US US12/044,484 patent/US7724594B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20080151662A1 (en) | 2008-06-26 |
JP2006120301A (ja) | 2006-05-11 |
KR100649834B1 (ko) | 2006-11-28 |
US7724594B2 (en) | 2010-05-25 |
US20060087898A1 (en) | 2006-04-27 |
KR20060035235A (ko) | 2006-04-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5073181B2 (ja) | 半導体メモリ素子の漏洩電流制御装置 | |
US6226215B1 (en) | Semiconductor memory device having reduced data access time and improve speed | |
JP4354917B2 (ja) | 半導体記憶装置 | |
KR100507379B1 (ko) | 워드라인 구동 회로 | |
JP2007257707A (ja) | 半導体記憶装置 | |
JP2004134026A (ja) | 半導体記憶装置及びその制御方法 | |
JP2007012244A (ja) | 半導体メモリ装置のレイテンシ制御回路 | |
JP2010061701A (ja) | 半導体装置 | |
JP2000149547A (ja) | 半導体記憶装置 | |
JP2008269772A (ja) | カラムリダンダンシ回路 | |
US8553479B2 (en) | Semiconductor memory device | |
JP2008305531A (ja) | ワードライン駆動回路及びこれを備える半導体メモリ装置並びにそのテスト方法 | |
JP2006286163A (ja) | 半導体メモリ素子のオーバードライバ制御信号の生成回路 | |
JP5119795B2 (ja) | 半導体メモリ、半導体メモリのテスト方法およびシステム | |
JP2008084428A (ja) | 半導体メモリおよびシステム | |
JP2007095286A (ja) | 電圧発生装置 | |
JP2001076498A (ja) | 半導体記憶装置 | |
KR100700331B1 (ko) | 셀프 리프레쉬 전류 제어 장치 | |
JP2001176296A (ja) | ストレス試験を行うダイナミックメモリデバイス | |
JP4563694B2 (ja) | 半導体メモリ装置及びワードライン駆動方法。 | |
KR100535131B1 (ko) | 페이지 모드에서의 메모리 소자 리드 방법 및 이를 이용한로우 디코더 제어회로 | |
KR100294450B1 (ko) | 반도체메모리장치의어레이내부전원전압발생회로 | |
KR100535814B1 (ko) | 서브워드라인 드라이버의 안정된 부스팅 마진을 얻을 수있는 워드라인 제어신호 발생회로, 워드라인 제어신호발생방법, 및 그것을 구비한 반도체 메모리 장치 | |
KR100816729B1 (ko) | 코어전압 생성 장치 및 그를 포함하는 반도체 메모리 장치 | |
JP5564829B2 (ja) | 半導体記憶装置及びその制御方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080327 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101102 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101109 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110209 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111101 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120201 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120206 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120301 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120807 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120822 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150831 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |