US20060087898A1 - Leakage current control device of semiconductor memory device - Google Patents

Leakage current control device of semiconductor memory device Download PDF

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Publication number
US20060087898A1
US20060087898A1 US11/148,567 US14856705A US2006087898A1 US 20060087898 A1 US20060087898 A1 US 20060087898A1 US 14856705 A US14856705 A US 14856705A US 2006087898 A1 US2006087898 A1 US 2006087898A1
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Prior art keywords
signal
bit line
unit
leakage current
voltage
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Abandoned
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US11/148,567
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English (en)
Inventor
Sung Xi
Chae Jang
Hoe Jeong
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SK Hynix Inc
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Hynix Semiconductor Inc
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Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JANG, CHAE KYU, JEONG, HOE KWON, XI, SUNG SOO
Publication of US20060087898A1 publication Critical patent/US20060087898A1/en
Priority to US12/044,484 priority Critical patent/US7724594B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present invention generally relates to a leakage current control device of a semiconductor memory device, and more specifically, to a technology of effectively removing leakage current when a process defect is generated by gate residues.
  • FIGS. 1 and 2 are diagrams illustrating a path of leakage current by the gate residue process defect in a conventional semiconductor memory device.
  • a word line WL and a bit line BL are connected to a resistor R and a capacitor C. While the semiconductor memory device is precharged, the word line WL transits to a ground voltage level, and the bit line BL is maintained at a core voltage/2 (bit line precharge voltage VBLP).
  • a basic refresh operation is required to maintain data for the minimum power consumption at a standby mode of a low power consumption memory product.
  • leakage current is generated by a gate residue phenomenon at the standby mode of the low power consumption memory product, unnecessary current is consumed.
  • Various embodiments of the present invention are directed at controlling a pair of bit lines, which are boosted to a voltage level of core voltage/2 during a precharge or standby period, at a ground voltage level to remove unnecessary leakage current flowing into a word line.
  • a leakage current control device of a semiconductor memory device comprises a control signal generating unit adapted and configured to control a driving control signal in response to a block selecting signal, and a plurality of current blocking driving element adapted and configured to be turned on in response to the driving control signal during a precharge period and to transit a voltage level of a bit line to a ground voltage to intercept a current path formed from the bit line to a word line.
  • a leakage current control device of a semiconductor memory device comprises a refresh block detecting unit adapted and configured to detect a block where a refresh operation is performed in response to a driving control signal generated by combination of a block selecting signal, a control signal input unit adapted and configured to latch an output signal from the refresh block detecting unit for a predetermined time at a standby mode, and a voltage control unit adapted and configured to supply a bit line precharge voltage to a bit line in response to an output signal from the control signal input unit at a refresh mode and to supply a ground voltage to the bit line at the standby mode.
  • a leakage current control device of a semiconductor memory device comprises a block detecting unit adapted and configured to sense a block selecting signal and to control activation of a selected cell array block, a logic unit adapted and configured to combine a predetermined logic signal and an output signal from the block detecting unit and to output a control signal for activating a corresponding cell array block, and a voltage control unit adapted and configured to supply a bit line precharge voltage to a bit line of the cell array block in response to an output signal from the logic unit at a refresh mode, and to supply a ground voltage to the bit line at the standby mode.
  • FIGS. 1 and 2 are diagrams illustrating a path of leakage current in a conventional semiconductor memory device
  • FIG. 3 is a circuit diagram illustrating a leakage current control device of a semiconductor memory device according to an embodiment of the present invention
  • FIG. 4 is a waveform diagram of each control signal of the leakage current control device of the semiconductor memory device according to an embodiment of the present invention.
  • FIG. 5 is a simulation diagram illustrating the leakage current control device of the semiconductor memory device according to an embodiment of the present invention.
  • FIG. 6 is a diagram illustrating a leakage current control device of a semiconductor memory device according to another embodiment of the present invention.
  • FIG. 7 is a circuit diagram illustrating a bit line voltage control unit of FIG. 6 ;
  • FIG. 8 is a diagram illustrating a leakage current control device of a semiconductor memory device according to still another embodiment of the present invention.
  • FIG. 3 is a circuit diagram illustrating a leakage current control device of a semiconductor memory device according to an embodiment of the present invention.
  • a leakage current control device comprises a control signal generating unit 10 , a sub word line driving unit 20 , a sense amplifier SA and a plurality of current blocking driving elements 30 ⁇ 35 .
  • control signal generating unit 10 comprises NAND gates ND 1 , ND 2 , and inverters IV 1 ⁇ IV 3 .
  • the NAND gate ND 1 performs a NAND operation on a logic high signal and a block selecting signal BSS to output a driving control signal GTRSD.
  • the inverters IV 1 , IV 2 invert the driving control signal GTRSD.
  • the NAND gate ND 2 performs a NAND operation on the logic high signal and the block selecting signal BSS to output the driving control signal GTRSD.
  • the inverter IV 3 inverts the driving control signal GTRSD.
  • Each of the plurality of current blocking driving elements 30 ⁇ 35 which are connected between paired bit lines BL and BLB and a ground voltage terminal, comprises a plurality of NMOS transistors that have each gate to receive output signals from the inverters IV 1 ⁇ IV 3 .
  • the paired bit lines BL and BLB are precharged to a bit line precharge voltage (core voltage VCORE/2) level before a word line WL is activated.
  • core voltage VCORE/2 bit line precharge voltage
  • the block selecting signal BSS becomes ‘low’ which is relatively faster that the decoded word line WL.
  • the driving control signal GTRSD outputted from the NAND gates ND 1 and ND 2 becomes ‘high’ during an effective period of the sense amplifier SA.
  • the output signals from the inverters IV 1 ⁇ IV 3 become ‘low’, so that all of the current blocking driving elements 30 ⁇ 35 are kept off.
  • the paired bit lines BL and BLB are precharged to a bit line precharge voltage VBLP (core voltage/2) during an active period to perform a general memory operation.
  • the sense amplifier SA positioned above and below one corresponding word line WL selected by the block selecting signal BSS is driven by a conventional signal CS.
  • the block selecting signal BSS becomes ‘high’.
  • the driving control signal GTRSD outputted from the NAND gates ND 1 and ND 2 transits to ‘low’.
  • the output signals from the inverters IV 1 ⁇ IV 3 become ‘high’ to turn on all of the current blocking driving elements 30 ⁇ 35 .
  • the paired bit lines BL and BLB of a cell array where a gate residue phenomenon occurs becomes at a ground voltage level to intercept a leakage path of unnecessary current.
  • the leakage current control device supplies the bit line precharge voltage VBLP (core voltage/2) to the bit line BL connected to a Core during the active period, and supplies a ground voltage to the bit line BL during the precharge period.
  • VBLP core voltage/2
  • FIG. 6 is a diagram illustrating a leakage current control device of a semiconductor memory device according to another embodiment of the present invention.
  • a leakage current control device of FIG. 6 comprises a refresh counter 40 , refresh block detecting unit 50 , a control signal input unit 60 , a latch unit 70 , a logic unit 80 and a voltage control unit 90 .
  • the refresh counter 40 performs a refresh counting operation to output the driving control signal GTRSD obtained by combining word line, block selecting and bank selecting signals to the refresh block detecting unit 50 . Since the driving control signal GTRSD is relatively faster than a timing when signals for generating the word line WL are decoded, the voltage control unit 90 is controlled by the driving control signal GTRSD.
  • the refresh block detecting unit 50 detects a block where a refresh operation is performed in response to the driving control signal GTRSD to output a control signal of n bits.
  • the control signal input unit 60 comprises a plurality of inverters IV 4 , IV 5 , a plurality of NAND gates ND 3 ⁇ ND 8 , and a plurality of latches R 1 ⁇ R 6 .
  • the plurality of inverters IV 4 ⁇ IV 5 invert the control signal of n bits applied from the refresh block detecting unit 50 .
  • the plurality of NAND gates ND 3 ⁇ ND 8 perform a NAND operation on output signals from the inverters IV 4 , IV 5 and a standby signal STBY.
  • the plurality of latches R 1 ⁇ R 6 latch output signals from the plurality of NAND gates ND 3 ⁇ ND 8 in response to an active signal ACT.
  • the control signal input unit 60 is turned off when the active signal ACT and the standby signal STBY are “0”.
  • the control signal input unit 60 is activated when the active signal ACT is “0” and the standby signal STBY is “1”. Also, the control signal input unit 60 is turned off when the active signal ACT is “1” and the standby signal STBY is “Don't Care”.
  • the latch unit 70 that comprises a plurality of latches R 7 ⁇ R 12 latches an output signal from the control signal input unit 60 .
  • the logic unit 80 performs a NAND operation on an output signal from the latch unit 70 and a logic high signal.
  • the voltage control unit 90 that comprises a plurality of bit line voltage control units 91 ⁇ 96 controls the bit line precharge voltage VBLP in response to an output signal from the logic unit 80 to selectively output the voltage VBLP to cell arrays F 0 ⁇ F 4 .
  • FIG. 7 is a circuit diagram illustrating one of the bit line voltage control units 91 ⁇ 96 of FIG. 6 .
  • the bit line voltage control unit 91 is exemplified because the plurality of bit line voltage control units 91 ⁇ 96 have the same configuration.
  • the bit line voltage control unit 91 comprises inverters IV 9 ⁇ IV 12 , and NMOS transistors N 1 , N 2 .
  • the inverter IV 9 inverts an output signal from the NAND gate ND 9
  • the inverter IV 10 inverts an output signal from the inverter IV 9
  • the inverters IV 11 and IV 12 non-invert and delay an output signal from the inverter IV 9 .
  • the NMOS transistor N 1 which is connected between a bit line precharge voltage VBLP terminal and an output node NODE, has a gate to receive an output signal from the inverter IV 10 .
  • the NMOS transistor N 2 which is connected between a ground voltage VSS terminal and the output node NODE, has a gate to receive an output signal from the inverter IV 12 .
  • the output node NODE of the bit line voltage control unit 91 which is connected to the bit line precharge unit 100 of the sense amplifier SA controls the paired bit lines BL and BLB at the ground voltage VSS level during the precharge period at the standby mode.
  • the output node NODE of the bit lien voltage control unit 91 which is connected to a precharge unit 101 , the paired bit lines BL and BLB at the ground voltage VSS level during the precharge period at the standby mode.
  • the refresh counter 40 counts a refresh operation at a refresh mode, and combines a block selecting signal to output the driving control signal GTRSD at a high level during the effective period of the sense amplifier SA.
  • the refresh counter 40 sequentially accesses a corresponding block using an address generated at the refresh mode, and previously sets a block to be boosted to the bit line precharge voltage VBLP.
  • a refresh block counted by the refresh counter 40 is the Nth
  • the bit line precharge voltage (core voltage VCORE/2) is previously supplied to the (N+1)th block.
  • the driving control signal GTRSD transits to ‘low’ during the precharge period.
  • the active signal ACT becomes “0”
  • the standby signal STBY controls the operation of the control signal input unit 60 . That is, the control signal input unit 60 is turned off when the standby signal STBY is “0”, and activated when the standby signal STBY is “1”.
  • the latch unit 70 When the standby signal STBY becomes “1” at the standby mode, the latch unit 70 outputs a high signal to the logic unit 80 , and the logic unit 80 outputs a low signal to the voltage control unit 90 .
  • the NMOS transistor N 2 is turned on by output signals from the inverters IV 9 , IV 11 and IV 12 in the bit line voltage control unit 91 . Then, the ground voltage VSS is supplied to a common connection node of the NMOS transistors N 4 and N 5 of the bit line precharge unit 100 . Also, the ground voltage VSS is supplied to a common connection node of the NMOS transistors N 7 and N 8 of the precharge unit 100 .
  • bit line equalizing signal BLEQ becomes ‘high’
  • the NMOS transistors N 3 ⁇ N 8 are turned on, so that the paired bit lines BL and BLB become at the ground voltage level.
  • the paired bit lines BL and BLB of a cell array where the gate residue phenomenon occurs become at the ground voltage level to intercept a leakage path of unnecessary current.
  • the control signal operation unit 60 is turned off.
  • the latch unit 70 outputs a low signal to the logic unit 80 , which outputs a high signal to the voltage control unit 90 .
  • the bit line voltage control unit 91 the NMOS transistor N 1 is turned on by output signals from the inverters IV 9 and IV 10 .
  • the bit line precharge voltage (core voltage VCORE/2) is supplied to the common connection node of the NMOS transistors N 4 and N 5 of the bit line precharge unit 100 .
  • the bit line precharge voltage (core voltage VCORE/2) is supplied to the common connection node of the NMOS transistors N 7 and N 8 of the precharge unit 100 .
  • the NMOS transistors N 3 ⁇ N 8 are turned on, so that the paired bit lines BL and BLB are precharged to a precharge voltage (core voltage VCORE/2) level.
  • bit line precharge voltage VBLP core voltage/2
  • VBLP core voltage/2
  • FIG. 8 is a diagram illustrating a leakage current control device of a semiconductor memory device according to still another embodiment of the present invention.
  • a leakage current control device of FIG. 8 comprises a block detecting unit 110 , a logic unit 120 and a voltage control unit 130 .
  • the block detecting unit 110 which comprises a plurality of block selecting signal sense units 111 ⁇ 114 controls activation of a selected block by a block selecting signal BSS.
  • the logic unit 120 which comprises a plurality of NAND gates ND 16 ⁇ ND 20 performs a logic operation on an output signal from the block detecting unit 110 .
  • the voltage control unit 130 which comprises a plurality of bit line voltage control units 131 is substantially similar to components described in reference to FIG. 7 .
  • the block selecting signal BSS which is relatively faster than a decoded word line WL controls the operation of the bit lien voltage control unit 130 .
  • the paired bit lines BL and BLB are precharged to the bit line precharge voltage VBLP (core voltage/2) level during an active period to perform a general memory operation.
  • VBLP core voltage/2
  • a sense amplifier SA positioned above and below one corresponding word line WL selected by the block selecting signal BSS is driven by a conventional signal CS.
  • the block selecting signal BSS becomes ‘high’ to supply a ground voltage to a bit line BL. Then, paired bit lines BL and BLB of a cell array where a gate residue phenomenon occurs become at a ground voltage level to intercept a leakage path of unnecessary current.
  • a leakage current control device is applied to all products using a semiconductor to improve degradation of performance of a memory by a gate residue phenomenon without structural change of a memory core and to reduce unnecessary current and power consumption at a standby mode, thereby improving the performance of the memory.
US11/148,567 2004-10-22 2005-06-09 Leakage current control device of semiconductor memory device Abandoned US20060087898A1 (en)

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US7102934B1 (en) * 2004-03-09 2006-09-05 Lattice Semiconductor Corporation Sense amplifier systems and methods
US20100054050A1 (en) * 2008-09-03 2010-03-04 Hynix Semiconductor, Inc. Apparatus and method for providing power in semiconductor memory device
US20120287741A1 (en) * 2011-05-11 2012-11-15 Fujitsu Semiconductor Limited Semiconductor storage
US8599633B2 (en) * 2012-05-06 2013-12-03 Elite Semiconductor Memory Technology Inc. Method for reducing standby current of semiconductor memory device
TWI466115B (zh) * 2012-07-20 2014-12-21 Elite Semiconductor Esmt 減少半導體記憶裝置待機電流之方法
KR20220115848A (ko) * 2021-02-12 2022-08-19 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 회로 및 그 동작 방법

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US7944747B2 (en) * 2008-03-17 2011-05-17 Samsung Electronics Co., Ltd. Flash memory device and method for programming flash memory device having leakage bit lines
US8947968B2 (en) * 2013-07-08 2015-02-03 Arm Limited Memory having power saving mode
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US20060209608A1 (en) * 2004-03-09 2006-09-21 Cruz Louis D L Sense amplifier systems and methods
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US20120287741A1 (en) * 2011-05-11 2012-11-15 Fujitsu Semiconductor Limited Semiconductor storage
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TWI466115B (zh) * 2012-07-20 2014-12-21 Elite Semiconductor Esmt 減少半導體記憶裝置待機電流之方法
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JP5073181B2 (ja) 2012-11-14
KR20060035235A (ko) 2006-04-26
US7724594B2 (en) 2010-05-25
KR100649834B1 (ko) 2006-11-28
JP2006120301A (ja) 2006-05-11
US20080151662A1 (en) 2008-06-26

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