GB2314951A - DRAM sense amplifier arrays - Google Patents
DRAM sense amplifier arrays Download PDFInfo
- Publication number
- GB2314951A GB2314951A GB9712287A GB9712287A GB2314951A GB 2314951 A GB2314951 A GB 2314951A GB 9712287 A GB9712287 A GB 9712287A GB 9712287 A GB9712287 A GB 9712287A GB 2314951 A GB2314951 A GB 2314951A
- Authority
- GB
- United Kingdom
- Prior art keywords
- sense amplifier
- pull
- bias voltages
- driver
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
A dynamic random access memory comprises first and second sense amplifier arrays, each including a sense amplifier 6, 26 for sensing/amplifying data on a bit line connected to a selected word line, a sense amplifier driver 9, 29 for generating pull-up and pull-down bias voltages to drive the sense amplifier, and an equalization transistor MN1, MN4 for equalizing the pull-up and pull-down bias voltages from the sense amplifier driver when the sense amplifier is not driven. The dynamic random access memory further comprises a signal transfer circuit 40 connected between the sense amplifiers in the first and second sense amplifier arrays, for switching the pull-up and pull-down bias voltages from the sense amplifier driver in the first sense amplifier array to the sense amplifier in the second sense amplifier array, and a control signal generator 41 for controlling the signal transfer circuit 40,the sense amplifier drivers 9, 29 and the equalization transistor MN1,MN4. After the first sensing operation is performed, the sense amplifier bias voltages with supply and ground voltage levels are transferred for the second sensing operation and then equalized. Therefore, current consumption can be reduced in the second sensing operation.
Description
DYNAMIC RANDOM ACCESS MEMORY
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates in general to a semiconductor memory device, and more particularly to a dynamic random access memory (referred to hereinafter as DRAM) which is capable of reducing power consumption in successive sensing operations.
The present invention is applicable to all semiconductor memory devices. More particularly, the present invention is applied to a DRAM which comprises a plurality of cells, each of which is provided with one transistor and one capacitor. Further, the present invention can reduce power consumption even in a selfrefresh operation of the DRAM.
Description of the Prior Art
Generally, a DRAM comprises a cell array block for storing data therein. The cell array block includes word lines and bit lines interconnected in the form of a net, and a plurality of cells connected to the word lines and bit lines, each of which is provided with one NMOS transistor and one capacitor.
A row decoder is adapted to select a desired one of the word lines in the cell array block. Namely, the row decoder selects one of the word lines in the cell array block corresponding to an input row address. The operation of the general DRAM will be described hereinafter.
When a row address strobe bar signal /RAS which is a main signal operating the DRAM is made active low in logic, the row decoder performs a row decoding operation. That is, the row decoder receives row address signals from a row address buffer and decodes the received row address signals. Then, the row decoder selects one of the word lines in the cell array block corresponding to the decoded result. Data from each of the cells connected to the selected word line are placed on true and complementary bit lines BL and /BL. At this time, a signal indicative of an operation time point of a bit line sense amplifier is enabled to operate a sense amplifier driver in the cell array block corresponding to the row address. As the sense amplifier driver is operated, sense amplifier bias voltages become a supply voltage level Vcc and a ground voltage level Vss, respectively, to drive the sense amplifier. As the sense amplifier is driven, a voltage difference between the true and complementary bit lines BL and /BL goes from low to high in level. Thereafter, a column decoder is selected by a column address to turn on a column transfer transistor. After being turned on, the column transfer transistor transfers the data on the true and complementary bit lines BL and /BL to true and complementary data bus lines DB and /DB, respectively.
In a standby mode before the DRAM begins to operate, the true and complementary bit lines BL and /BL are precharged with half a supply voltage level, i.e., Vcc/2, referred to hereinafter as "half voltage level". Thereafter, when the DRAM is operated, a small voltage difference is present between the true and complementary bit lines BL and /BL due to the transfer of cell data thereto.
Under this condition, the sense amplifier is driven in such a manner that the true and complementary bit lines BL and /BL with the small voltage difference can have the supply voltage level Vcc and the ground voltage level Vss, respectively. The data on the true and complementary bit lines BL and /BL, amplified as mentioned above, are transferred respectively to the true and complementary data bus lines DB and /DB in response to an output signal Yi from the column decoder. Then, a bit line equalization transistor equalizes the true and complementary bit lines B1 and /BL with the half voltage level Vcc/2 for the next operation.
In equalizing the true and complementary bit lines BL and /BL as mentioned above, the precharge operation is not directly performed in response to an external precharge command, but after the lapse of a predetermined delay time in response to an internal command, to prevent cell data from being damaged.
Fig. 1 is a partial circuit diagram of a conventional DRAM with a sense amplifier. As shown in this drawing, the DRAM comprises a memory cell array 1 including a plurality of memory cells 5, a row decoder 2 for selecting a word line in response to a row address, a sense amplifier 6 for sensing/amplifying data on true and complementary bit lines 3 and 4 connected to the selected word line, a sense amplifier driver 9 for generating pull-up and pull-down bias voltages SA~P and SA~N to drive the sense amplifier 6, an equalization transistor MN1 for equalizing the pull-up and pull-down bias voltages SA~P and SA~N from the sense amplifier driver 9 with a half voltage level Vcc/2 when the sense amplifier 6 is not driven, and data transfer transistors MN2 and MN3 for transferring the data on the true and complementary bit lines 3 and 4 respectively to true and complementary data bus lines 11 and 12 in response to an output signal Yi from a column decoder 10.
The sense amplifier 6 is provided with two latched inverters for amplifying data from the memory cell array 1 or from the true and complementary data bus lines 11 and 12 respectively to a supply voltage level Vcc and a ground voltage level Vss.
The operation of the conventional DRAM with the abovementioned construction will be described hereinafter.
In an active interval where the sense amplifier 6 is driven, the pull-up and pull-down bias voltages SA~P and SA~N from the sense amplifier driver 9 are maintained respectively at the supply voltage level Vcc and the ground voltage level Vss. Then, if the present mode enters a standby mode where the sense amplifier 6 is not driven, the equalization transistor MN1 is operated to equalize the pull-up and pull-down bias voltages SA~P and SA~N from the sense amplifier driver 9 with the half voltage level Vcc/2.
Noticeably, the pull-up and pull-down bias voltages SA~P and SA N with the supply and ground voltage levels Vcc and Vss are not used in other fields in the active interval, but directly enter the standby mode to be equalized with the half voltage level Vcc/2, resulting in an increase in the amount of current consumption.
Fig. 2 is a timing diagram illustrating a self-refresh operation of the conventional DRAM in Fig. 1, in which an internal operation signal is automatically produced. The above-mentioned current consumption is caused in the self-refresh operation which is similar to the normal operation. In Fig. 2, "ti" designates an interval between internal self-refresh operations, "N" designates the number of self-refresh cycles, and "t2" designates a refresh period.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problem, and it is an objective of the present invention to provide a DRAM in which, after the present sensing operation is performed, sense amplifier bias voltages with supply and ground voltage levels are transferred for the subsequent sensing operation and then equalized, so that current consumption can be reduced in the subsequent sensing operation.
In accordance with the present invention, the above and other objectives can be accomplished by a provision of a dynamic random access memory having first and second sense amplifier arrays, each of the first and second sense amplifier arrays including a sense amplifier for sensing/amplifying data on a bit line connected to a selected word line, a sense amplifier driver for generating pull-up and pull-down bias voltages to drive the sense amplifier, and equalization means for equalizing the pull-up and pull-down bias voltages from the sense amplifier driver when the sense amplifier is not driven, wherein the improvement comprises signal transfer means connected between the sense amplifiers in the first and second sense amplifier arrays, for switching the pull-up and pulldown bias voltages from the sense amplifier driver in the first sense amplifier array to the sense amplifier in the second sense amplifier array; and control signal generation means for controlling the signal transfer means, the sense amplifier drivers and the equalization means.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objectives, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a partial circuit diagram of a conventional DRAM with a sense amplifier;
Fig. 2 is a timing diagram illustrating a self-refresh operation of the conventional DRAM in Fig. 1;
Fig. 3 is a partial circuit diagram of a DRAM in accordance with an embodiment of the present invention; and
Fig. 4 is a timing diagram illustrating the operation of the
DRAM in Fig. 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. 3 is a partial circuit diagram of a DRAM in accordance with an embodiment of the present invention. As shown in this drawing, the DRAM comprises two sense amplifier arrays. Each of the sense amplifier arrays includes a memory cell array 1 or 21 having a plurality of memory cells 5 or 25, a row decoder 2 or 22 for selecting a word line in response to a row address, a sense amplifier 6 or 26 for sensing/amplifying data on true and complementary bit lines 3 or 23 and 4 or 24 connected to the selected word line, a sense amplifier driver 9 or 29 for generating pull-up and pull-down bias voltages SA~P and SA~N to drive the sense amplifier 6 or 26, an equalization transistor MN1 or MN4 for equalizing the pull-up and pull-down bias voltages SA~P and SA~N from the sense amplifier driver 9 or 29 with a half voltage level
Vcc/2 when the sense amplifier 6 or 26 is not driven, and data transfer transistors MN2 or MN5 and MN3 or MN6 for transferring the data on the true and complementary bit lines 3 or 23 and 4 or 24 respectively to true and complementary data bus lines 11 or 30 and 12 or 31 in response to an output signal Yi from a column decoder.
The DRAM further comprises a signal transfer circuit 40 connected between the sense amplifiers 6 and 26 in the first and second sense amplifier arrays, and a control signal generator 41 for controlling the signal transfer circuit 40, the sense amplifier drivers 9 and 29 and the equalization transistors MN1 and MN4.
The signal transfer circuit 40 is provided with a PMOS transistor MP1 and an NMOS transistor MN7.
The operation of the DRAM with the above-mentioned construction in accordance with the present invention will hereinafter be described in detail with reference to Fig. 4.
Fig. 4 is a timing diagram illustrating the operation of the
DRAM in Fig. 3. First, after the first sense amplifier array is operated, the pull-up and pull-down bias voltages SAP and SA~N from the sense amplifier driver 9 is not directly equalized but maintained at their voltage levels in an interval t3.
Then, in the sensing operation of the second sense amplifier array, the word line WL 2 is first driven in the interval t3, and the PMOS and NMOS transistors MP1 and MN7 of the signal transfer circuit 40 connected between the first and second sense amplifier arrays are then driven in an interval t4 to operate the sense amplifier driver 29 and sense amplifier 26 in the second sense amplifier array. Thereafter, the pull-up and pull-down bias voltages 7 and 8 in the first sense amplifier array are equalized.
Noticeably, in the sensing operation of the second sense amplifier array, the operating power is not directly obtained from the supply voltage source or ground voltage source, but first from charge sharing with the bias stage of the first sense amplifier array. Then, the sensing operation is performed by the sense amplifier driver 29 in the second sense amplifier array.
The following table 1 shows the pull-up and pull-down bias voltages of the first and second sense amplifier arrays.
TABLE 1
FIRST SA P FIRST SA~N SECOND SA~P SECOND SA N
INITIAL Vcc/2 Vcc/2 Vcc/2 Vcc/2
FIRST ARRAY
OPERATION Vcc gnd (Vcc) Vcc/2 Vcc/2
t4 (3/4)Vcc (l/4)Vcc (3/4)Vcc (1/4)Vcc
tS Vcc/2 Vcc/2 Vcc gnd (Vcc)
In the above table 1, "FIRST SA~P" indicates the pull-up bias voltage of the first sense amplifier array, "FIRST SA N" indicates the pull-down bias voltage of the first sense amplifier array, "SECOND SA P" indicates the pull-up bias voltage of the second
sense amplifier array, and "SECOND SA N" indicates the pull-down
bias voltage of the second sense amplifier array.
Each of the pull-up bias voltages SA~P of the first and second sense amplifier arrays have a (3/4)Vcc level in the interval t4.
The reason is that charge sharing occurs between the pull-up bias voltage SA~P of the first sense amplifier array which has the supply voltage level Vcc and the pull-up bias voltage SA~P of the second sense amplifier array which has the half voltage level
Vcc/2. Because the pull-up bias voltages SA~P of the first and second sense amplifier arrays are substantially the same in capacitance, the sum thereof has an intermediate voltage level.
As is apparent from the above description, according to the present invention, after the present sensing operation is performed, the sense amplifier bias voltages with the supply and ground voltage levels are transferred for the subsequent sensing operation and then equalized. Therefore, current consumption can be reduced in the subsequent sensing operation.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, . additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (4)
1. A dynamic random access memory having first and second sense amplifier arrays, each of said first and second sense amplifier arrays including a sense amplifier for sensing/amplifying data on a bit line connected to a selected word line, a sense amplifier driver for generating pull-up and pull-down bias voltages to drive said sense amplifier, and equalization means for equalizing said pull-up and pull-down bias voltages from said sense amplifier driver when said sense amplifier is not driven, wherein the improvement comprises:
signal transfer means connected between said sense amplifiers in said first and second sense amplifier arrays, for switching said pull-up and pull-down bias voltages from said sense amplifier driver in said first sense amplifier array to said sense amplifier in said second sense amplifier array; and
control signal generation means for controlling said signal transfer means, said sense amplifier drivers and said equalization means.
2. A dynamic random access memory as set forth in Claim 1, wherein said equalization means in said first sense amplifier array and said sense amplifier driver in said second sense amplifier array are operated after said signal transfer means is operated for a predetermined time period.
3. A dynamic random access memory as set forth in Claim 1, wherein said signal transfer means includes first and second MOS transistors.
4. A dynamic random access memory as set forth in Claim 3, wherein said first MOS transistor is of a P type and said second
MOS transistor is of a N type.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960025743A KR100203142B1 (en) | 1996-06-29 | 1996-06-29 | Dram |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9712287D0 GB9712287D0 (en) | 1997-08-13 |
| GB2314951A true GB2314951A (en) | 1998-01-14 |
| GB2314951B GB2314951B (en) | 2000-10-25 |
Family
ID=19464740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9712287A Expired - Fee Related GB2314951B (en) | 1996-06-29 | 1997-06-12 | Dynamic random access memory |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH1064267A (en) |
| KR (1) | KR100203142B1 (en) |
| GB (1) | GB2314951B (en) |
| TW (1) | TW326527B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1619688A1 (en) * | 2004-07-21 | 2006-01-25 | Dialog Semiconductor GmbH | Dynamical biasing of memory sense amplifiers |
| US7177213B2 (en) | 2004-08-13 | 2007-02-13 | Micron Technology, Inc. | Capacitor supported precharging of memory digit lines |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100298443B1 (en) * | 1998-08-18 | 2001-08-07 | 김영환 | Sense amp control circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943944A (en) * | 1987-11-25 | 1990-07-24 | Kabushiki Kaisha Toshiba | Semiconductor memory using dynamic ram cells |
| EP0499478A2 (en) * | 1991-02-14 | 1992-08-19 | Sharp Kabushiki Kaisha | Semiconductor memory unit array |
| EP0522361A2 (en) * | 1991-07-12 | 1993-01-13 | International Business Machines Corporation | Power saving sensing circuits for dynamic random access memory |
| GB2264376A (en) * | 1992-02-19 | 1993-08-25 | Samsung Electronics Co Ltd | Bit line control in a semiconductor memory device |
-
1996
- 1996-06-29 KR KR1019960025743A patent/KR100203142B1/en not_active IP Right Cessation
-
1997
- 1997-05-27 TW TW086107158A patent/TW326527B/en not_active IP Right Cessation
- 1997-06-12 GB GB9712287A patent/GB2314951B/en not_active Expired - Fee Related
- 1997-06-16 JP JP9158855A patent/JPH1064267A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943944A (en) * | 1987-11-25 | 1990-07-24 | Kabushiki Kaisha Toshiba | Semiconductor memory using dynamic ram cells |
| EP0499478A2 (en) * | 1991-02-14 | 1992-08-19 | Sharp Kabushiki Kaisha | Semiconductor memory unit array |
| EP0522361A2 (en) * | 1991-07-12 | 1993-01-13 | International Business Machines Corporation | Power saving sensing circuits for dynamic random access memory |
| GB2264376A (en) * | 1992-02-19 | 1993-08-25 | Samsung Electronics Co Ltd | Bit line control in a semiconductor memory device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1619688A1 (en) * | 2004-07-21 | 2006-01-25 | Dialog Semiconductor GmbH | Dynamical biasing of memory sense amplifiers |
| US7023750B2 (en) | 2004-07-21 | 2006-04-04 | Dialog Semiconductor Gmbh | Dynamical biasing of memory sense amplifiers |
| US7177213B2 (en) | 2004-08-13 | 2007-02-13 | Micron Technology, Inc. | Capacitor supported precharging of memory digit lines |
| US7423923B2 (en) | 2004-08-13 | 2008-09-09 | Micron Technology, Inc. | Capacitor supported precharging of memory digit lines |
| US7663952B2 (en) | 2004-08-13 | 2010-02-16 | Micron Technology, Inc. | Capacitor supported precharging of memory digit lines |
Also Published As
| Publication number | Publication date |
|---|---|
| KR980004961A (en) | 1998-03-30 |
| KR100203142B1 (en) | 1999-06-15 |
| TW326527B (en) | 1998-02-11 |
| JPH1064267A (en) | 1998-03-06 |
| GB9712287D0 (en) | 1997-08-13 |
| GB2314951B (en) | 2000-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20090612 |