TW326527B - Dynamic random access memory - Google Patents

Dynamic random access memory

Info

Publication number
TW326527B
TW326527B TW086107158A TW86107158A TW326527B TW 326527 B TW326527 B TW 326527B TW 086107158 A TW086107158 A TW 086107158A TW 86107158 A TW86107158 A TW 86107158A TW 326527 B TW326527 B TW 326527B
Authority
TW
Taiwan
Prior art keywords
sense amplifier
pull
random access
access memory
dynamic random
Prior art date
Application number
TW086107158A
Other languages
Chinese (zh)
Inventor
Jin Lee Jae
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW326527B publication Critical patent/TW326527B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A kind of dynamic random access memory comprises a first and a second sense amplifier arrays. Each of the first and the second sense amplifier arrays includes a sense amplifier for sensing/amplifying data on a bit line connected to a selected word line, a sense amplifier driver for generating pull-up and pull-down bias voltages to drive the sense amplifier, and an equalization transistor for equalizing the pull-up and pull-down bias voltages from the sense amplifier driver when the sense amplifier is not driven. It is characterized in that a signal transfer circuit is connected between the sense amplifiers in the first and second sense amplifier arrays for switching the pull-up and pull-down bias voltages from the sense amplifier driver in the first sense amplifier array to the sense amplifier in the second sense amplifier array, and a control signal generator is set for controlling the signal transfer circuit, the sense amplifier drivers and the equalization transistor.
TW086107158A 1996-06-29 1997-05-27 Dynamic random access memory TW326527B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025743A KR100203142B1 (en) 1996-06-29 1996-06-29 Dram

Publications (1)

Publication Number Publication Date
TW326527B true TW326527B (en) 1998-02-11

Family

ID=19464740

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086107158A TW326527B (en) 1996-06-29 1997-05-27 Dynamic random access memory

Country Status (4)

Country Link
JP (1) JPH1064267A (en)
KR (1) KR100203142B1 (en)
GB (1) GB2314951B (en)
TW (1) TW326527B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298443B1 (en) * 1998-08-18 2001-08-07 김영환 Sense amp control circuit
EP1619688A1 (en) 2004-07-21 2006-01-25 Dialog Semiconductor GmbH Dynamical biasing of memory sense amplifiers
JP2006054017A (en) 2004-08-13 2006-02-23 Micron Technology Inc Precharge by capacitor support of memory digit line

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells
JPH04258875A (en) * 1991-02-14 1992-09-14 Sharp Corp Semiconductor memory device
US5280452A (en) * 1991-07-12 1994-01-18 International Business Machines Corporation Power saving semsing circuits for dynamic random access memory
KR950009234B1 (en) * 1992-02-19 1995-08-18 삼성전자주식회사 Bit-line disconnection clock generating device of semiconductor memory device

Also Published As

Publication number Publication date
KR980004961A (en) 1998-03-30
GB2314951A (en) 1998-01-14
KR100203142B1 (en) 1999-06-15
JPH1064267A (en) 1998-03-06
GB9712287D0 (en) 1997-08-13
GB2314951B (en) 2000-10-25

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees