KR100693782B1 - Sense amp driver - Google Patents

Abstract

The present invention relates to a sense amplifier driver of a memory. The present invention relates to a memory for generating a first pull-up enable signal and a second pull-up enable signal, the potential of the high voltage level when the first pull-up enable signal is activated. Control signal generating means for outputting a signal as a control signal and outputting a potential level obtained by adding the threshold voltage of the transistor and the core voltage when the second pull-up enable signal is activated as a control signal; Pull-up means for outputting a voltage applied from the outside by the control signal to a pull-up line; Pull-down means which are activated at the same time as the pull-up means to pull down the pull-down line to ground level; And an equalizer means for occupying the pull-up line and the pull-down line as a precharge voltage when the pull-up means and the pull-down means are in an inactive state.

Sense Amplifier Drivers, Core Voltage, Bitline Sense Amplifiers

Description

Sense amp driver             

1A is a circuit diagram of a memory employing a conventional sense amplifier driver.

1B is a detailed circuit diagram of a conventional sense amplifier driver.

1C is an input / output waveform diagram of a conventional sense amplifier driver.

2A is a circuit diagram of a memory employing a sense amplifier driver according to the present invention.

2B illustrates an embodiment of a sense amplifier driver according to the present invention.

2C is an input / output waveform diagram of a sense amplifier driver according to the present invention.

* Explanation of symbols for the main parts of the drawings

100: control signal generation unit 200: pull-up unit

300: pull-down section 400: equalizer section

The present invention relates to a memory device, and more particularly to a sense amplifier driver of the memory.

In general, a semiconductor memory device uses a plurality of cells for storing data and a bit line sense amplifier for reading or writing data written in the plurality of cells. As the memory density becomes higher, the data of more cells must be amplified at the same time. In this situation, the load of the pull-up and pull-down devices of the bitline sense amplifier becomes larger, and the power supply voltage becomes smaller and smaller. In order to compensate for this, the voltage level of the "high" data to be written should be reduced for the stability of the bit line. In order to compensate for this problem, an external voltage and a core voltage are conventionally applied to the pull-up line (RTO) of the bit line sense amplifier. Generated the power used.

That is, in order to improve the amplification speed, the line RTO is increased to an external voltage Vext higher than the core voltage Vcore, and then the core voltage Vcore is applied to the line RTO.

1A is a partial circuit diagram of a memory device according to the related art, and includes a cell array unit connected to a bit line BL and a word line WL, and a bit line for amplifying a voltage difference between a pair of bit lines BL and / BL. A sense amplifier driver disposed between the sense amplifier array unit and the bit line sense amplifier array unit is shown in which a pull-up element, a source line, and an RTO of the sense amplifier drive the source line SB of the fall-down element.

1B shows a detailed circuit of a conventional sense amplifier driver.

Referring to FIG. 1B, a PMOS 11 for receiving a first pull-up enable signal rtoen0 as a gate and transferring an external voltage Vext to the line RTO, and a second pull-up enable signal rtpen1 as a gate are illustrated. A ground-up voltage Vss is transmitted to the line SB in response to a pull-up unit 10 configured as a PMOS 12 for receiving a core voltage Vcore to the line RTO and a pull-down enable signal sben. A pull-down unit 20 and an equalizer unit 20 which occupies the line RTO and the line SB as a bit line precharge voltage Vblp when the pull-up unit 10 and the pull-down unit 30 are in an inactive state. It is done by

The operation of the sense amplifier driver having the above configuration will be described with reference to FIG. 1C.

First, when the first pull-up enable signal rtoen0, the second pull-up enable signal rtoen1, and the pull-down enable signal sben are in an inactive state, the pull-up line RTO and the pull-down line SB are bits. It is occupied by the line precharge voltage Vblp.

The precharge voltage Vblp is a voltage at an intermediate level between the core voltage Vcore and the ground voltage Vss.

Subsequently, when a RAS (raw address strobe) command is applied, the word line (W / L) of the memory is activated after a predetermined time (t1), and cell data is transferred to the bit line, and a minute voltage is applied to the bit line pairs BL and / BL. The difference is generated and the equalizer signal eq is shifted to the low level so that the precharge voltage Vblp is not supplied to the pull-up line RTO and the pull-down line SB, so that the data of the cell is sufficiently loaded on the bit line between the t1 and t2 sections. Give you a time margin.

Subsequently, in order to obtain a fast sensing speed, the first pull-up enable signal rtoen0 transitions to a low level, and the line RTO begins to rise to the external voltage Vext, and the pull-down enable signal sben transitions to a high level. Line SB drops to ground voltage Vss.

The potential of the pull-up line RTO is increased by transferring the external voltage Vext to the pull-up line RTO, which is the t2 timing section of FIG. 1C.

Subsequently, the transistor 11 is inactivated by changing the first pull-up enable signal rtoen0 activated in the t2 timing section of FIG. 1C to a high level, and the second pull-up enable signal rtoen1 is activated to a low level, thereby enabling the core of the memory. The voltage Vcore will be supplied to the pull-up line RTO.

Accordingly, the conventional sense amplifier driver increases the potential of the pull-up line RTO by the first pull-up enable signal rtoen0 and pulls up the core voltage Vcore by the second pull-up enable signal rtoen1. The drive takes place.

On the other hand, the load of the pull-up line RTO, the source of the pull-up device of the plurality of bit line sense amplifiers is very large, and the method of increasing the size of the driver of the pull-up line RTO to increase the voltage of the pull-up line RTO quickly is ideal. As the memory is highly integrated, there are many limitations. In the conventional driving method of the sense amplifier driver, the pull-up line RTO is driven using only the PMOS 11 during the t3 to t3 timing period, and only after the t3, only the PMOS 12 is driven. Drive the pull-up line RTO.

Therefore, since the pull-up line RTO is driven up in two stages, the pull-up unit 10 is driven, so that the pull-up line RTO is not as efficient as the overall pull-up driver.

The present invention has been made to solve the conventional problems as described above, in driving the source line RTO of the pull-up element of the bit line sense amplifier, the pull-up driving of the source line RTO is driven using one pull-up driver The object is to provide a sense amplifier driver that improves efficiency.

The present invention relates to a sense amplifier driver of a memory. The present invention for this purpose, the present invention relates to a sense amplifier driver of a memory for the present invention, for generating a first pull-up enable signal and a second pull-up enable signal In the memory, when the first pull-up enable signal is activated, outputs a potential of a high voltage level as a control signal, and when the second pull-up enable signal is activated, outputs a potential level obtained by adding the threshold voltage of the transistor and the core voltage as a control signal. Control signal generating means; Pull-up means for outputting a voltage applied from the outside by the control signal to a pull-up line; Pull-down means which are activated at the same time as the pull-up means to pull down the pull-down line to ground level; And an equalizer means for occupying the pull-up line and the pull-down line as a precharge voltage when the pull-up means and the pull-down means are in an inactive state.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2B illustrates an embodiment of a sense amplifier driver according to the present invention.

Referring to FIG. 2B, in the memory generating the first pull-up enable signal rtoen0 and the second pull-up enable signal rtoen1, the potential VPP of the high voltage level when the first pull-up enable signal rtoen0 is activated. ) Is output as a control signal rtoen_new, and when the second pull-up enable signal rtoen1 is activated, the control signal rtoen_new is a potential level (Vcore + Vt) to which the core voltage Vcore and the threshold voltage Vt of the transistor are added. And a pull-up unit 200 for outputting a voltage Vext applied from the outside by the control signal rtoen_new to the pull-up line RTO, and a pull-up unit 200. At the same time, the pull-down unit 300 which pulls down the pull-down line SB to the ground level and the pull-up line RTO and the pull-down line SB are precharged when the pull-up unit 200 and the pull-down unit 300 are inactive. The equalizing unit 400 occupies.

In detail, the control signal generator 100 may include a PMOS 101 having one side connected to a high voltage and a gate connected to the first pull-up enable signal, and one side connected to a first voltage Vcore + Vt. PMOS 102 receiving a second pull-up enable signal rtoen1, one side of which is jointly connected to the other side of the PMOS 101 and the other side of the PMOS 102, and a gate of the first pull-up enable signal An NMOS 103 connected to rtoen0 and one side thereof are connected to the other side of the NMOS 103, and a gate thereof is connected to the second pull-up enable signal rtoen1 and the other side is grounded. Is composed,

The pull-up control unit 200 is composed of an NMOS 201, one side is connected to the external voltage, the gate is connected to the control signal, the other side is connected to the pull-up line,

The pull-down control unit 300 is configured to include an NMOS 301 having one side connected to the pull-down line SB, a gate connected to a pull-down enable signal sben, and the other side grounded.

The equalizer 400 includes an NMOS 401 having one side connected to a precharge voltage Vblp, a gate connected to an equalizer enable signal eq, and the other side connected to a pull-up line RTO, and one side of the equalizer 400. An NMOS 402 connected to the charge voltage Vblp, the other end connected to a pull-down line SB, and the gate connected to an equalizer enable signal eq, and in series with the pull-up line RTO and pull-down line SB. And a gate is implemented with an NMOS 403 coupled to the equalizer enable signal.

The operation of the present invention having the above configuration will be described in detail with reference to FIGS. 2A and 2C.

Figure 2a is a diagram showing that the sense amplifier driver of the present invention is applied to the actual memory, it can be seen that only the external voltage is driven by not using the core voltage of the memory.

FIG. 2B is a detailed circuit diagram of the sense amplifier of the present invention shown in FIG. 2A.

First, when the first pull-up enable signal rtoen0, the second pull-up enable signal rtoen1, and the pull-down enable signal sben are in an inactive state, the pull-up line RTO and the pull-down line SB are It is occupied by the bit line precharge voltage Vblp.

Subsequently, when a RAS (raw address strobe) command is applied to the memory, after a predetermined time (t1), the word line (W / L) of the memory is activated, and the equalizer signal (eq) transitions to the low level so that the pull-up line (RTO) The precharge voltage Vblp is not supplied to the pull-down line SB.

Subsequently, when cell data is transmitted to the bit line after the word line W / L is activated, the first pull-up enable signal rtoen0 generated in the memory transitions to a low level to turn on the PMOS 101. By turning on, the control signal rtoen_new of the high voltage VPP level is generated.

As shown in FIG. 2C, the control signal rtoen_new maintains a high voltage Vpp initially (t2) in order to increase the response speed of the NMOS 201, but after a predetermined time delay (t3), the first voltage Vpp + Vt. ).

Here, the high voltage Vpp refers to a voltage higher than the external voltage Vext by the threshold voltage of the PMOS 101.

At this time, when the control signal rtoen_new transitions to a high level, the NMOS 103 and the NMOS 104 are turned off.

Subsequently, the high level control signal rtoen_new is input to the gate of the NMOS 201 so that an external voltage Vext is applied to the pull-up line, and the pull-down enable signal sben is also controlled as shown in FIG. 2C. Since it is activated to the high level at the rising edge of the signal rtoen_new and is deactivated to the low level at the falling edge of the control signal rtoen_new, the pull-down line SB is brought low when the pull-up line RTO is charged to the external voltage Vext. Occupy the level.

At this time, the voltage waveform of the pull-up line (RTO) is the potential of the pull-up line (RTO) in the t2 period by the external voltage (Vext) as shown in Figure 2c, after a certain time (after t3) the core of the memory The voltage drops to the Vcore level. Unlike the related art, since the core voltage Vcore of the memory is not directly connected to the pull-up line RTO, it does not affect the core voltage Vcore of the memory and the core voltage Vcore. Since there is no fluctuation of), the operation characteristic of the memory becomes stable and there is no characteristic of current waste when overdriving the memory.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation.

In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the present invention, in the pull-up line pull-up as described above, by implementing a sense amplifier driver that does not use the core voltage of the memory, the unnecessary current is consumed due to the increase of the core voltage, and the change of the memory core voltage is not generated. By doing so, the stability of the memory operation is increased.

Claims (5)

A memory for generating a first pull-up enable signal and a second pull-up enable signal, Control signal generating means for outputting a potential of a high voltage level as a control signal when the first pull-up enable signal is activated and outputting a potential level obtained by adding the threshold voltage of the transistor and the core voltage as a control signal when the second pull-up enable signal is activated. ; Pull-up means for outputting a voltage applied from the outside by the control signal to a pull-up line; Pull-down means which are activated at the same time as the pull-up means to pull down the pull-down line to ground level; And Equalizer means for occupying the pull-up line and the pull-down line as a precharge voltage when the pull-up means and the pull-down means are in an inactive state. A sense amplifier driver having a. The method of claim 1, The control signal generating means, A first PMOS connected at one side to a high voltage and receiving a gate of the first pull-up enable signal; A second PMOS having one side connected to a first voltage and a gate receiving a second pull-up enable signal; A first NMOS coupled to one side of the first PMOS and the other side of the second PMOS, and having a gate connected to the first pull-up enable signal; And And a second NMOS having one side connected to the other side of the first NMOS, a gate connected to the second pull-up enable signal, and the other side grounded. The method of claim 1, The pull-up means, And a third NMOS connected at one side to an external voltage, at a gate thereof to the control signal, and at the other side to a pull-up line. The method of claim 1, The pull-down means, And a fourth NMOS, wherein one side is connected to the pull-down line, the gate is connected to a pull-down enable signal, and the other side is grounded. The method of claim 2, The first voltage is, And a core voltage of a memory and a threshold voltage of the second PMOS.

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