KR20110011832A - Senseamp and driving method of the same - Google Patents

Abstract

PURPOSE: A sense amp and a driving method of the same are provided to improve the operation property of a sense amplifier by preventing the data of a bit line being inversed in a reading operation. CONSTITUTION: A sense amplifier(100) senses the voltage of a bit line. The sense amplifier enables the bit line to be pulled up down according to a sensing result. A pull up voltage supply unit(300) supplies a pull up voltage to the sense amplifier. A pull down voltage supply unit(400) supplies a pull down voltage to the sense amplifier and converts it into a negative voltage.

Description

Sense amplifier device and its driving method {SENSEAMP AND DRIVING METHOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier device of a semiconductor memory, and more particularly, to a sense amplifier device and a method of driving the same which can further stabilize the operating characteristics of the sense amplifier by variably adjusting a pull-down voltage supplied to the sense amplifier. .

The semiconductor memory device includes a sense amplifier for sensing data, and the sense amplifier is driven by a pull-up voltage and a pull-down voltage to sense and amplify data transferred through a pair of bit lines.

At this time, the sense amplifier performs an overdrive operation to perform a fast and stable amplification operation.

1 is a circuit diagram showing the configuration of a conventional sense amplifier device.

When the word line is enabled, the sense amplifier device senses and amplifies the cell data carried on the bit line pair BL and / BL through the bit line pair according to the sense amplifier 10 and the pull-up driving signals SAP1, SAP2 and the pull-down driving signal SAN. And a sense amplifier driver 20 for supplying a pull-up voltage and a pull-down voltage for amplifying the transferred cell data to the sense amplifier 10.

FIG. 2 illustrates operation waveforms of the bit line pairs BL and / BL for the pull-up and pull-down control signals. Referring to FIG. 2, the operation of the sense amplifier will be described below.

When the word line is enabled and the cell is selected, data of the selected cell is transferred to the bit line BL by charge sharing, thereby generating a voltage difference of ΔV between the bit line BL and the bit bar line / BL. .

Next, when the pull-up control signal SAP1 and the pull-down control signal SAN are enabled, the NMOS transistors N1 and N3 are turned on so that the pull-up node RTO is supplied with a power supply voltage VDD higher than the core voltage VCORE and the ground-down voltage VSS is supplied to the pull-down node SB. do. As a result, during the initial operation of the sense amplifier 10, the voltage level of the bit line BL is immediately overdriven to the power supply voltage VDD level, and the voltage level of the bit bar line / SB starts to fall toward the ground voltage VSS level.

Next, the pull-up control signal SAP1 is disabled, the NMOS transistor N1 is turned off, the pull-up control signal SAP2 is enabled, and the NMOS transistor N3 is turned on so that the core voltage VCORE is supplied to the pull-up node RTO.

As a result, the final voltage of the bit line BL is developed at the core voltage VCORE level and the voltage of the bit line bar / BL is developed at the ground voltage VSS level.

As such, the sense amplifier device temporarily supplies the driving voltage VDD at a level higher than the core voltage VCORE before supplying the core voltage VCORE to the pull-up node RTO of the sense amplifier 10 during the initial operation of the sense amplifier 10. Overdriving the BL improves the memory development speed.

Next, when the column select signal YI is enabled, the NMOS transistors N4 and N5 are turned on to transfer the data of the developed bit lines BL and / BL to the data bus SIO and SIOB.

However, since the data buses SIO and SIOB are precharged to the core voltage VCORE level, when transistors N4 and N5 are turned on, current flows from the data bus SIO, which is the core voltage VCORE level, to the bit line / BL which is the ground voltage VSS level. The voltage level of BL rises. The voltage of the bit bar line / BL is also lower than the core voltage VCORE level by the latch operation of the sense amplifier. That is, the voltage of the bit line BL increases and the voltage of the bit bar line / BL decreases.

When this phenomenon is intensified, the voltage levels of the bit line pairs BL and / BL are inverted, and when the sense amplifier 10 performs the latch operation while the voltage levels are inverted, the bit line pairs BL and / BL are as shown in FIG. Likewise, it is developed with the opposite data. Then, after the data is opposite the output to re-read (READ 2 ^nd) to the data latched in the sense amplifier it will cause a defect.

An object of the present invention to solve the above problem is to improve the device of the sense amplifier by converting the level of the pull-down voltage to a negative voltage when the data of the bit line is transferred to the data bus by the voltage of the data bus during the read operation This prevents the voltage on the bit line from reversing, improving the sense amplifier's operating characteristics.

According to an embodiment of the present invention, a sense amplifier device senses a voltage of a bit line and pulls up or pulls down a bit line according to a sensing result, a pull-up voltage supply unit supplying a pull-up voltage to a sense amplifier, and a pull-down voltage to a sense amplifier. It supplies a but the pull-down voltage supply for changing the pull-down voltage to a negative voltage when the sensing result of the sense amplifier is transferred to the data bus.

As such, the present invention converts the pull-down voltage of the sense amplifier into a negative voltage when the data sensed by the sense amplifier is transferred to the data bus, thereby preventing the voltage of the bit line from being reversed by the voltage of the data bus during the read operation. Improves the operating characteristics of the sense amplifier.

In the sense amplifier device of the present invention, the pull-down voltage supply unit selectively supplies a ground voltage or a negative voltage to the sense amplifier according to the first pull-down control signal and the second pull-down control signal. The pull-down voltage supply unit supplies the ground voltage to the sense amplifier when the second pull-down control signal is enabled while the first pull-down control signal is disabled, and the first pull-down control when the first pull-down control signal is enabled. A negative voltage is supplied to the sense amplifier regardless of the state of the signal.

The pull-down voltage supply unit selects a ground voltage to the sense amplifier according to a logic combination of the first switching unit and the first pull-down control signal and the second pull-down control signal to selectively supply a negative voltage to the sense amplifier according to the first pull-down control signal. It may include a second switching unit for supplying.

In the sense amplifier device of the present invention, the pull-up voltage supply unit may selectively supply a normal driving voltage or an overdriving voltage to the sense amplifier according to the first pull-up control signal and the second pull-up control signal.

The sense amplifier device of the present invention may further include a data transfer unit for transmitting the sensing result of the sense amplifier to the data bus according to the first pull-down control signal, wherein the first pull-down control signal is a column selection signal enabled only in the read mode. Can be.

The sense amplifier driving method according to an embodiment of the present invention is a first step of sensing the voltage difference between the bit line and the bit bar line, the first step to pull up or pull down the bit line and bit bar line according to the sensing result to amplify the sensing result A second step and a third step of converting the pulled-down line of the bit line and the bit bar line to the negative voltage level when transferring the amplified sensing result to the data bus.

In the second step of the sense amplifier driving method of the present invention, the pull-up line between the bit line and the bit bar line is overdriven, and the ground voltage is supplied to the pull-down line between the bit line and the bit bar line. In the third step, a negative voltage may be supplied when the column selection signal of the read mode is activated.

The present invention improves the operation characteristics of the sense amplifier by easily and effectively preventing the problem of inverting the data of the bit line by the current flowing into the bit line from the data bus during the read operation.

Hereinafter, with reference to the accompanying drawings will be described in detail preferred embodiments of the present invention.

4 is a circuit diagram showing the configuration of a sense amplifier device according to an embodiment of the present invention. For convenience of description, the same reference numerals are given to the same elements as those of FIG. 1 described above with reference to FIG. 4.

The sense amplifier device of FIG. 4 includes a sense amplifier 100, a data transfer unit 200, a pull-up voltage supply unit 300, and a pull-down voltage supply unit 400.

The sense amplifier 100 senses and amplifies cell data loaded on the bit line pairs BL and / BL in the read mode. That is, the sense amplifier 100 uses the voltage difference generated in the bit line pairs BL and / BL by charge sharing of the capacitances of the capacitors of the selected cell and the bit lines BL and / BL on which the cell data is to be loaded. Sensing data The sense amplifier 100 converts the voltage of the bit line BL or the bit bar line / BL into a pull-up voltage or pull-down voltage using the pull-up voltage and the pull-down voltage provided from the pull-up voltage supply unit 300 and the pull-down voltage supply unit 400. Amplify.

The data transfer unit 200 transmits the cell data amplified by the sense amplifier 100 on / off according to the pull-down control signal YI_RD to the data buses SIO and SIOB. In this case, the pull-down control signal YI_RD may use a signal enabled in the read mode in which the cell data amplified by the sense amplifier 100 is transferred to the data buses SIO and SIOB. To this end, according to an exemplary embodiment of the present invention, the column selection signal is divided into a column selection signal enabled in the write mode and a column selection signal enabled in the read mode, and then the column selection signal enabled in the read mode is divided. Can be used as pull-down control signal YI_RD. Alternatively, the pull down control signal YI_RD separate from the column selection signal may be generated using the read command signal. The data transfer unit 200 includes NMOS transistors N6 and N7 connected between the output nodes SL and / SL of the sense amplifier 100 and the data buses SIO and SIOB and turned on / off according to the pull-down control signal YI_RD.

The pull-up voltage supply unit 300 supplies pull-up voltages VCORE and VDD for cell data amplification in the sense amplifier 100 to the pull-up node RTO of the sense amplifier 100 according to the pull-up control signals SAP1 and SAP2. At this time, the pull-up voltage supply unit 300 is an overdriving voltage of a level higher than the core voltage VCORE when the pull-up voltage is supplied to the sense amplifier 100 to improve the development speed of the bit line BL or bit bar line / BL during the pull-up operation. After supplying VDD temporarily, the core voltage VCORE can be supplied as a normal driving voltage. The pull-up voltage supply unit 200 is turned on / off according to the pull-up control signal SAP1 to selectively supply the overdriving voltage VDD to the pull-up node RTO of the sense amplifier 100 and on / off according to the pull-up control signal SAP2. And an NMOS transistor N2 for selectively supplying the normal overdriving voltage VCORE to the pull-up node RTO of the sense amplifier 100.

The pull-down voltage supply unit 400 pulls down the pull-down voltage VSS for amplifying the cell data in the sense amplifier 100 or the negative voltage VBBW for preventing data reversal of the bit line according to the pull-down control signal YI_RD and SAN. Supply to node SB. That is, when the cell data is amplified in the sense amplifier 100 according to the pull-down control signal YI_RD and SAN, the pull-down voltage supply unit 400 supplies a pull-down voltage VSS to the pull-down node SB of the sense amplifier 100 and the amplified cell data is data. When delivered to the bus SIO, SIOB, a negative voltage VBBW is supplied to the pull-down node SB. The pull-down voltage supply unit 400 is turned on / off according to an output signal of an AND gate AND and an AND gate AND that outputs an AND of an inverter IV for inverting the pull-down control signal YI_RD and an output signal / YI_RD of the inverter IV and a pull-down control signal SAN. And on / off according to the NMOS transistor N8 and the pulldown control signal YI_RD which selectively supply the pulldown voltage VSS to the pulldown node SB of the sense amplifier 100, and selectively supply the negative voltage VBBW to the pulldown node SB of the sense amplifier 100. NMOS transistor N9.

FIG. 5 is a timing diagram for describing an operation of the sense amplifier device of FIG. 4. Referring to Figure 5 describes the operation of the sense amplifier device according to the present invention.

In the precharge period before the word line is enabled, the pull-up node RTO and the pull-down node SB of the bit line pair BL, / BL, and the sense amplifier 100 are precharged to the half-core voltage Half_VCORE level.

When the word line is enabled and a specific cell is selected, the cell data is transferred to the bit line BL by charge sharing, thereby generating a voltage difference of ΔV between the bit line BL and the bit bar line / BL.

Next, when the pull-up control signal SAP1 and the pull-down control signal SAN are enabled, the NMOS transistors N1 and N8 are turned on to supply the pull-up node RTO of the sense amplifier 100 with a power supply voltage VDD of a level higher than the core voltage VCORE, that is, an overdriving voltage. The ground voltage VSS is supplied to the pull-down node SB. As a result, in the initial operation of the sense amplifier 10, the voltage level of the bit line BL is overdriven to the power supply voltage VDD level in an instant and the voltage level of the bit bar line / BL begins to gradually decrease.

Next, the pull-up control signal SAP1 is disabled, the NMOS transistor N1 is turned off, the pull-up control signal SAP2 is enabled, and the NMOS transistor N2 is turned on so that the core voltage VCORE, that is, the normal driving voltage is supplied to the pull-up node RTO.

As a result, the final voltage of the bit line BL is developed at the core voltage VCORE level and the voltage of the bit line bar / BL is developed at the ground voltage VSS level.

Next, when the pull-down control signal YI_RD is enabled, the NMOS transistors N6 and N7 are turned on to transfer the data of the developed bit line pairs BL and / BL to the data bus SIO and SIOB. At this time, since the NMOS transistor N9 of the pull-down voltage supply unit 400 is turned on and the NMOS transistor N8 is turned off, the negative voltage VBBW is supplied to the pull-down node SB of the sense amplifier 100 so that the voltage level of the bit bar line / BL is negative. Is converted. That is, when the NMOS transistors N6 and N7 are turned on and the data of the bit line pairs BL and / BL are transferred to the data buses SIO and SIOB, a negative voltage is supplied to the pull-down node SB of the sense amplifier 100 to supply the bit line / BL. It converts the voltage level to a voltage level lower than the ground voltage VSS.

As such, by lowering the voltage level of the bit bar line / BL to a voltage level lower than the ground voltage VSS, current flows from the data bus SIOB to the bit bar line / BL in the process of transferring data to the data bus SIO and SIOB. Even if the voltage level of the BL is slightly higher, the data reversal phenomenon between the bit line BL and the bit bar line / BL does not occur as shown in FIG. 6.

1 is a circuit diagram showing the configuration of a conventional sense amplifier device.

FIG. 2 is a diagram illustrating operation waveforms of a pair of bit lines for pull-up and pull-down driving signals in the sense amplifier device of FIG. 1. FIG.

FIG. 3 is a diagram illustrating a data reversal phenomenon occurring in the read mode in the configuration of FIG. 1. FIG.

4 is a circuit diagram showing a configuration of a sense amplifier device according to an embodiment of the present invention.

FIG. 5 is a timing diagram for describing an operation of the sense amplifier device of FIG. 4.

6 is a diagram illustrating that no data reversal occurs in the read mode through the configuration of FIG. 4;

Claims (12)

A sense amplifier configured to sense a voltage of a bit line and pull up or pull down the bit line according to a sensing result; A pull-up voltage supply unit supplying a pull-up voltage to the sense amplifier; And a pull-down voltage supply unit configured to supply a pull-down voltage to the sense amplifier and change the pull-down voltage to a negative voltage when a sensing result of the sense amplifier is transmitted to a data bus. The method of claim 1, wherein the pull-down voltage supply unit And a ground voltage or a negative voltage is selectively supplied to the sense amplifier according to a first pull-down control signal and a second pull-down control signal. 3. The method of claim 2, And a data transfer unit configured to transfer a sensing result of the sense amplifier to the data bus according to the first pull-down control signal. The method of claim 2 or 3, wherein the first pull-down control signal is And a column select signal enabled only in the read mode. The method of claim 2, wherein the pull-down voltage supply unit And when the second pull-down control signal is enabled while the first pull-down control signal is disabled, supplying the ground voltage to the sense amplifier. The method of claim 2 or 5, wherein the pull-down voltage supply unit And when the first pull-down control signal is enabled, supplying the negative voltage to the sense amplifier regardless of the state of the first pull-down control signal. The method of claim 2, wherein the pull-down voltage supply unit A first switching unit selectively supplying a negative voltage to the sense amplifier according to the first pull-down control signal; And And a second switching unit for selectively supplying the ground voltage to the sense amplifier according to a logical combination of the first pulldown control signal and the second pulldown control signal. The method of claim 1, wherein the pull-up voltage supply unit And a sensor for selectively supplying a normal driving voltage or an overdriving voltage to the sense amplifier according to a first pull-up control signal and a second pull-up control signal. Sensing a voltage difference between the bit line and the bit bar line; A second step of amplifying the sensing result by pulling up or pulling down the bit line and the bit bar line according to the sensing result; And And a third step of converting a pulled down line of the bit line and the bit bar line to a negative voltage level when transferring the amplified sensing result to the data bus. 10. The method of claim 9, wherein the second step is And overdriving the pull-up line among the bit line and the bit bar line. 10. The method of claim 9, wherein the second step is And a ground voltage is supplied to a line pulled down between the bit line and the bit bar line. 12. The method of claim 11, wherein the third step is And supplying the negative voltage when the column selection signal of the read mode is activated.

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