KR100976407B1 - Semiconductor memory device and operation method thereof - Google Patents

Abstract

According to the present invention, a sensing amplifier means for sensing and amplifying data transmitted to a data line by receiving power through a pull-up driving line and a pull-down driving line, and a high potential voltage having a characteristic that a voltage level decreases as an external power supply voltage increases. A high potential voltage generating means for generating a voltage, an overdriving driving means for driving the pull-up driving line to an external power supply voltage in response to an overdriving control signal activated by the high potential voltage, and the pull-down in response to a pull-down control signal Provided is a semiconductor memory device having pull-down driving means for driving a driving line to a ground power supply voltage.

Overdriving, Pullup Power Line, Pulldown Power Line, Sense Amplifier

Description

Semiconductor memory device and driving method thereof {SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device having a sense amplifier employing an over driving method in sensing and amplifying data transmitted through a data line. It is about a method.

In general, semiconductor memory devices, including DDR Double Data Rate Synchronous DRAM (DDR SDRAM), have more than tens of millions of memory cells for storing data, and the data is processed according to the instructions required by the CPU. Save or output the data. That is, when the CPU requests a write operation, the CPU stores data in a memory cell corresponding to an address input from the CPU, and when the CPU requests a read operation, the memory corresponds to an address input from the CPU. Output the data stored in the cell. In other words, data input from an external device during a write operation is input to a memory cell via a data input path through an input / output pad, and data stored in the memory cell during an read operation is input through an input / output pad via a data output path. Is output.

On the other hand, semiconductor memory devices have become increasingly integrated these days, and sub-micron or lower design-rules are applied to design internal circuits. Memory cells are also designed accordingly, and the amount of charge stored therein is very small. Therefore, in order to determine such a small amount of charge externally, a circuit for sensing and amplifying it is required, and this role is performed by a sense amplifier mounted inside the semiconductor memory device.

1 is a diagram for describing a general read operation and a write operation of a semiconductor memory device. For reference, more than tens of millions of memory cells are designed in the semiconductor memory device. For convenience of description, one memory cell is illustrated and a reference numeral '110' is assigned thereto.

A simple read operation of the semiconductor memory device will be described with reference to FIG. 1.

First, when a selected word line WL is activated by decoding a row address input according to an external command signal, a cell transistor T1 of the memory cell 110 is turned on. on), and the data stored in the cell capacitor C1 is charge-shared to the precharged positive / negative bit lines BL and / BL. The positive bit line BL and the sub bit line / BL have a small potential difference through a charge sharing operation. For reference, the precharged voltage level has a ½ voltage level of the core voltage, which is an internal power supply voltage.

Subsequently, the bit line sense amplifier 120 senses and amplifies a small potential of the positive bit line BL and the corresponding sub bit line / BL. In other words, when the potential of the positive bit line BL is higher than the potential of the negative bit line / BL, the positive bit line BL is amplified by the pull-up power supply voltage applied to the pull-up power line RTO and the negative bit line ( BL) is amplified by the pull-down power supply voltage applied to the pull-down power supply line SB. On the contrary, when the potential of the positive bit line BL is lower than the potential of the negative bit line / BL, the positive bit line BL is amplified by the pull-down power supply voltage and the negative bit line / BL is amplified by the pull-up power supply voltage. .

Meanwhile, when the selected column select signal YI is decoded by decoding a column address input according to an external command signal, the column selector 130 is activated to operate with the positive and negative bit lines BL and / BL. Positive and negative segment input and output lines (SIO, / SIO) are connected. That is, the data amplified on the positive bit line BL is transferred to the positive segment input / output line SIO, and the data amplified on the negative bit line / BL is transferred to the sub segment input / output line / SIO.

Subsequently, when the input / output switching unit 140 is activated in response to the input / output control signal CTR_IO, the positive / negative segment input / output lines SIO and / SIO and the positive / negative local input / output lines LIO and / LIO are connected. That is, the data transmitted to the positive segment input / output line SIO is transmitted to the positive local input / output line LIO, and the data transmitted to the secondary segment input / output line / SIO is transmitted to the secondary local input / output line / LIO. The read driving unit 150 drives the global input / output line GIO according to data transmitted through the positive / negative local I / O lines LIO and / LIO.

As a result, the data stored in the memory cell 110 is amplified in the positive and negative bit lines BL and / BL and transferred to the positive and negative segment input and output lines SIO and / SIO, and the positive and negative segment input and output lines SIO and / SIO) is transmitted to the positive and negative local I / O lines (LIO, / LIO) in response to the column selection signal (YI), the data transmitted to the positive / negative local I / O lines (LIO, / LIO) In response to the input / output control signal CTR_IO, the signal is transmitted to the global input / output line GIO. The data thus delivered is finally output to the outside through a corresponding input / output pad (not shown).

On the other hand, the data applied from the outside during the write operation is transferred in the opposite direction to the read operation. That is, data applied through the input / output pad is positive / negative local I / O lines (LIO, / LIO) from the global input / output line (GIO) through the write driving unit 160, and positive / negative local I / O lines (LIO, / LIO). ) From the positive / negative segment input / output lines (SIO, / SIO) to the positive / negative segment input / output lines (SIO, / SIO) to the positive / negative bit lines (BL, / BL). The data thus transferred is finally stored in the memory cell 110.

On the other hand, semiconductor memory devices have evolved in order to perform faster operations. The most common method for increasing the operation speed of a semiconductor memory device is to increase the frequency of an external clock signal applied from the outside. However, this method has reached a certain limit due to the time inevitably delayed in the internal operation of the semiconductor memory device. Therefore, in recent years, efforts are being made to improve the internal operation of the semiconductor memory device to ensure faster operation, one of which is an overdriving method. This overdriving method is used for pull-up power lines (RTO). Another reason for using this overdriving method will be discussed below.

FIG. 2 is a diagram for describing a configuration related to driving the pull-up power line RTO and the pull-down power line SB of FIG. 1.

2 illustrates a driving controller 210, a power line driver 230, an internal power voltage generator 250, a bit line detection amplifier 270, and a word line driver 290.

The driving controller 210 may include a pull-up control signal SAP1, a pull-down control signal SAN, a bit line equalization control signal BLEQ in response to the first to fourth activation signals EN1, EN2, EN3, and EN4. And generates an overdriving control signal SAP2. Herein, the first to fourth activation signals EN1, EN2, EN3, and EN4 are signals that are activated at a predetermined time during an active operation of the semiconductor memory device.

The power line driver 230 is configured to perform a predetermined operation under the control of the pull-up control signal SAP1, the pull-down control signal SAN, the bit line equalization control signal BLEQ, and the overdriving control signal SAP2. The power line driver 230 may pull up and pull down the pull-up power line RTO and the pull-down power line SB in response to the pull-up control signal SAP1 and the pull-down control signal SAN. perform a pull down operation and perform an equalization operation of the pull-up power line RTO and the pull-down power line SB in response to the bit line equalization control signal BLEQ, followed by a precharge operation. In response to the overdriving control signal SAP2, the overdriving operation is performed.

Meanwhile, various internal power supply voltages are applied to the drive control unit 210 and the power line driver 230. For reference, a semiconductor memory device may be equipped with an internal power supply voltage generation circuit, and the semiconductor memory device may be guaranteed more efficient power consumption and more stable circuit operation by using internal power supply voltages having various voltage levels generated therein. The internal power supply voltage includes a core voltage generated by down converting the external power supply voltage, a peri voltage and a precharge voltage, and an external power supply voltage and a ground power supply voltage. There are a pumping voltage, which is a high potential voltage generated by pumping, and a substrate via voltage, which is a low potential voltage.

The internal power supply voltage generator 250 includes a precharge power supply voltage generator 252 for generating a precharge power supply voltage VBLP, a core power supply voltage generator 254 for generating a core power supply voltage VCORE, and pumping. A pumping power supply voltage generation unit 256 for generating a power supply voltage VPP is provided. The precharge power supply voltage VBLP, the core power supply voltage VCORE, and the pumping power supply voltage VPP generated by the internal power supply voltage generator 250 may include a drive controller 210, a power line driver 230, and The word line driver 290 is applied.

The bit line detection amplifier 270 detects data transferred to the positive and negative bit lines BL and / BL using power applied to the pull-up power line RTO and the pull-down power line SB according to an operation. In order to amplify the signal, the configuration of the bit line sense amplifier 270 is illustrated in 120 of FIG. 1.

Finally, the word line driver 290 receives the pumping power voltage VPP to drive the word line WL.

3 is a block diagram illustrating the driving control unit 210 of FIG. 2.

Referring to FIG. 3, the driving controller 210 may include a first control signal generator 310 for generating a pull-up control signal SAP1 in response to the first activation signal EN1, and a second activation signal EN2. In response to the second control signal generator 330 for generating the overdriving control signal SAP2 and generating a third control signal for generating the pull-down control signal SAN in response to the third activation signal EN3. And a fourth control signal generator 370 for generating the bit line equalization control signal BLEQ in response to the fourth activation signal EN4.

Here, since the first and second control signal generators 310 and 330 receive the pumping power supply voltage VPP and the ground power supply voltage VSS, the pull-up control signal SAP1 and the overdriving control signal SAP2 It has a voltage level corresponding to the pumping power supply voltage VPP and the ground power supply voltage VSS. Since the third and fourth control signal generators 350 and 370 receive the external power supply voltage VDD and the ground power supply voltage VSS, the pull-down control signal SAN and the bit line equalization control signal BLEQ. Has a voltage level corresponding to the external power supply voltage VDD and the ground power supply voltage VSS.

4 is a circuit diagram illustrating the power line driver 230 of FIG. 2.

Referring to FIG. 4, the power line driver 230 includes a pull-up driver 410, an overdriving driver 430, a pull-down driver 450, and an equalizer 470.

The pull-up driver 410 drives the pull-up power line RTO to the core power voltage VCORE in response to the pull-up control signal SAP1, and the overdrive driver 430 pulls up in response to the over-driving control signal SAP2. The power line RTO is driven by an external power supply voltage VDD.

Subsequently, the pull-down driver 450 drives the pull-down power line SB to the ground power voltage VSS in response to the pull-down control signal SAN, and the equalizer 470 responds to the bit line equalization control signal BLEQ. As a result, the pull-up power supply line RTO and the pull-down power supply line SB are driven to the precharge power supply voltage VBLP.

Hereinafter, the precharging operation, the overdriving operation, and the normal driving operation of the power line driver 230 will be described.

First, in the overdriving operation, the pull-up power line RTO is driven to the external power supply voltage VDD in response to the overdriving control signal SAP2, and the pull-down power supply line SB is driven to the ground power supply voltage VSS. At this time, since the bit line equalization control signal BLEQ is logic 'low', the equalization unit 470 is deactivated.

Next, in the normal driving operation, the pull-up power line RTO is driven by the core power supply voltage VCORE in response to the pull-up control signal SAP1, and the pull-down power supply line SB is driven by the ground power supply voltage VSS. At this time, the equalizer 470 is also deactivated.

Finally, in the precharging operation, the pull-up power supply line RTO and the pull-down power supply line SB are driven with the precharge power supply voltage VBLP in response to the bit line equalization control signal BLEQ. In this case, since both the pull-up control signal SAP1, the overdriving control signal SAP2, and the pull-down control signal SAN become logic 'low', the pull-up driving unit 410, the over-driving driving unit 430, and the pull-down driving unit 450. Is deactivated.

As a result, the pull-up power line RTO is driven to the external power supply voltage VDD which is an overdriving level for an initial predetermined period through an overdriving operation, and then to the core power supply voltage VCORE that is a normal driving level. Referring to FIG. 2 again, the positive bit line BL and the sub bit line / BL are driven at an overdriving level in an overdriving period according to data, and at a normal driving level in a normal driving period. This overdriving operation is to ensure faster operation of the semiconductor memory device as described above. In other words, when the positive bit line BL and the sub bit line / BL are initially amplified to an overdriving level, the corresponding bit line is amplified faster, which ensures faster operation of the semiconductor memory device. Can be.

Another reason for using such an overdriving method is that in the case of a semiconductor memory device using a relatively low external power supply voltage VDD, excessive current generated during the amplification operation of the bit line detection amplifier 270 is converted into a core power supply voltage VCORE. This is because it is difficult to handle alone. That is, the external power supply voltage VDD may supply sufficient current to drive the bit line detection amplifier 270 in some initial periods, and then the core power supply voltage VCORE may supply a current to ensure more stable operation. have.

However, this overdriving operation is similarly performed in a semiconductor memory device using a relatively high external power supply voltage VDD. That is, if a suitable amount of current is supplied to the pull-up power line RTO in the semiconductor memory device receiving the low external power supply voltage VDD, a pull-up power line (V) in the semiconductor memory device receiving the higher external power supply voltage VDD is applied. RTO) is supplied with an excessive amount of current. This excessively flowing current not only means unnecessary power consumption, but also causes a defect of the semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object thereof is to provide a semiconductor memory device and a driving method thereof capable of controlling the amount of current used in an overdriving operation as the external power supply voltage increases.

In accordance with an aspect of the present invention, a semiconductor memory device includes: amplifying means for sensing and amplifying data transmitted to a data line by receiving power through a pull-up drive line and a pull-down drive line; High-potential voltage generating means for generating a high-potential voltage having a characteristic of decreasing a voltage level as the external power supply voltage is increased; Overdriving driving means for driving the pull-up driving line to an external power supply voltage in response to an overdriving control signal activated by the high potential voltage; And pull-down driving means for driving the pull-down driving line to a ground power supply voltage in response to a pull-down control signal.

According to another aspect of the present invention, there is provided a method of driving a semiconductor memory device, the method comprising: generating a high potential voltage having a characteristic in which a voltage level decreases as an external power supply voltage increases; Driving a pull-up driving line to an overdriving level for an initial predetermined period in response to an overdriving control signal having a voltage level of the high potential voltage; Driving the pull-up driving line to a normal driving level lower than the overdriving level after the initial predetermined period; And amplifying data with power applied to the pull-up driving line.

The present invention is applied to a pull-up power line while maintaining a desired operating speed even in a semiconductor memory device using a relatively high external power supply voltage (VDD) by controlling the amount of current used in an overdriving operation as the external power supply voltage increases. The overdriving level can be improved.

The present invention can secure the predetermined overdriving level irrespective of the external power supply voltage, thereby obtaining an effect of minimizing power consumption while maintaining a desired operating speed.

In addition, it is possible to secure a stable overdriving level to eliminate the defects of the conventional semiconductor memory device, it is possible to obtain an effect that can ensure a more stable operation of the semiconductor memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

5 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to the present invention.

Referring to FIG. 5, the semiconductor memory device may include a drive controller 510, a power line driver 530, an internal power voltage generator 550, a bit line sense amplifier 570, and a word line driver 590. ) May be provided.

The driving controller 510 may include a pull-up control signal SAP1, a pull-down control signal SAN, a bit line equalization control signal BLEQ in response to the first to fourth activation signals EN1, EN2, EN3, and EN4. And generates an overdriving control signal SAP2. Here, the first to fourth activation signals EN1, EN2, EN3, and EN4 are signals that are activated at a predetermined time during the active operation of the semiconductor memory device. As will be described later, the overdriving control signal SAP2 according to the present invention has a voltage level that gradually decreases as the voltage level of the external power supply voltage VDD increases.

The power line driver 530 is controlled by the pull-up control signal SAP1, the pull-down control signal SAN, the bit line equalization control signal BLEQ, and the overdriving control signal SAP2 to perform a predetermined operation. The power line driver 530 pulls up and pulls down the pull-up power line RTO and the pull-down power line SB in response to the pull-up control signal SAP1 and the pull-down control signal SAN. performs a pull down operation, and performs an equalization operation of the pull-up power supply line RTO and the pull-down power supply line SB in response to the bit line equalization control signal BLEQ. The overdriving operation may be performed in response to the ice control signal SAP2.

The internal power supply voltage generation unit 550 includes a precharge power supply voltage generation unit 552 for generating a precharge power supply voltage VBLP, which is an internal power supply voltage, and a core power supply voltage generation unit for generating a core power supply voltage VCORE. 554, a first pumping power supply voltage generator 556 for generating the first pumping power supply voltage VPP1, and a second pumping power supply voltage generator for generating the second pumping power supply voltage VPP2. 558).

The internal power supply voltage generator 550 of the semiconductor memory device according to the present invention further includes a first pumping power supply voltage generator 556 compared to FIG. 2, and for convenience of description, the first pumping power supply voltage generator 550. The description of the components other than 556 will be omitted. For reference, the second pumping power voltage generator 558 of FIG. 5 corresponds to the pumping power voltage generator 256 of FIG. 2.

FIG. 6 is a circuit diagram illustrating the first pumping power voltage generator 556 of FIG. 5.

Referring to FIG. 6, the first pumping power supply voltage generation unit 556 generates the first pumping power supply voltage VPP1 through a pumping operation based on a target voltage level corresponding to the external power supply voltage VDD. The voltage detector 610, the oscillation signal generator 630, and the pumping unit 650 may be provided.

The voltage detector 610 may detect the first pumping power supply voltage VPP1 according to the target voltage level corresponding to the external power supply voltage VDD and output the first pumping power supply voltage VPP1 as the oscillation activation signal EN_OSC. Here, the oscillation activation signal EN_OSC activates the oscillation operation of the oscillation signal generator 630 when the first pumping power supply voltage VPP1 is lower than the target voltage level, and the first pumping power supply voltage VPP1 is the target voltage. When the level is higher than the level, the oscillation operation of the oscillation signal generator 630 may be deactivated. Here, the target voltage level according to the present invention has a characteristic of decreasing as the external power supply voltage VDD increases. This will be described in more detail with reference to FIGS. 7 and 8.

The oscillation signal generator 630 may generate the oscillation signal OSC through an oscillation operation in response to the oscillation activation signal EN_OSC. As described above, the oscillation signal generator 630 may be activated according to the oscillation activation signal EN_OSC to perform an oscillation operation or to be inactivated.

The pumping unit 650 may generate the first pumping power supply voltage VPP1 in which the external power supply voltage VDD is pumped in response to the oscillation signal OSC.

As a result, the first pumping power supply voltage generation unit 556 increases the first pumping power supply voltage VPP1 by performing a pumping operation when the first pumping power supply voltage VPP1 is lower than the target voltage level, and thus, first pumping power supply voltage. When VPP1 is lower than the target voltage level, the pumping operation is not performed.

7 is a circuit diagram illustrating the voltage detector 610 of FIG. 6.

Referring to FIG. 7, the voltage detector 610 includes a voltage divider 710, first and second input units 730, an activation unit 750, first and second power supply units 770, and The output unit 790 may be provided.

The voltage divider 710 is for distributing the first pumping power voltage VPP1, and includes first and second resistors R1 connected in series between the first pumping power voltage VPP1 and the ground power supply voltage terminal VSS. , R2). The common node between the first and second resistors R1 and R2 outputs a distribution voltage DIV having a voltage level obtained by dividing the first pumping power supply voltage VPP1.

The first and second input units 730 are used to differentially receive the divided voltage DIV and the reference voltage VREF corresponding to the first pumping power voltage VPP1. A source-drain path may be connected between the gates 750 and a first NMOS transistor NM1 configured to receive the division voltage DIV as a gate. The second input unit may include an output terminal and an activation unit for outputting a detection signal DET. A source-drain path may be formed between the gates 750 and the second NMOS transistor NM2 may receive a reference voltage VREF as a gate.

The activation unit 750 includes a third NMOS transistor NM3 having a source-drain path formed between the common node of the first and second input units 730 and the ground power supply voltage VSS, and receiving the activation signal EN as a gate. ) May be provided. Here, the activation signal EN may be a signal corresponding to the power-up operation of the semiconductor memory device, and the first and second input units 730 may divide the dividing voltage DIV and the reference voltage VREF in response to the activation signal EN. ) Can be input.

The first and second power supply units 770 correspond to the first NMOS transistors NM1 and the second NMOS transistors NM2 of the first and second input units 730, respectively. And the second input unit 730. Here, the first power supply unit may include a first PMOS transistor PM1 having a source-drain path formed between an external power supply voltage VDD terminal and an A node, and an A node connected to a gate to be connected in a diode type. The second power supply unit may include a second PMOS transistor PM2 having a source-drain path formed between an external power supply voltage VDD terminal and an output terminal where the detection signal DET is output, and having an A node connected to a gate thereof.

The output unit 790 outputs the oscillation activation signal EN_OSC in response to the detection signal DET output from the output terminal between the second PMOS transistor PM2 and the second NMOS transistor NM2. The inverter INV may be provided to receive and buffer the DET and output the buffered signal as the oscillation activation signal EN_OSC.

FIG. 8 is a graph for describing an operation of the voltage detector 610 of FIG. 7. Here, it is assumed that the first pumping power supply voltage VPP1 keeps rising because it is to find the activation time of the oscillation activation signal EN_OSC.

7 and 8, three operations of the voltage detector 710 may be described according to the voltage level of the external power supply voltage VDD. The first is when the external power supply voltage VDD (not shown) has a predetermined voltage level corresponding to the target voltage level by the reference voltage VREF, and the second is when the external power supply voltage VDD is higher than the first case. In the third case, the external power supply voltage VDD has a lower voltage level than the first case.

In the first case, since the external power supply voltage VDD (not shown) has a voltage level corresponding to the target voltage level, the oscillation activation signal EN_OSC transitions from logic 'high' to logic 'low' at the time T1 (shown). Can not be used).

In the second case, since the external power supply voltage VDD has a higher voltage level than the first case, the voltage level of the node A (see FIG. 7) has a relatively high voltage level corresponding to the external power supply voltage VDD. Therefore, the effective channel length of the first NMOS transistor NM1 is shortened by effective channel length modulation. This means that the first NMOS transistor NM1 performs a turn on operation even if the distribution voltage DIV is slightly lower than the first case. That is, even if the distribution voltage DIV is not higher than the reference voltage VREF, the first NMOS transistor NM1 may be turned on to cause the oscillation activation signal EN_OSC to transition. In other words, the oscillation activation signal EN_OSC may transition from logic 'high' to logic 'low' even when the first pumping power supply voltage VPP1 reaches a voltage level of T2 lower than T1.

In the third case, since the external power supply voltage VDD has a lower voltage level than the first case, as in the second case, the first NMOS transistor NM1 has a long effective channel length due to the effective channel length change. This means that the first NMOS transistor NM1 is turned off even if the distribution voltage DIV is somewhat higher than the reference voltage VREF. In other words, the oscillation activation signal EN_OSC may transition from logic 'high' to logic 'low' only when the first pumping power supply voltage VPP1 becomes a voltage level of T3 higher than T1.

As a result, the target voltage level of the voltage detector 610 is changed to T1, T2, and T3 according to the external power supply voltage VDD, and thus the transition time of the oscillation activation signal EN_OSC is also changed to T1, T2, and T3. In other words, the target voltage level is lowered as the voltage level of the external power supply voltage VDD is increased, and the transition time of the oscillation activation signal EN_OSC is also lowered as the voltage level of the external power supply voltage VDD is increased. 1 The voltage level of the pumping power supply voltage VPP1 is detected.

Subsequently, the oscillation activation signal EN_OSC is a signal that determines whether the oscillation signal generator 630 (see FIG. 6) performs an oscillation operation as described above. Therefore, the pumping unit 650 according to the present invention may deactivate the oscillation operation of the oscillation signal generator 630 in advance than the first case by operating as the second case described above when the external power voltage VDD is high. If the external power supply voltage VDD is low, the oscillation operation of the first oscillation call generator 414 may be activated longer than the first case by operating as in the third case described above. Therefore, the first pumping power generator 556 (refer to FIG. 5) according to the present invention may generate the first pumping power supply voltage VPP1 having the negative characteristic of decreasing the voltage level as the external power supply voltage VDD is increased. Can be.

Referring to FIG. 5 again, the precharge power supply voltage VBLP generated by the internal power supply voltage generation unit 550, the core power supply voltage VCORE, the first pumping power supply voltage VPP1, and the second pumping power supply voltage ( The VPP2 may be generated and applied to the driving controller 510, the power line driver 530, and the word line driver 590.

Before describing the driving controller 510, the bit line detection amplifier 570 and the word line driver 590 will be briefly described. The bit line detection amplifier 570 senses data transferred to the positive / negative bit lines BL and / BL using power applied to the pull-up power line RTO and the pull-down power line SB according to an operation. The word line driver 590 may drive the word line WL by receiving the pumping power voltage VPP.

FIG. 9 is a block diagram illustrating the driving control unit 510 of FIG. 5.

Referring to FIG. 9, the driving controller 510 may include a first control signal generator 910 for generating a pull-up control signal SAP1 in response to the first activation signal EN1, and a second activation signal EN2. In response to the second control signal generator 930 for generating the overdriving control signal SAP2 and generating a third control signal for generating the pull-down control signal SAN in response to the third activation signal EN3. And a fourth control signal generator 970 for generating a bit line equalization control signal BLEQ in response to the fourth activation signal EN4.

Here, since the first control signal generator 910 receives the second pumping power voltage VPP2 and the ground power voltage VSS, the pull-up control signal SAP1 may have a voltage level corresponding thereto. Since the second control signal generator 930 receives the first pumping power supply voltage VPP1 and the ground power supply voltage VSS, the overdriving control signal SAP2 may have a voltage level corresponding thereto. That is, the overdriving control signal SAP2 according to the present invention may have a negative characteristic corresponding to the external power voltage VDD which is a characteristic of the first pumping power voltage VPP1.

Subsequently, since the third control signal generators 950 and 970 receive the external power voltage VDD and the ground power voltage VSS, the pull-down control signal SAN and the bit line equalization control signal BLEQ are external power supplies. It may have a voltage level corresponding to the voltage VDD and the ground power supply voltage VSS.

Referring to FIG. 5 again, the power line driver 530 may include the pull-up control signal SAP1, the pull-down control signal SAN, the bit line equalization control signal BLEQ, and the overdriving control signal 530. Under the control of SAP2), a predetermined operation can be performed. Since the power line driver 530 has a configuration similar to that of FIG. 4, a separate drawing will be omitted and will be described with reference to FIG. 4. The biggest difference in the present invention with respect to the existing operation is in the overdriving operation.

Hereinafter, an overdriving operation according to the present invention will be described with reference to FIG. 4. For reference, since the normal driving operation and the precharging operation are performed in the same manner as in the related art, description thereof will be omitted.

In the overdriving operation, the pull-up power line RTO is driven by the external power supply voltage VDD and the pull-down power supply line SB is driven by the ground power supply voltage VSS in response to the overdriving control signal SAP2. At this time, since the bit line equalization control signal BLEQ is logic 'low', the equalization unit 470 is deactivated.

In this case, the overdriving driver 430 drives the pull-up power supply line RTO to the external power supply voltage VDD in response to the overdriving control signal SAP2, and the external power supply voltage VDD stage and the pull-up power supply line RTO. An NMOS transistor may be formed between a source and a drain path and receive an overdriving control signal SAP2 as a gate. Herein, when the voltage level of the overdriving control signal SAP2 is increased, the NMOS transistor has a smaller loading value. When the voltage level of the overdriving control signal SAP2 is lowered, the NMOS transistor has a higher loading value. That is, the smaller the loading value of the NMOS transistor in the state where the same external power supply voltage VDD is applied, it means that much current can flow to the pull-up power supply line RTO, and the loading value of the NMOS transistor is increased. This means that less current can flow into the pull-up power line (RTO).

In other words, the overdriving driver 430 may adjust the loading value in response to the overdriving control signal SAP2, and accordingly, the current applied to the pull-up power line RTO from the external power supply voltage VDD may be controlled. . In the conventional configuration, since the signal controlling the overdriving driver 430 operates independently of the external power supply voltage VDD, an excessive amount of current is supplied to the pull-up power line RTO during the overdriving operation. .

However, in the semiconductor memory device according to the present invention, since the overdriving driver 430 operates in response to the overdriving control signal SAP2 having negative characteristics with respect to the external power supply voltage VDD, the semiconductor memory device is relatively external to the semiconductor memory device. When the power supply voltage VDD is applied, the loading value of the overdriving driver 430 may be increased to transmit a desired amount of current to the pull-up power supply line RTO, and when a relatively low external power supply voltage VDD is applied, overdriving By lowering the loading value of the driver 430, a desired current amount can be transferred to the pull-up power line RTO.

As a result, the semiconductor memory device according to the present invention generates the first pumping power supply voltage VPP1 having a characteristic in which the voltage level decreases as the external power supply voltage VDD increases, and the voltage level of the first pumping power supply voltage VPP1. By generating the overdriving control signal SAP2 having a, the pull-up power line RTO can be driven to an overdriving level during an initial predetermined period by using the overdriving control signal SAP2. Subsequently, after overdriving, the pull-up power line RTO may be driven to the core power voltage VCORE at the normal driving level in response to the pull-up control signal SAP1, and the positive and negative bit lines BL and / BL may be driven. The data may be amplified by the power applied to the pull-up power line RTO.

Here, the overdriving control signal SAP2 is a pulse signal that is activated during a predetermined period, and the pull-up control signal SAP1 includes after the activation period of the overdriving control signal SAP2, which may vary according to design.

10 is a simulation for explaining the overdriving control signal SAP2 and the pull-up power line RTO of the present invention.

Referring to FIG. 10, although the conventional overdriving control signal SAP2 maintains the same voltage level regardless of the external power supply voltage VDD, the overdriving control signal SAP2 according to the present invention is an external power supply voltage VDD. It can be seen that the characteristics (sub-characteristics) gradually decrease as the height increases.

In addition, although the conventional pull-up power line RTO is gradually increased as the external power supply voltage VDD is increased, the pull-up power supply line RTO according to the present invention has a predetermined target voltage level even when the external power supply voltage VDD is increased. Correspondingly, it can be seen to maintain a nearly constant voltage level.

In addition, although the current flowing to the pull-up power line RTO in response to the overdriving control signal SAP2 has a characteristic of increasing as the external power voltage VDD increases, in the present invention, the pull-up power line RTO is used. It can be seen that the flowing current is lowered as the external power supply voltage VDD is increased.

As described above, in the semiconductor memory device according to the present invention, the pull-up power line RTO may maintain the target voltage level regardless of the voltage level of the external power supply voltage VDD. Therefore, power consumption can be minimized while maintaining a desired operating speed, and a stable overdriving level can be ensured, thereby ensuring more stable operation of the semiconductor memory device.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.

1 is a diagram for explaining general read and write operations of a semiconductor memory device;

FIG. 2 is a view for explaining a configuration related to driving the pull-up power line RTO and the pull-down power line SB of FIG.

3 is a block diagram illustrating the driving control unit 210 of FIG. 2.

4 is a circuit diagram illustrating the power line driver 230 of FIG. 2.

5 is a block diagram for explaining a part of a configuration of a semiconductor memory device according to the present invention;

FIG. 6 is a circuit diagram for describing the first pumping power supply voltage generation unit 556 of FIG. 5.

FIG. 7 is a circuit diagram for describing the voltage detector 610 of FIG. 6.

FIG. 8 is a graph for describing an operation of the voltage detector 610 of FIG. 7.

FIG. 9 is a block diagram illustrating the driving control unit 510 of FIG. 5.

10 is a simulation for explaining the overdriving control signal SAP2 and the pull-up power line RTO of the present invention.

* Explanation of symbols for the main parts of the drawings

510: drive control unit 530: power line drive unit

550: internal power voltage generator 570: bit line detection amplifier

590: word line driver

Claims (18)

Sensing amplification means for sensing and amplifying data transmitted to a data line by receiving power through a pull-up drive line and a pull-down drive line; High-potential voltage generating means for generating a high-potential voltage having a characteristic of decreasing a voltage level as the external power supply voltage is increased; Overdriving driving means for driving the pull-up driving line to an external power supply voltage in response to an overdriving control signal activated by the high potential voltage; And Pull-down driving means for driving the pull-down driving line to a ground power supply voltage in response to a pull-down control signal; A semiconductor memory device having a. The method of claim 1, And a pull-up driving means for driving the pull-up driving line to an internal power supply voltage in response to a pull-up control signal. The method according to claim 1 or 2, And driving control means for generating the overdriving control signal corresponding to the voltage level of the high potential voltage. The method of claim 1, And said overdriving driving means has a loading value corresponding to the voltage level of said high potential voltage. The method of claim 2, And the activation period of the pull-up control signal includes an activation period of the overdriving control signal. The method of claim 1, The high potential voltage generating means detects the high potential voltage based on a target voltage level corresponding to the external power supply voltage, and accordingly pumps the external power supply voltage to generate the high potential voltage. Device. The method of claim 6, The high potential voltage generating means, A voltage detector configured to detect the high potential voltage based on a target voltage level corresponding to the external power supply voltage and output the oscillation activation signal; An oscillation signal generator for generating an oscillation signal in response to the oscillation activation signal; And And a pumping unit configured to generate the high potential voltage in which the external power supply voltage is pumped in response to the oscillation signal. The method of claim 6, And the target voltage level is lowered as the external power supply voltage is increased. The method of claim 7, wherein The voltage detector, First and second input units configured to differentially input the high potential voltage and the reference voltage; First and second power supply units corresponding to the first and second input units, respectively, for supplying the external power voltage to the first and second input units; And And an output unit connected between the second input unit and the second power supply unit to output the oscillation activation signal. The method of claim 7, wherein A voltage divider for distributing the high potential voltage and providing the high input voltage to the first input unit; And an activation unit for activating input operations of the first and second input units in response to an activation signal. 10. The method of claim 9, And the first power supply unit is connected in a diode type between the external power supply voltage and the first input unit. 10. The method of claim 9, The second power supply unit includes a MOS transistor for receiving the output signal of the first power supply unit as a gate. 10. The method of claim 9, And the first power supply unit is a first MOS transistor having a source-drain path formed between the external power supply voltage and the first input unit, and having the source and the gate connected in common. 10. The method of claim 9, And the second power supply unit is a second MOS transistor having a source-drain path formed between the external power supply voltage and the output unit and connected to a gate of the first MOS transistor and its gate. . Generating a high potential voltage having a characteristic of decreasing a voltage level as the external power supply voltage is increased; Driving a pull-up driving line to an overdriving level for an initial predetermined period in response to an overdriving control signal having a voltage level of the high potential voltage; Driving the pull-up driving line to a normal driving level lower than the overdriving level after the initial predetermined period; And Amplifying data with power applied to the pull-up driving line Method of driving a semiconductor memory device comprising a. The method of claim 15, Generating the high potential voltage, Detecting the high potential voltage based on a target voltage level corresponding to the external power supply voltage; Generating an oscillation signal in response to the detection result; And And generating the high potential voltage pumping the external power voltage in response to the oscillation signal. The method of claim 16, And the target voltage level is lowered as the external power supply voltage is increased. The method of claim 15, The overdriving control signal is a pulse signal that is activated during a predetermined period, Driving to the normal driving level, And activating in response to a signal including after an activation period of the overdriving control signal.

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