KR100335119B1 - Nonvolatile ferroelectric memory device - Google Patents

Abstract

The present invention relates to a memory device having a plurality of cell arrays formed in a vertical direction, wherein a configuration of a sensing amplifier formed between the cell array unit is divided into a pull-down sensing amplifier unit and a pull-up sensing amplifier unit, and then a pull-up is used. In order to provide a non-volatile ferroelectric memory device that can efficiently reduce the layout and ensure stability due to amplification by allowing the up sensing amplifier to share the upper cell array and the lower cell array, A nonvolatile ferroelectric memory device having a plurality of cell array units, the nonvolatile ferroelectric memory device comprising: a pull-down sensing amplifier unit formed to correspond to each cell array unit between cell array units in a vertical direction and pull-down amplifying data of the cell array unit; The output of the pull-down sensing amplifier portion corresponding to the upper cell array portion and the lower cell array; And a pull-up sensing amplifier unit which selectively shares the output of the pull-down sensing amplifier unit corresponding to this unit and selectively pulls-up amplifies the output of the pull-down sensing amplifier unit.

Description

Nonvolatile Ferroelectric Memory Device {NONVOLATILE FERROELECTRIC MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile ferroelectric memory device capable of efficiently reducing layout through sharing of sensing amplifiers.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FRAM), has a data processing speed of about dynamic random access memory (DRAM), and is stored in the next generation because of the characteristic that data is preserved even when the power is turned off. It is attracting attention as an element.

FRAM is a memory device having a structure almost similar to that of DRAM, and uses a ferroelectric as a material of a capacitor and uses high residual polarization characteristic of the ferroelectric.

Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

1 is a characteristic diagram showing a hysteresis loop of a general ferroelectric.

As shown in FIG. 1, it can be seen that the polarization induced by the electric field does not disappear due to the presence of residual polarization (or spontaneous polarization) even when the electric field is removed, and maintains a certain amount (d, a state).

A nonvolatile ferroelectric memory cell is applied as a memory device by matching the d and a states to 1,0.

Hereinafter, a nonvolatile ferroelectric memory device according to the related art will be described with reference to the accompanying drawings.

2 illustrates a unit cell of a nonvolatile ferroelectric memory according to the prior art.

As shown in FIG. 2, the bit line B / L formed in one direction, the word line W / L formed in a direction crossing the bit line, and the same direction as the word line at regular intervals from the word line. A plate line (P / L) formed of a plurality of transistors; a transistor (T1) having a gate connected to the word line and a source connected to the bit line; and a first terminal of two terminals connected to a drain of the transistor (T1). The second terminal includes a ferroelectric capacitor FC1 connected to the plate line P / L.

The data input / output operation of the conventional nonvolatile ferroelectric memory device configured as described above is as follows.

FIG. 3A is a timing diagram illustrating an operation of a write mode of a conventional nonvolatile ferroelectric memory device, and FIG. 3B is a timing diagram illustrating an operation of a read mode.

First, in the write mode, when the chip enable signal CSBpad applied from the outside is activated from high to low, and simultaneously applying the write enable signal WEBpad from high to low, the write mode Begins.

Subsequently, when address decoding starts in the write mode, a pulse applied to the corresponding word line transitions from 'low' to 'high' so that the cell is selected.

As described above, in the section in which the word line maintains the 'high' state, the 'high' signal and the 'low' signal of the predetermined section are sequentially applied to the corresponding plate line.

In order to write a logic value '1' or '0' to the selected cell, a 'high' or 'low' signal is applied to the corresponding bit line in synchronization with the write enable signal WEBpad.

In other words, if the 'high' signal is applied to the bit line and the signal applied to the plate line is 'low' in the period where the signal applied to the word line is 'high', the logic value '1' is written in the ferroelectric capacitor.

When the 'low' signal is applied to the bit line and the signal applied to the plate line is the 'high' signal, a logic value '0' is written in the ferroelectric capacitor.

The operation for reading data stored in the cell by the operation of the write mode is as follows.

First, when the chip enable signal CSBpad is externally activated from 'high' to 'low', all bit lines are equipotentially applied to the 'low' voltage by the equalizer signal before the corresponding word line is selected.

After deactivating each bit line, the address is decoded, and a 'low' signal is changed to a 'high' signal in the word line by the decoded address to select a corresponding cell.

The 'high' signal is applied to the plate line of the selected cell to destroy the data corresponding to the logic value '1' stored in the ferroelectric memory.

If a logic value '0' is stored in the ferroelectric memory, the corresponding data is not destroyed.

The destroyed data and the unbroken data are output different values based on the above-described hysteresis loop principle, so that the sense amplifier senses a logic value '1' or '0'.

That is, when data is destroyed, it is a case where d is changed from f to f as in the hysteresis loop of FIG. 1, and when data is not destroyed, it is when a case is changed from a to f.

Therefore, if the sense amplifier is enabled after a certain time has elapsed, the data is amplified when the data is destroyed and outputs a logic value '1', and when the data is not destroyed, the logic value '0' is output.

As described above, after the data is output from the sense amplifier, the original data must be restored, and the plate line is deactivated from 'high' to 'low' while the 'high' signal is applied to the corresponding word line.

4 is a configuration diagram of a nonvolatile ferroelectric memory device having a cell having a conventional 1T / 1C structure.

As shown in FIG. 4, the main cell array unit 41 and the main cell array unit 41 are formed of an array of unit cells and configured by allocating a lower portion to the reference cell array unit 42. A word line driver part 43 formed to apply driving signals to the main cell array part 41 and the reference cell array part 42, and a sensing amplifier part 44 formed under the main cell array part 41. It is composed of

Here, the word line driver unit 43 applies a driving signal to the main word line of the main cell array unit 41 and the reference word line of the reference cell array unit 42.

The sensing amplifier unit 44 is composed of a plurality of sensing amplifiers and amplifies the signals of the bit line and the bit bar line.

The operation of the conventional nonvolatile ferroelectric memory device will be described with reference to FIG. 5.

FIG. 5 is a partial detailed view of FIG. 4, and as shown in the drawing, the main cell array has a folded bitline structure like DRAM.

The reference cell array unit 42 also has a folded bit line structure and is configured by pairing a reference cell word line and a reference cell plate line.

In this case, the reference cell word line and the reference cell plate line are defined as RWL_1, RPL_1, RWL_2, and RPL_2, respectively.

When the main cell word line MWL_N-1 and the main cell plate line MPL_N-1 are activated, the reference cell word line RWL_1 and the reference cell plate line RPL_1 are activated.

Therefore, the data of the main cell is loaded on the bit line B / L, and the data of the reference cell is loaded on the bit bar line BB / L.

In addition, when the main cell word line MWL_N and the main cell plate line MPL_N are activated, the reference cell word line RWL_2 and the reference cell plate line RPL_2 are also activated.

Accordingly, data of the main cell is loaded on the bit bar line BB / L, and reference cell data is loaded on the bit line B / L.

FIG. 6 is a partial detailed view of FIG. 4 and illustrates only one of a plurality of sensing amplifiers constituting the sensing amplifier unit.

The sensing amplifier according to the prior art has a structure of a latch type sensing amplifier.

That is, it consists of two PMOS transistors and two NMOS transistors, and the transistors form a latch type inverter structure.

In the configuration, the first PMOS transistor MP1 and the second PMOS transistor MP2 are formed to face each other, and the output terminal of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2. The output terminal of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1.

In addition, SAP signals are commonly applied to the input terminals of the first and second PMOS transistors MP1 and MP2.

The SAP signal is an activation signal for activating the first and second PMOS transistors MP1 and MP2.

A first NMOS transistor MN1 is connected in series with an output terminal of the first PMOS transistor MP1, and a second NMOS transistor MN2 is connected in series with an output terminal of the second PMOS transistor MP2. .

In this case, an output terminal of the second NMOS transistor MN2 is connected to a gate of the first NMOS transistor MN1, and an output terminal of the first NMOS transistor MN1 is a gate of the second NMOS transistor MN2. Is connected to.

In addition, a SAN signal is commonly applied to the input terminals of the first and second NMOS transistors MN1 and MN2. The SAN signal is an activation signal for activating the first and second NMOS transistors MN1 and MN2.

Output terminals of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the bit line B_N in common, and the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to each other. The output stage is connected to the next bit line B_N + 1.

In such a sensing amplifier, its output is connected to the bit lines B_N and B_N + 1, respectively, to enable input and output to the main cell and the reference cell.

Accordingly, the signals of SAP, SAN, B_N, and B_N + 1 are all maintained at 1 / 2Vcc during the precharge period during normal sensing amplifier deactivation.

On the other hand, when activated, SAP is pulled up to a high level and the SAN is pulled down to the ground level.

FIG. 7 is configured to sense data of an upper cell array unit and a lower cell array unit using a conventional sensing amplifier.

In FIG. 7, reference numeral '41a' indicates an upper cell array unit and '41b' indicates a lower cell array unit.

In order to sense data of the upper cell array unit, the TSEL signal, which is a control signal, is set to high level, and the BSEL signal is set to low level.

Accordingly, a pad path between the lower cell array unit and the sensing amplifier is blocked, and a path between the upper cell array unit and the sensing amplifier is configured.

Accordingly, the sensing amplifier senses a signal on the bit line and the bit bar line of the upper cell array unit.

On the contrary, in order to sense data of the lower cell array unit, the control signal TSEL transitions to a low level and the BSEL signal transitions to a high level.

Accordingly, the pad path between the upper cell array unit and the sensing amplifier is blocked, and a path of the sensing amplifier of the lower cell array unit is configured.

Accordingly, the sensing amplifier senses a signal on the bit line and the bit bar line of the lower cell array unit.

However, the conventional nonvolatile ferroelectric memory device has the following problems.

Since the input terminal of the sensing amplifier is directly connected to the upper and lower bit lines through a switching element, the loading between the bit line and the bit bar line may be different.

Therefore, amplification occurs in a state in which loadings are different from each other, and thus amplification becomes unstable.

The present invention has been made to solve the above problems of the prior art, in the memory device having a plurality of cell array formed in the vertical direction, the configuration of the sensing amplifier formed between the cell array unit pull-down sensing amplifier unit The present invention provides a nonvolatile ferroelectric memory device that reduces the layout by dividing the P-PSI into a pull-up sensing amplifier unit and allowing the pull-up sensing amplifier unit to share the upper cell array unit and the lower cell array unit. There is this.

Another object of the present invention is to provide a nonvolatile ferroelectric memory device capable of compensating for different loadings between a bit line and a bit bar line to secure stability due to amplification.

1 is a characteristic diagram showing a hysteresis loop of a typical ferroelectric

2 is a unit cell configuration diagram of a nonvolatile ferroelectric memory according to the related art.

3A is a timing diagram illustrating an operation of a write mode of a conventional nonvolatile ferroelectric memory device.

3B is a timing diagram illustrating an operation of a read mode.

4 is a configuration diagram of a nonvolatile ferroelectric memory device having a cell having a conventional 1T / 1C structure.

5 is a partial detail view of FIG. 4.

6 is a detailed configuration diagram of the sensing amplifier of FIG.

7 is a diagram illustrating a configuration between a cell array unit and a sensing amplifier in a conventional nonvolatile ferroelectric memory device.

8 is a configuration diagram of a unit cell according to a nonvolatile ferroelectric memory device of the present invention.

9 is a circuit diagram illustrating a nonvolatile ferroelectric memory device of the present invention.

10 is an operation timing diagram of a nonvolatile ferroelectric memory device of the present invention.

11 is a block diagram illustrating a nonvolatile ferroelectric memory device of the present invention.

12 is a partially enlarged view of FIG. 11;

13 is a configuration diagram of a sensing amplifier in accordance with the nonvolatile ferroelectric memory device of the present invention.

14 is a view showing a waveform change in the output node of the sensing amplifier shown in FIG.

15 is a configuration diagram of a pull-down sensing amplifier according to the nonvolatile ferroelectric memory device of the present invention.

16 is a configuration diagram of a pull-up sensing amplifier according to the nonvolatile ferroelectric memory device of the present invention.

Explanation of symbols for main parts of the drawings

11_1,11_2,11_3, ..., 11_N: cell array unit

12_1,12_2, ..., 12_N: First pull-down sensing amplifier

13_1,13_2, ..., 13_N: Pull-up sensing amplifier

14_1,14_2, ..., 14_N: second pull-down sensing amplifier

A nonvolatile ferroelectric memory device of the present invention for achieving the above object is a nonvolatile ferroelectric memory device having a plurality of cell array portion formed in the form of a matrix, it is formed to correspond to each cell array portion between the cell array portion in the vertical direction And a pull-down sensing amplifier unit for pull-down amplifying data of the corresponding cell array unit, the upper cell array unit and the lower cell array unit share, and selectively select data of the upper cell array unit or data of the lower cell array unit. It characterized in that it comprises a pull-up sensing amplifier for amplifying the pull-up.

Hereinafter, a nonvolatile ferroelectric memory device according to the present invention will be described.

8 illustrates a unit cell of a nonvolatile ferroelectric memory device of the present invention.

As shown in FIG. 8, the first split word line SWL1, the second split word line SWL2, the first and second split word lines SWL1, which are formed in a row direction and have a predetermined distance from each other, are formed in a row direction. The first bit line B / L1 and the second bit line B / L2 formed in the direction crossing the SWL2, the gate is connected to the first split word line SWL1, and the drain thereof is the first bit line B / L1. The first transistor T1 connected to L1, the first ferroelectric capacitor FC1 connected between the source of the first transistor T1 and the second split word line SWL2, and the gate of the second split word line A second ferroelectric capacitor connected between the second transistor T2 and the drain connected to the second bit line B2, and between the source of the second transistor T2 and the first split word line SWL1. (FC2).

A plurality of such unit cells are formed to form a cell array unit. In the data storage unit, a pair of split word lines, one bit line, one transistor 1T, and one ferroelectric capacitor 1C become unit cells. Structurally, a pair of split word lines, two bit lines, two transistors 2T, and two ferroelectric capacitors 2C become unit cells.

The operation principle of the nonvolatile ferroelectric memory device will be described in more detail as follows.

9 is a simplified circuit configuration of the nonvolatile ferroelectric memory device of the present invention.

As illustrated in FIG. 9, a plurality of split word line pairs having a pair of first and second split word lines SWL1 and SWL2 are formed in a row direction and cross the split word line pairs. A plurality of bit lines B / Ln and B / Ln + 1 are formed, and data lines DL or data bar lines are sensed by sensing data transmitted through both bit lines between each bit line and the bit line. Sensing amplifiers SA are transmitted to (/ DL).

In this case, a sensing amplifier enable unit (not shown) for outputting an activation signal SEN for activating the sensing amplifiers SA is further provided, and the selection switching unit CS selectively switches the bit lines and the data lines. Is further provided.

The operation of the nonvolatile ferroelectric memory device of the present invention will be described with reference to the timing diagram shown in FIG. 10.

The section T0 of FIG. 10 is a section before the first split word line SWL1 and the second split word line SWL2 are activated as 'H', and all bit lines are set to the threshold voltage level of the NMOS transistor. Precharge.

The T1 section is a section in which the first and second split word lines SWL1 and SWL2 are both 'H', and data of the ferroelectric capacitor of the main cell is transferred to the main bit line, thereby changing the level of the bit line.

At this time, the ferroelectric capacitor stored as logic 'High' is applied to the bit line and the split word line by the opposite polarity of the electric field so that a large amount of current flows while the polarity of the ferroelectric is destroyed, thereby inducing a high voltage on the bit line.

On the other hand, ferroelectric capacitors stored as logic 'Low' are applied with the same polarity to the bit line and the split word line, so that the polarity of the ferroelectric is not destroyed, so that less current flows and a little voltage is induced in the bit line.

When the cell data is sufficiently loaded on the bit line, the sensing amplifier enable signal SEN is shifted high to amplify the level of the bit line to activate the sensing amplifier.

On the other hand, the logic 'H' data of the destroyed cell cannot be restored while the first split word line SWL1 and the second split word line SWL2 are high, so they are restored in the next T2 and T3 sections. It can be restored.

Subsequently, the T2 section is a section in which the first split word line SWL1 transitions to a low level and the second split word line SWL2 remains in a high state, and the second transistor T2 is turned on. (On) state. At this time, if the corresponding bit line is in a high state, high data is transferred to one electrode of the second ferroelectric capacitor FC2 to between the low state of the first split word line SWL1 and the high level of the bit line. Logic 1 state is restored.

The T3 section is a section in which the first split word line SWL1 transitions high again and the second split word line SWL2 transitions low, and the first transistor T1 is turned on. On). At this time, if the corresponding bit line is in a high state, high data is transferred to one electrode of the first ferroelectric capacitor FC1 to restore the logic 1 state between the high levels of the second split word line SWL2.

11 is a block diagram illustrating an embodiment of a nonvolatile ferroelectric memory device of the present invention.

As shown in FIG. 11, a cell disposed between the plurality of cell array units 11_1, 11_2,..., 11_N formed in a matrix form and between the cell array units in the vertical direction among the cell array units. First pull-down sensing amplifier units 12_1, 12_2,..., 12_N that pull-down amplify the bit line signals of the array unit, and second second pull-down amplify bitline signals of the cell array unit located below; Outputs of the pull-down sensing amplifier units 14_1, 14_2,..., 14_N and the first pull-down sensing amplifier units 12_1, 12_2,... 12_N or the second pull-down sensing amplifier unit. And a pull-up sensing amplifier unit 13_1, 13_2, ..., 13_N for pull-up amplifying the output of (14_1, 14_2, ..., 14_N).

Here, the sensing amplifier units 15_1 and 15_2 for sensing data of the outermost cell array unit in the vertical direction among the cell array units may be any one of the first pull-down sensing amplifier unit and the second pull-down sensing amplifier unit. One and the pull-up sensing amplifier unit has a structure combined.

That is, one of the two pull-down sensing amplifier units and the pull-up sensing amplifier unit are connected to each other to form the sensing amplifier units 15_1 and 15_2 for sensing data located at the outermost.

In this case, the first pull-down sensing amplifier units 12_1, 12_2,..., 12_N and the second pull-down sensing amplifier units 14_1, 14_2,... 14_N have the same configuration.

However, an input terminal of the first pull-down sensing amplifier unit 12_1, 12_2, 12_N is connected to a bit line of a cell array unit located at an upper portion thereof, and second pull-down sensing amplifier unit 14_1, 14_2,..., 14_N ) Is connected to the bit line of the cell array unit located below.

Each output terminal of the first and second pull-down sensing amplifier units is commonly connected to an input terminal of the pull-up sensing amplifier units 13_1, 13_2,..., 13_N.

Meanwhile, the first pull-down sensing amplifier units 12_1, 12_2,..., 12_N and the pull-up sensing amplifier units 13_1, 13_2,..., 13_N are simultaneously activated, and the second pull-down The down sensing amplifier units 14_1, 14_2,..., 14_N and the pull-up sensing amplifier units 13_1, 13_2,..., 13_N are also activated at the same time.

However, when the first pull-down sensing amplifier unit and the pull-up sensing amplifier unit are in an active state, the second pull-down sensing amplifier unit remains inactive, and conversely, the second pull-down sensing amplifier unit and the pull-up sensing unit. If the amplifier unit is in an activated state, the first pull-down sensing amplifier unit remains in an inactive state.

FIG. 12 is a block diagram illustrating a first and a second pull-down sensing amplifier unit and a pull-up sensing amplifier unit in accordance with the nonvolatile ferroelectric memory device of the present invention.

As shown in FIG. 12, the first pull-down sensing amplifier unit 12_1 and the pull-up sensing amplifier unit 13_1 are combined to form one intact sensing amplifier unit 12a, and the second pull- The down sensing amplifier unit 14_1 and the pull-up sensing amplifier unit 13_1 are combined to form another intact sensing amplifier unit 14a.

Here, it can be seen that the pull-up sensing amplifier unit 13_1 is commonly used.

In the nonvolatile ferroelectric memory device of the present invention configured as described above, the first pull-down sensing amplifier unit 12_1 and the pull-up sensing amplifier unit are configured to sense and amplify data of the cell array unit 11_1 disposed above. 13_1 is activated, and the second pull-down sensing amplifier unit 14_1 is deactivated.

When the bit line level of the cell array unit 11_1 positioned above the first pull-down sensing amplifier unit 12_1 and the pull-up sensing amplifier unit 13_1 is in an active state, the first pull-down is performed. If the down sensing amplifier unit 12_1 performs pull-down amplification, and the reference level is higher than or equal to the reference level, the pull-up sensing amplifier unit 13_1 amplifies the output of the first pull-down sensing amplifier unit 12_1. do.

On the contrary, in order to sense and amplify data of the lower cell array unit 11_2, the second pull-down sensing amplifier unit 14_1 and the pull-up sensing amplifier unit 13_1 are activated and the first pull-down is performed. The sensing amplifier 12_1 is deactivated.

When the bit line level of the cell array unit 11_2 positioned below the second pull-down sensing amplifier unit 14_1 and the pull-up sensing amplifier unit 13_1 is in an active state, the second pull-down The pull-up sensing amplifier unit 14_1 pull-ups the output of the second pull-down sensing amplifier unit 14_1 when the -down sensing amplifier unit 14_1 performs pull-down amplification. .

Hereinafter, the sensing amplifier unit located at the outermost portion in which one pull-down sensing amplifier unit and the pull-up sensing amplifier unit are combined will be described in detail.

FIG. 13 illustrates a configuration of a sensing amplifier unit according to the nonvolatile ferroelectric memory device of the present invention, and illustrates a sensing amplifier for sensing data of a cell array unit located at the outermost portion.

As illustrated in FIG. 13, a first transistor T1 for switching a signal loaded on a bit line, a second transistor T2 for switching a reference signal output from a reference signal generation circuit unit (not shown), and a second transistor T2. The third transistor T3 for switching the signal of the bit line applied through the first transistor T1, the fourth transistor T4 for switching the reference signal applied through the second transistor T2, and the gate of the third transistor T3. A fifth transistor T5 connected to an input terminal of the fourth transistor T4 and a drain connected to an output terminal of the third transistor T3, a gate connected to an input terminal of the third transistor T3, and a drain of the fourth transistor T4 A sixth transistor T6 connected to the output terminal of the fourth transistor T4 and a fifth transistor T6 formed between the output terminal of the fifth transistor T5 and the data line D / L and controlled by the column select signal CS. 7 The eighth transistor T8 formed between the transistor T7, the output terminal of the sixth transistor T6 and the data bar line DB / L and controlled by the column select signal CS, and the source is connected to the ground terminal ( A ninth transistor T9 connected to a drain of the fifth and sixth transistors T5 and T6, a source connected to a power supply voltage terminal Vcc, and a drain of the second transistor connected to a drain of the fifth and sixth transistors T5 and T6. A tenth transistor T10 connected to the output terminal of T2, a source is connected to the power supply voltage terminal, and a drain is commonly connected to an output terminal of the third transistor T3 and a gate of the tenth transistor T3; And the twelfth transistor T12 for equalizing the drain of the tenth transistor T10 and the drain of the eleventh transistor T11.

Here, the gate of the eleventh transistor T11 is connected to the drain of the tenth transistor T10.

The first transistor T1 is controlled by the bit line control signal BLC and the second transistor T2 is controlled by the reference bit line control signal RLC.

The third and fourth transistors T3 and T4 are controlled by the latch enable control signal LEC.

The ninth transistor T9 is controlled by the sensing amplifier activation signal SEN.

The twelfth transistor T12 is controlled by the sensing amplifier equalizing signal SEQ.

FIG. 14 illustrates changes in output waveforms at nodes SN3 and SN4 of the sensing amplifier unit shown in FIG. 13.

Here, section A is a precharge section, and section B is an amplification section.

Section C is a pseudo latch section, section D is an actual latch section, and section E represents an output section.

15 is a detailed configuration diagram of a pull-down sensing amplifier according to the nonvolatile ferroelectric memory device of the present invention.

It can be seen that the pull-down sensing amplifier illustrated in FIG. 15 is part of the sensing amplifier illustrated in FIG. 13.

According to the configuration, the signal of the main bit line transferred through the first transistor T1 for switching the signal of the main bit line, the second transistor T2 for switching the reference signal, and the first transistor T1 A third transistor T3 for switching, a fourth transistor T4 for switching the reference signal transmitted through the second transistor T2, a gate is connected to an input terminal of the fourth transistor T4, and a drain thereof is A fifth transistor T5 connected to the output terminal of the third transistor T3, a sixth transistor connected to an input terminal of the third transistor T3, and a drain thereof connected to an output terminal of the fourth transistor T4. And a ninth transistor T9 having a source connected to the ground terminal GND and a drain connected to the drains of the fifth and sixth transistors T5 and T6 in common.

When the sensing amplifier activation signal applied to the gate of the ninth transistor T9 transitions to a high level, the pull-down sensing amplifier unit includes a fifth transistor T5 to which a reference signal is applied to the gate, and a bit line signal to the gate. Amplification occurs by the sixth transistor T6 to which is applied.

The output is sent to the nodes SN3 and SN4, and the output is sent back to the nodes SN1 and SN2 by the latch enable control signal LEC.

Therefore, the bit line control signal BLC is transferred to the bit line of the cell through the first transistor T1 and the second transistor T2.

FIG. 16 illustrates in detail the pull-up sensing amplifier unit according to the nonvolatile ferroelectric memory device of the present invention.

It can be seen that the pull-up sensing amplifier unit shown in FIG. 16 is part of the sensing amplifier unit shown in FIG. 13.

That is, the pull-up sensing amplifier unit is composed of parts of the sensing amplifier unit illustrated in FIG. 13 except for the components of the pull-down sensing amplifier illustrated in FIG. 15.

The pull-up sensing amplifier unit amplifies a bit line signal input through the nodes SN3 and SN4.

Here, the node SN3 is an output terminal of the third transistor T3 and SN4 is an output terminal of the fourth transistor T4.

Since the third and fourth transistors T3 and T4 constitute a pull-down sensing amplifier unit, the pull-up sensing amplifier unit may pull-up amplify a signal of a bit line input through the pull-down sensing amplifier unit. have.

Referring to the configuration of the pull-up sensing amplifier illustrated in FIG. 16, drains are respectively connected to the nodes SN3 and SN4 to which the bit line signals are transmitted from the pull-down sensing amplifier, and a source is connected to the power supply voltage terminal Vcc. Two PMOS transistors T10 and T11, another PMOS transistor T12 for equalizing drains of the PMOS transistors T10 and T11, and the pull-up amplified signal to a data line and data. It consists of two NMOS transistors T7 and T8 that selectively transfer to the bar line.

That is, when the data on the bit line is equal to or higher than the level of the reference signal, the pull-up sensing amplifier unit pulls the bit line signals transferred through the third and fourth transistors T3 and T4 constituting the pull-down sensing amplifier unit. -Up will be amplified.

This process corresponds to a read. In the write mode, if the data loaded on the data line and the data bar line is equal to or higher than the level of a reference signal, the pull-up amplification unit is pulled up and amplified to the node SN3. The third and fourth transistors T3 and T4 and the first and second transistors T1 and T2 constituting the pull-down sensing amplifier are transferred to the bit line through and SN4.

In the pull-up sensing amplifier as described above, the twelfth transistor T12 not only functions to equalize the nodes SN3 and SN4 but also amplifies the signals induced in the nodes SN3 and SN4 by the pull-down sensing amplifier. Even if it does, it performs the function of preventing the latch mode.

This can cause amplification again for the changed input even if the input changes at any time.

Accordingly, the twelfth transistor T12 is maintained in an on state during the precharge period and the amplification period of the initial sensing amplifier.

As described above, the nonvolatile ferroelectric memory device of the present invention has the following effects.

The sensing amplifier is divided into a pull-down sensing amplifier unit and a pull-up sensing amplifier unit, and the pull-up sensing amplifier unit can be shared by vertically arranged upper and lower cell array units to minimize the area occupied by the sensing amplifier. In this way, the layout can be reduced efficiently, and stability due to amplification can be ensured.

Claims (17)

A nonvolatile ferroelectric memory device having a plurality of cell array portions formed in a matrix form, A pull-down sensing amplifier unit formed to correspond to each cell array unit between the cell array units in the vertical direction and to pull-down amplify data of the cell array unit; Non-volatile ferroelectric memory, characterized in that the upper cell array unit and the lower cell array unit and a pull-up sensing amplifier unit for selectively pull-up amplification of the data of the upper cell array unit or the data of the lower cell array unit Device. The sensing amplifier unit of claim 1, wherein the sensing amplifier unit for sensing data of the outermost cell array unit in the vertical direction of the plurality of cell array units has a combination of one pull-down sensing amplifier unit and a pull-up sensing amplifier unit. Nonvolatile ferroelectric memory device, characterized in that. The pull-down sensing amplifier unit and the pull-up sensing amplifier unit corresponding to the upper cell array unit among pull-down sensing amplifier units formed to correspond to each cell array unit are simultaneously activated or lower cells. And a pull-down sensing amplifier unit corresponding to an array unit and the pull-up sensing amplifier unit are simultaneously activated. A first cell array unit and a second cell array unit formed in a vertical direction; First and second split word line driver units configured to output driving signals to the corresponding cell array units; A first pull-down sensing amplifier unit to selectively pull down data of the first cell array unit; A second pull-down sensing amplifier unit selectively pulling down data of the second cell array unit; And a pull-up sensing amplifier unit configured to share the first cell array unit and the second cell array unit and selectively pull-up data of each cell array unit. The nonvolatile ferroelectric memory device of claim 4, wherein any one of the first pull-down sensing amplifier unit and the second pull-down sensing amplifier unit is activated simultaneously with the pull-up sensing amplifier unit. The pull-up sensing amplifier unit of claim 4, wherein the bit-up sensing amplifier unit is pulled up when the bit line level of the first cell array unit is greater than or equal to a reference level while the first pull-down sensing amplifier unit and the pull-up sensing amplifier unit are activated. And amplifying the first pull-down sensing amplifier unit if the reference level is lower than the reference level. The pull-up sensing amplifier unit of claim 4, wherein the bit-up sensing amplifier unit is pulled up when the bit line level of the second cell array unit is greater than or equal to a reference level while the second pull-down sensing amplifier unit and the pull-up sensing amplifier unit are activated. And amplifying the second pull-down sensing amplifier unit if the reference level is lower than the reference level. The nonvolatile ferroelectric memory device of claim 6, wherein the pull-up sensing amplifier unit pull-ups a signal of the bit line transferred through the pull-down sensing amplifier unit. The nonvolatile ferroelectric memory device of claim 4, wherein the first and second cell array units are formed in plural in a matrix form. 10. The method of claim 9, wherein the sensing amplifier unit for sensing data of the cell array unit located at the outermost of the plurality of first and second cell array units of the first pull-down sensing amplifier or the second pull-down sensing amplifier Nonvolatile ferroelectric memory device, characterized in that having a combination of any one of the pull-up sensing amplifier unit. The nonvolatile ferroelectric memory device of claim 4, wherein the first pull-down sensing amplifier unit and the second pull-down sensing amplifier unit have the same structure. The sensing amplifier unit of claim 10, wherein the sensing amplifier unit is configured to sense data of the outermost cell array unit. A first transistor for switching a signal of a main bit line, A second transistor for switching the reference signal; A third transistor controlled by a latch enable control signal and switching an output signal of the first transistor; A fourth transistor controlled by the latch enable control signal and switching an output signal of the second transistor; A fifth transistor having a gate connected to the fourth transistor and an input terminal, and a drain thereof connected to an output terminal of the third transistor; A sixth transistor having a gate connected to an input terminal of the third transistor and a drain connected to an output terminal of the fourth transistor; A seventh transistor formed between the output terminal and the data line of the fifth transistor and controlled by a column select signal; An eighth transistor formed between an output terminal of the sixth transistor and a data bar line and controlled by a column select signal; A ninth transistor having a drain connected in common with the sources of the fifth and sixth transistors, the source of which is connected to a ground terminal and operated by a sensing amplifier activation signal; A tenth transistor having a source connected to a power supply voltage terminal and a drain connected to an output terminal of the third transistor; An eleventh transistor having a source connected to a power supply voltage terminal and a drain connected to the output terminal of the fourth transistor and the gate of the tenth transistor in common; And a twelfth transistor for equalizing the drain of the tenth transistor and the drain of the eleventh transistor. 13. The nonvolatile ferroelectric memory device of claim 12, wherein the tenth, eleventh, and twelfth transistors are formed of PMOS transistors and other NMOS transistors. 11. The apparatus of claim 10, wherein the pull-up sensing amplifier unit comprises: a seventh transistor formed between an output terminal of the fifth transistor and a data line of the sensing amplifier unit located at the outermost portion and controlled by a column select signal; An eighth transistor formed between an output terminal of the sixth transistor and a data bar line and controlled by a column select signal; A tenth transistor having a source connected to a power supply voltage terminal and a drain connected to an output terminal of the third transistor; An eleventh transistor having a source connected to a power supply voltage terminal and a drain connected to the output terminal of the fourth transistor and the gate of the tenth transistor in common; And a twelfth transistor for equalizing the drain of the tenth transistor and the drain of the eleventh transistor. The method of claim 10, wherein the first pull-down sensing amplifier unit A first transistor for switching a signal of a main bit line of the first cell array unit among the first and second cell array units; A second transistor for switching the reference signal; A third transistor controlled by a latch enable control signal and switching an output signal of the first transistor; A fourth transistor controlled by the latch enable control signal and switching an output signal of the second transistor; A fifth transistor having a gate connected to the fourth transistor and an input terminal, and a drain thereof connected to an output terminal of the third transistor; A sixth transistor having a gate connected to an input terminal of the fourth transistor and a drain connected to an output terminal of the fourth transistor; And a ninth transistor having a source connected to a ground terminal and a drain connected to the drains of the fifth and sixth transistors in common. 16. The fire of claim 15, wherein the drain of the fifth transistor is connected to the drain of the tenth transistor constituting the pull-up transistor, and the drain of the sixth transistor is connected to the drain of the eleventh transistor. Volatile ferroelectric memory device. 11. The method of claim 10, wherein the second pull-down sensing amplifier portion has the same structure as the first pull-down sensing amplifier portion, wherein the first transistor is the second cell array portion of the first, second cell array portion Nonvolatile ferroelectric memory device, characterized in that for switching the signal of the main bit line.