DE10035108A1 - Non-volatile ferroelectric memory has cell arrays in matrix with number of pulldown read amplifiers formed between cell arrays and pullup read amplifier - Google Patents

Abstract

The memory has a number of cell arrays in a matrix with a number of pulldown read amplifiers (121, 122,..;141, 142,..) formed between cell arrays arranged in the vertical direction so that they corresp. to them to perform pulldown amplification of data in a corresp. cell array and a pullup read amplifier (131, 132,..) commonly used by an upper and a lower cell array to perform selective pullup amplification of a data value in the upper or lower cell array. .

Description

The invention relates to a non-volatile ferroelectric memory, more specifically a non-volatile ferroelek trical memory, in which the layout through common groove tion of a sense amplifier can be effectively reduced. A non-volatile ferroelectric memory, namely a ferroelectric random access memory (FRAM) has in Generally about a data processing speed that as high as that of a dynamic random access memory (DRAM), and it maintains data even when the Voltage is switched off. Because of this, do not have volatile ferroelectric memory as memory of the next a lot of attention.  

FRAMs and DRAMs are memories with almost the same structure ren, and they contain a ferroelectric capacitor with the property of high residual polarization. this makes possible that data is not deleted even if a electric field is removed.

Fig. 1 shows the hysteresis loop of a conventional Ferroelek trikums. As shown in Fig. 1, data stored by the electric field induced polarization remains to some extent even when the electric field is removed (states d and a) due to the presence of residual polarization (or spontaneous polarity) sation) received without deletion.

This effect can be used as a memory cell Memory that states d and a are logical Values 1 and 0 are equated.

If, for the sake of brevity, the Re de is, including a non-volatile ferroelectric Understand memory.

A known memory will now be described with reference to the accompanying Figs. 2 and 6. Fig. 2 shows a unit cell of this memory.

As shown in Fig. 2, the known memory includes a unidirectional bit line B / L; a word line W / L intersecting the bit line; a plate line P / L extending in the direction of the word line and spaced therefrom; a transistor T1 whose gate is connected to the word line and whose source is connected to the bit line; and a ferroelectric capacitor FC1, the first terminal of which is connected to the drain of the transistor T1 and the second terminal of which is connected to the plate line P / L.

Below is a data input / output process at the sem known memory described.

Figure 3a is a timing diagram illustrating the operation in the write mode of this memory, and Figure 3b is a corresponding diagram for the read mode.

In write mode, an externally created chip release signal CSBpad activated from high to low. The write mode starts if at the same time Write enable signal WEBpad from high to low to stand is created.

Then, when an address decoding process in the Write mode starts, on to a corresponding word line applied pulse from low to high leads, whereby a cell is selected.

A Perio de, in which the word line is kept high, a high signal in a certain period and a low The signal is applied sequentially in a certain period.

To the logical value 1 or 0 in the selected cell too write, a with the write enable signal WEBpad synchronized high or low signal to an ent speaking bit line. In other words, a ho hes signal applied to the bit line, and in the ferroelek trical capacitor, the logic value 1 is written ben when the signal applied to the plate line in egg ner period is low, in which the word line put signal is high.  

When a low signal is applied to the bit line, becomes the logical value 0 in the ferroelectric condensers Tor registered, if this to the plate line placed signal is high.

Now a reading for the one in through the above Process described in data mode stored data value ben.

If the chip enable signal CSBpad supplied from the outside of high to low will get everyone Bit lines through a compensation signal the same low Voltage before a corresponding word line is selected becomes.

Then the respective bit line becomes inactive and it takes place address decoding. In a corresponding wording device is a low Sig by means of the decoded address nal converted into a high signal, causing the corresponding Cell is selected.

A high is applied to the plate line of the selected cell Signal applied to the stored in the cell, the lo to destroy the corresponding data value 1.

If the logic value 0 ge in the ferroelectric cell is stored, the corresponding data value is not destroyed disturbs.

The destroyed data value and the not destroyed data value are based on the principle mentioned above Hysteresis loop output as different values, so that a sense amplifier detects the logical value 1 or 0.  

In other words, if the data value is destroyed, state d is changed to state f, as represented by the hysteresis loop in FIG. 1. If the data value is not destroyed, state a is changed to state f. Accordingly, when the data value is destroyed, the logic value 1 is output when the sense amplifier is activated after a lapse of a certain time, while in the case of a non-destroyed data value, the logic value 0 is output.

As mentioned above, after the reader amplifier has a Has issued data value, the plate line from the high to stood in the low state disabled while a ho hes signal is applied to the corresponding word line, to restore the original data value.

Fig. 4 is a block diagram of the known memory.

As shown in Fig. 4, the known memory includes a main cell array 41 ; a reference cell array 42 associated with the lower part of the main cell array 41 ; a word line driver 43 formed on one side of the main cell array to apply a drive signal to the main cell array 41 and the reference cell array 42 ; and a sense amplifier 44 formed in the lower part of the reference cell array 42 .

The word line driver 43 applies the drive signal to a main word line of the main cell array 41 and a reference word line of the reference cell array 42 .

The sense amplifier 44 has a number of individual read amplifiers and it amplifies signals of a bit line and an inverse bit line.

The operation of this memory will now be described with reference to FIG. 5, which is a detailed partial view of FIG. 4. As can be seen from the drawing, the main cell array has a folded bit line structure in the same way as a DRAM.

Reference cell array 42 also has a folded bit line structure, and includes a reference cell word line and a reference cell plate line in pairs. The reference cell word line and the reference cell plate line referred to as RWL_1 and RPL_1 or RWL_2 and RPL_2.

When the main cell word line MWL_N-1 and the main cell len plate line MPL_N-1 are activated, the Be pull cell word line RWL_1 and the reference cell plates Line RPL_1 activated. Therefore, the data value is in a Main cell loaded on bit line B / L, and a data value in a reference cell, the inverse bit line BB / L loaded.

If the main cell word line MWL_N and the main cell Plate line MPL_N are activated, the reference cell len word line RWL_2 and the reference cell plate line RPL_2 activated. Therefore, the data value is in a main cell le loaded onto the inverse bit line BB / L, and the data value in a reference cell is loaded on the bit line B / L the.

Fig. 6 is a detailed detailed view of Fig. 4 and shows one of the multiple single sense amplifiers that make up the sense amplifier.

As shown in Fig. 6, the known reading amplifier has the structure of such a latch type.

In other words, the reader amplifier contains two PMOS Transistors and two NMOS transistors, each over Latch type inverter structure. A first PMOS Transistor MP1 and a second PMOS transistor MP2 are one facing others. The output connector of the first PMOS train transistor MP1 is with the gate of the second PMOS transistor MP2 connected, and the output terminal of this second PMOS transistor MP2 is with the gate of the first NMOS train transistor MP1 connected.

To the input connections of the first and second PMOS train A signal SAP is applied jointly to sistors MP1 and MP2. This signal SAP is an active signal that the first and second PMOS transistor MP1 and MP2 activated.

The first NMOS transistor MN1 is connected to the output terminal of the first PMOS transistor MP1 connected in series while de second NMOS transistor MN2 with the output terminal of second NMOS transistor MN2 is connected in series.

The output terminal of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, wäh rend the output terminal of this first NMOS transistor MN1 connected to the gate of the second NMOS transistor MN2 is.

To the input ports of the first and second NMOS tran A signal SAN is applied to sistors MN1 and MN2 together. This signal SAN is an active signal that the first and second NMOS transistor MN1 and MN2 activated.

The output terminals of the first PMOS transistor MP1 and of the first NMOS transistor MN1 are common to the bit line B_N connected while the output terminals of the second PMOS transistor MP2 and the second NMOS transistor  tors MN2 are connected to the next bit line B_N + 1.

The output signal of the sense amplifier is on the Bitlei lines B_N and B_N + 1 given to enter the main cell and the Reference cell to be input and output, thereby I / O operations in the main cell and the reference cell are enabled.

The signal SAP, the signal SAN and the signals B_N and B_N + 1 are all for a precharge period in which the read amplifier is inactive, kept at 1/2 Vcc. On the other hand the SAP signal is pulled to the high level and the Sig nal SAN is pulled to the low level.

Fig. 7 shows a system for sensing signals from an upper cell array and a lower cell array using the known sense amplifier.

The reference number 41 a denotes the upper cell array, and 41 b denotes the lower cell array. In order to acquire data in the upper cell array, a control signal TSEL is transferred to the high level, and another control signal BSEL is transferred to the low level. Accordingly, the path between the lower cell array and the sense amplifier is blocked while the path between the upper cell array and the sense amplifier is opened. Then the read amplifier detects the signal on the bit line and the inverse bit line in the upper cell array.

On the other hand, it is used to collect data in lower cells array a control signal TSEL to the low level leads, and another control signal BSEL is on the high Level transferred. Accordingly, the path between the top Cell array and the sense amplifier locked and the path between the lower cell array and the sense amplifier  open. The sense amplifier detects the signal on the bit line and the inverse bit line of the lower cellar rays.

Accordingly, there is a problem in the known memory that Bit line and inverse bit line loads can differ because the input connection of the read amplifier via a switching component directly with the above ren and lower bit lines is connected. As a result of this Reinforcement process can take place at different loads, the gain can become unstable.

The invention is based on the object, a non-cursed ferroelectric memory with reduced layout area to create.

Another object of the invention is a non-cursed ferroelectric memory with stable gain create.

These tasks are attached by the memory according to the independent claims 1 and 4 solved.

Additional features and objects of the invention are set forth in the following description and partially go out this emerges, but also arise on the other hand when out practice the invention. The tasks and other advantages of the He are achieved through the measures as they are specific in the description, the claims and the appended Drawings are set out.

It should be noted that both the general above Description as well as the following detailed description exemplary and explanatory of the claimed invention are.  

The drawings that are attached to help understand the To promote the invention, exemplary embodiments illustrate of the invention and together with the description serve to explain their principles.

Fig. 1 shows the hysteresis loop of a conventional ferroelectric tricum;

Fig. 2 is a schematic illustration of the unit cell of a known memory;

FIGS. 3a and 3b are timing charts for the operation Veranschauli surfaces of the known memory in write or read mode;

Fig. 4 is a block diagram of the known memory with a cell having a 1T / 1C structure;

Fig. 5 is a detailed partial view of Fig. 4;

Fig. 6 is a detailed schematic view of a reading amplifier in Fig. 4;

Fig. 7 is a block diagram of a cell array and a sense amplifier in the known memory;

Fig. 8 is a block diagram of the unit cell of a SpeI Chers according to an embodiment of the invention;

Fig. 9 is a circuit diagram of the memory of the embodiment;

Fig. 10 is a timing chart for operating the SpeI Chers of the embodiment;

Fig. 11 is a block diagram of a memory management, for example in accordance with the off;

Fig. 12 is a partial enlarged view of Fig. 11;

Fig. 13 is a block diagram of a sense amplifier in the memory of the embodiment;

Fig. 14 shows the change of waveforms at the output node of the sense amplifier shown in Fig. 13;

Fig. 15 is a block diagram of a pull-down sense amplifier in the memory of the embodiment; and

Fig. 16 is a block diagram of a pull-sense amplifier in the memory according to the embodiment.

Now, the preferred embodiments are described in detail Reference of the invention, examples of which in the attached drawings are shown.

As shown schematically in Fig. 8, a unit cell in the memory according to the embodiment has a first and a second sub-word lines SWL1 and SWL2, which are formed with a certain interval in the row direction; a first and a second bit line B / L1 and B / L2 which intersect the first and second partial word lines SWL1 and SWL2; a first transistor T1, the gate of which is connected to the first partial word line SWL1 and the drain of which is connected to the bit line B / L1; a first ferroelectric capacitor FC1 connected between the source of the first transistor T1 and the second partial word line SWL2; a second transistor T2, the gate of which is connected to the second partial word line SWL2 and the drain of which is connected to the second bit line B / L2; and a second ferroelectric capacitor FC2 connected between the source of the second transistor T2 and the first sub-word line SWL1.

A number of unit cells form a cell array. Regarding data storage, a unit cell contains a pair of sub-word lines, a bit line, a transistor 1 T and a ferroelectric capacitor 1 C. Regarding the data structure, the unit cell contains a pair of sub-word lines, two bit lines, two transistors 2 T and two ferroelectric capacitors 2 C .

The operation of this memory will now be described in detail ben.

As shown in the circuit diagram of FIG. 9, a number of partial word line pairs are formed, each with a first and a second partial word line SWL1 and SWL2 in the row direction. Intersecting the partial word line pairs, a number of bit lines B / Ln and B / Ln + 1 is formed. Read amplifiers SA are formed between the respective bit lines, which sense data transmitted via the bit lines and transmit the data to a data line D / L or an inverse data line D / L. A sense amplifier enable section (not shown) and a select switch section CS are also provided. The sense amplifier enable section outputs a sense amplifier enable signal SEN to enable the sense amplifiers SA, and the select switch section CS selectively switches bit lines and data lines.

The operation of this memory will now be described with reference to the timing chart shown in FIG. 10.

A period T0 in FIG. 10 denotes the period before the activation of the first partial word line SWL1 and the second partial word line SWL2 to high (H). In this period T0 who all the bit lines are pre-charged to the threshold voltage level of an NMOS transistor.

A period T1 denotes a period in which the first and second sub-word lines SWL1 and SWL2 all the level H received. In this period T1 the data value in the fer Roelectric capacitor of a main cell to the main bit Transfer line, which changes the bit line level different.

In the case of a ferroelectric capacitor, the logical value high the polarity of the ferroelectric destroyed because of the bit line and the partial word line elec trical fields with opposite polarities so that a large current flows, causing in the bit line a high voltage is generated.

On the other hand, in the case of a ferroelectric condenser with the logical value low the polarity of the ferro Electrical equipment is not destroyed because the electrical fields are the same Polarities indicated on the bit line and the partial word line be placed so that a small current flows, causing in a relatively low voltage is generated on the bit line.

If the cell data is sufficiently on the bit line is loaded, the sense amplifier enable signal SEN transferred high to activate the sense amplifier. In the Er As a result, the bit line level is increased.

The logical data value H in the destroyed cell can in the Zu stood, in which the first and the second partial word line SWL1 and SWL2 are high, not restored  but it can be restored in periods T2 and T3 be put.

Then the first sub-word line SWL1 in the ge called period T2, transferred to low, the second part Word line SWL2 is brought into the high state and the second transistor T2 is turned on. It will be when the corresponding bit line is at a high level, a ho forth data value to an electrode of the second ferroelectric capacitor FC2 transferred, so that the logical value 1 is restored.

The first partial word line SWL1 is opened in the period T3 transferred high, the second sub-word line SWL2 is open transferred low and the first transistor T1 is turned on switches. The logical value 1 is restored, if the corresponding bit line is high.

According to the block diagram shown in FIG. 11, the memory of the exemplary embodiment has a number of cell arrays 11_1 , 11_2 , formed in a matrix. . ., 11 _N; first pulldown sense amplifiers 12_1 , 12_2,. . ., 12 _N formed between vertical cell arrays within the number of cell arrays to pull-down the bit line level of an upper cell array; second pulldown sense amplifiers 14_1 , 14_2,. . ., 14 _N to pull down the bit line level of a lower cell array; and pullup read amplifiers 13_1 , 13_2,. . ., 13 _N by a pull-up gain of the output signal of the first pull-down sense amplifiers 12_1 , 12_2,. . ., 12 _N or the output signal of the second pull-down sense amplifiers 14_1 , 14_2,. . ., 14 _N to make.

The sense amplifiers 15_1 and 15_2 for acquiring data in a cell array at the outermost position in the vertical direction have a system in which the pull-up sense amplifier and either the first or the second pull-down sense amplifier are combined.

That is, one of the two pulldown sense amplifiers is connected to the pullup sense amplifier to form sense amplifiers 15_1 and 15_2 for acquiring the data in the outermost cell array .

In this case, the first pulldown sense amplifiers 12_1 , 12_2,. . ., 12 _N and the second pulldown sense amplifiers 14_1 , 14_2,. . ., 14 _N the same system, but with the exception that the output connection of the first pull-down sense amplifiers 12_1 , 12_2,. . ., 12 _N is connected to the bit line in the upper cell array, while the input connection of the second pulldown sense amplifiers 14_1 , 14_2,. . ., 14 _N is connected to the bit line in the lower cell array. The output connections of the first and second pulldown sense amplifiers are common to the input connection of the pullup sense amplifier 13_1 , 13_2,. . ., 13 _N connected.

Meanwhile, the first pulldown sense amplifiers 12_1 , 12_2,. . ., 12 _N and the pullup sense amplifiers 13_1 , 13_2,. . ., 13 _N activated simultaneously, and also the second pull-down sense amplifiers 14_1 , 14_2,. . ., 14 _N and the pull-up sense amplifiers 13_1 , 13_2,. . ., 13 _N are activated at the same time.

However, when the first pulldown sense amplifiers and the pull up sense amplifiers are active, the second pulldown Sense amplifier kept inactive. In contrast to this kept the first pulldown sense amplifiers inactive when the second pulldown sense amplifiers and the pullup sense ver are more active.  

Fig. 12 is a block diagram showing the first and second pulldown sense amplifiers and a pullup sense amplifier in the memory of the embodiment. Accordingly, a first pull-down sense amplifier 12_1 and a pull-Lesever are combined more 13_1 to form a complete sense amplifier 12 a and a second pull-down sense amplifier 14_1 and the pull-up sense amplifier 13_1 are combined to another full sense amplifier 14 to form a. It should be noted here that the pull-up sense amplifier 13_1 is used in common for each of the pull-down sense amplifiers.

In the memory according to the invention with the above-mentioned system, in order to acquire and amplify a data value in the upper cell array 11_1 , a first pulldown sense amplifier 12_1 and a pullup sense amplifier 13_1 are activated, while the second pulldown sense amplifier 14_1 is not activated.

When the first pulldown sense amplifier 12_1 and the pullup sense amplifier 13_1 are activated and the bit line level in the upper cell array 11_1 is below a reference level, the first pulldown sense amplifier 12_1 carries out a pulldown amplification. When the bit line level in the upper cell array 11_1 is above the reference level, the pull-up sense amplifier 13_1 pull-amplifies the output signal of the first pull-down sense amplifier 12_1 .

On the other hand, in order to acquire and amplify a data value in the lower cell array 11_2 , the second pull- down sense amplifier 14_1 and the pull-up sense amplifier 13_1 are activated, and the first pull-down sense amplifier 12_1 is not activated.

When the second pulldown sense amplifier 14_1 and the pullup sense amplifier 13_1 are activated and the bit line level in the lower cell array 11_2 is below a reference level, the second pulldown sense amplifier 14_1 performs a pulldown gain, and when the bit line level is above the reference level is located, the pull-up sense amplifier 13_1 amplifies the output signal of the second pull-down sense amplifier 14_1 .

Now the sense amplifier is in an extreme position, the a pulldown sense amplifier and a pullup sense amplifier ker has in the memory of the embodiment in the zelnen described the first and second pulldown read amplifier and pull-up sense amplifier.

Fig. 13 is a block diagram of a sense amplifier for detecting data in the outermost cell array of a memory of the embodiment.

Referring to FIG. 13, the sense amplifier has the memory of the embodiment has a first transistor T1 for switching a loaded on the bit line signal; a second transistor T2 for switching a reference signal from a reference signal generating circuit (not shown); a third transistor T3 for switching a signal supplied via the first transistor T1 from the bit line; a fourth transistor T4 for switching a reference signal supplied via the second transistor T2; a fifth transistor T5, the gate of which is connected to the input terminal of the fourth transistor T4 and the drain of which is connected to the output terminal of the third transistor T3; a sixth transistor T6, the gate of which is connected to the input terminal of the third transistor T3 and the drain of which is connected to the output terminal of the fourth transistor T4; a seventh transistor T7 connected between the output terminal of the fifth transistor T5 and a data line D / L and controlled by a column select signal; an eighth transistor T8 connected between the output terminal of the sixth transistor T6 and an inverse data line DB / L and controlled by the column select signal; a ninth transistor T9 whose source is connected to a ground terminal GND and whose drain is connected to the drains of the fifth and sixth transistors T5 and T6; a tenth transistor T10 whose source is connected to a supply voltage terminal Vcc and whose drain is connected to the output terminal of the second transistor T2; an eleventh transistor T11 whose source is connected to the supply voltage terminal and whose drain is connected to both the output terminal of the third transistor T3 and the gate of the tenth transistor T10; and a twelfth transistor T12 for balancing the drains of the tenth transistor T10 and the eleventh transistor T11.

The gate of the eleventh transistor T11 is connected to the drain of the tenth transistor T10 connected.

The first transistor T1 is controlled by a bit line control signal BLC, and the second transistor T2 is controlled by a reference bit line control signal RLC. The third and fourth transistors T3 and T4 are controlled by a latch release control signal LEC. The ninth transistor T9 is controlled by a sense amplifier enable signal SEN. The twelfth transistor T12 is controlled by a sense amplifier compensation signal SEQ. In the waveforms shown at FIG. 14 at nodes SN3 and SN4 of the sense amplifier shown in FIG. 13, A represents a precharge period, B an amplification period, C a pseudolatch period, D an actual latch period and E an output period.

The pull-down sense amplifier shown in the detailed block diagram of FIG. 15 in the memory of the embodiment is part of the sense amplifier shown in FIG. 13.

. The pull-down sense amplifier shown in FIG 15 has a first transistor T1 for switching a signal from the main bit line; a second transistor T2 for switching a reference signal; a third transistor T3 for switching the signal received via the first transistor T1 from the main bit line; a fourth transistor T4 for switching a reference signal received via the second transistor T2; a fifth transistor T5 whose gate is connected to the input terminal of the fourth transistor T4 and whose drain is connected to the output terminal of the third transistor T3; a sixth transistor T6, the gate of which is connected to the input terminal of the third transistor T3 and the drain of which is connected to the output terminal of the fourth transistor T4; and a ninth transistor T9, the source of which is connected to a ground terminal GND and the drain of which is connected to the drains of the fifth and sixth transistors T5 and T6.

When one supplied to the gate of the ninth transistor T9 Sense amplifier enable signal converted to the high level is done by the fifth transistor T5, whose gate receives the reference signal, and the sixth transistor T6, the gate of which receives the signal from the bit line, a ver fortification process.

The output signal is then provided to nodes SN3 and SN4 and then is supplied to nodes SN1 and SN2 in response to the latch release control signal LEC. This means that the output signal is supplied to the cell bit line in response to a bit line control signal BLC via the first and second transistors T1 and T2. The pull-up sense amplifier shown in FIG. 16 in the memory of the exemplary embodiment is part of the sense amplifier shown in FIG. 13. That is, within the sense amplifier shown in Fig. 13, it has the parts excluding the pull-down sense amplifier shown in Fig. 15.

This pullup sense amplifier amplifies this across the nodes SN3 and SN4 supplied signal from the bit line. The knot SN3 is the output terminal of the third transistor T3, and node SN4 is the fourth output terminal Transistor T4.

Because the third and fourth transistors T3 and T4 components in the pullup sense amplifier, it can be said that the Pullup sense amplifier finally a pullup gain of the signal from the bit line that is pulling down sense amplifier is supplied.

The pull-up sense amplifier shown in Fig. 16 has two PMOS transistors T10 and T11, the drains of which are connected to nodes SN3 and SN4, to which a signal is fed from the bit line by the pull-down sense amplifier, and with sources which are connected to a supply voltage terminal Vcc are connected; another PMOS transistor T12 for balancing the drains of the PMOS transistors T10 and T11; and two NMOS transistors T7 and T8 for selectively transferring the pull-up signal to a data line and an inverse data line.

That is, if the data value is on the bit line is above the level of a reference signal, the pull-up read a pullup gain over the third and fourth transistor T3 and T4 in the pulldown sense amplifier transmitted bit line signal executes. This process he  follows in reading mode.

If, on the other hand, the data value on the data line and the inverse data line in write mode above the level of Be train signal is located, the bit line signal by the Pullup sense amplifier pullup amplified, it goes through the Nodes SN3 and SN4 and it will be over the third and fourth Transistor T3 and T4 and the first and second transistor T1 and T2 in the pulldown sense amplifier to the bit line delivers.

In the pullup sense amplifier above, the twelfth transis is used gate T12 not only for balancing nodes SN3 and SN4, but it also prevents the pullup sense amplifier switches to a latch mode, even though a through the nodes SN3 and SN4 induced signal by the pull down sense amplifier is amplified. Accordingly, a ver Strengthening always take place when the input signal changes. Therefore, the twelfth transistor T12 during the entire precharge period and the amplification period of the Input sense amplifiers held in the on state will.

As explained, the non-volatile according to the invention ferroelectric memory about the advantage that reading amplifiers each into a pulldown sense amplifier and egg a pull-up sense amplifier are divided, the pull-up Sense amplifiers from an upper and a lower cellar ray arranged in the vertical direction in common is used what is allowed by the sense amplifier to minimize the occupied area in order to achieve an effective ver lightening of the layout and fol for stability to provide a reinforcement process.

Claims (19)

1. Non-volatile ferroelectric memory with a number of cell arrays in a matrix, with:

• - A number of pulldown sense amplifiers ( 12_1 , 12_2 , ... , 12 _N and 14_1 , 14_2 , ... , 14 _N), which are formed between cell arrays arranged in the vertical direction so that they correspond to them by one Perform pulldown amplification of data in an appropriate cell array; and
• - A pull-up sense amplifier ( 13_1 , 13_2 , ... , 13 _N) which is shared by an upper and a lower cell array in order to carry out a selective pull-up amplification of a data value in the upper cell array or one in the lower cell array .

2. Memory according to claim 1, characterized in that the sense amplifier for acquiring a data value in one Cell array at the outermost position a combination of a pulldown sense amplifier and a pullup sense amplifier ker has. 3. Memory according to claim 1, characterized in that with respect to a pulldown sense amplifier corresponding to the cell arrays, that pulldown sense amplifier ( 12_1 ) and the pullup sense amplifier ( 13_1 ), both of which correspond to an upper cell array ( 11_1 ), are activated simultaneously or a pulldown sense amplifier ( 14_1 ) and the pullup sense amplifier ( 13_1 ), both of which correspond to a lower cell array ( 11_2 ), are activated simultaneously. 4. Non-volatile ferroelectric memory with:

• - a first and a second cell array ( 11_1 , 11_2 ) which are arranged in the vertical direction;
• - A first and a second sub-word line driver for supplying a drive signal to the corresponding cell lenarray;
• - a first pulldown sense amplifier ( 12_1 ) for selectively performing pulldown amplification of a data value in the first cell array;
• - a second pulldown sense amplifier ( 14_1 ) for selectively performing pulldown amplification of a data value in the second cell array ( 11_2 ); and
• - A pull-up sense amplifier ( 13_1 ), which is shared by the first and second cell arrays in order to carry out a selective pull-up amplification of a data value in each of the cell arrays.

5. A memory according to claim 4, characterized in that the first or second pull-down sense amplifier (12_1, 14_1) is activated simultaneously with the pull-sense amplifier (13_l). 6. The memory of claim 4, characterized in that when the first pulldown sense amplifier ( 12_1 ) and the pullup sense amplifier ( 13_1 ) are activated and the bit line level of the first cell array ( 11_1 ) is above a reference level, the first pulldown Sense amplifier pull-down amplifies, and when the bit line level is below the reference level, the pull-up sense amplifier pull-up the output signal of the first pull-down sense amplifier. 7. The memory according to claim 4, characterized in that in a state in which the second pulldown sense amplifier ( 14_1 ) and the pullup sense amplifier ( 13_1 ) are activated and the bit line level of the second cell array ( 11_2 ) is above a reference level which Pull-up sense amplifier pull-up amplifies the output of the second pull-down sense amplifier, and when the bit line level is below the reference level, the second pull-down sense amplifier performs pull-down gain. 8. Memory according to one of claims 6 or 7, characterized in that the pull-up sense amplifier ( 13_1 ) carries out a pull-up amplification of a bit line signal received via the pull-down sense amplifier ( 12_1 , 14_1 ). 9. Memory according to claim 4, characterized in that a number of first and second cell arrays ( 11_1 , 11_2 ) is formed in a matrix. 10. The memory as claimed in claim 9, characterized in that the sense amplifier for detecting a data value in the cell array at the outermost position among the number of first and second cell arrays is a combination of the first and second pull-down sense amplifiers ( 12_1 , 14_1 ) and the pull-up Sense amplifier ( 13_1 ). 11. The memory according to claim 4, characterized in that the first and the second pull-down sense amplifier ( 12_1 , 14_1 ) have the same system. 12. The memory as claimed in claim 10, characterized in that the sense amplifier for detecting a data value in the cell array has the following at the outermost position:

• - a first transistor (T1) for switching a signal from a main bit line;
• - A second transistor (T2) for switching a reference signal;
• - A third transistor (T3), which is controlled by a Latchfreiga be control signal LEC to switch the signal from the first transistor;
• - A fourth transistor (T4), which is controlled by the Latchfreiga control signal to switch the signal from the second transistor;
• - A fifth transistor (T5), the gate of which is connected to the input terminal of the fourth transistor and the drain of which is connected to the output terminal of the third transistor;
• - A sixth transistor (T6) whose gate is connected to the input terminal of the third transistor and whose drain is connected to the output terminal of the fourth transistor;
• - A seventh transistor (T7), which is formed between the output terminal of the fifth transistor and a data line B / L and is controlled by a column selection signal CS;
• - An eighth transistor (T8) which is formed between the output terminal of the sixth transistor and an inverse data line (DB / L) and is controlled by the column control signal;
• - A ninth transistor (T9), the drain of which is connected to the sources of the fifth and sixth transistor and the source of which is connected to a ground terminal (GND) and which operates in response to a sense amplifier enable signal (SEN);
• - A tenth transistor (T10), the source of which is connected to a supply voltage terminal (Vcc) and the drain of which is connected to the output terminal of the third transistor;
• - An eleventh transistor (T11), the source of which is connected to the supply voltage terminal and the drain of which is connected in common to the output terminal of the fourth transistor and the drain of the tenth transistor; and
• - A twelfth transistor (T12) for balancing the drains of the tenth and eleventh transistors.

13. The memory according to claim 12, characterized in that the tenth, eleventh and twelfth transistor (T10, T11 and T12) Are PMOS transistors and the other transistors are NMOS Are transistors. 14. Memory according to claim 12, characterized in that the third and fourth transistor (T3, T4) during the Writing data kept on be turned off and while reading data in the Condition. 15. The memory according to claim 10, characterized in that the pull-up sense amplifier ( 13_1 ) has the following:

• - A seventh transistor (T7) which is formed between the output terminal of the fifth transistor (T5) and a data line and is controlled by the column selection signal;
• - An eighth transistor (T8) which is formed between the output terminal of the sixth transistor (T6) and an inverse data line and is controlled by the column control signal;
• - A tenth transistor (T10), the source of which is connected to the supply voltage terminal (Vcc) and the drain of which is connected to the output terminal of the third transistor;
• - An eleventh transistor (T11), the source of which is connected to the supply voltage terminal and the drain of which is connected in common to the output terminal of the fourth transistor and the gate of the tenth transistor; and
• - A twelfth transistor (T12) for balancing the drains of the tenth and eleventh transistors.

16. The memory according to claim 10, characterized in that the first pull-down sense amplifier ( 12_1 ) has the following:

• - a first transistor (T1) for switching the signal from a main bit line of the first cell array ( 11_1 ) within the first and second cell arrays ( 11_1 , 12_1 );
• - A second transistor (T2) for switching a reference signal;
• - A third transistor (T3), which is controlled by a latch release control signal (LEC) in order to switch the signal from the first transistor;
• - A fourth transistor (T4), which is controlled by the Latchfreiga control signal to switch the signal from the second transistor;
• - A fifth transistor (T5), the gate of which is connected to the input terminal of the fourth transistor and the drain of which is connected to the output terminal of the third transistor;
• - A sixth transistor (T6) whose gate is connected to the input terminal of the third transistor and whose drain is connected to the output terminal of the fourth transistor; and
• - A ninth transistor (T9), whose source is connected to a ground connection and whose drain is connected to the drains of the fifth and sixth transistor.

17. The memory according to claim 16, characterized in that the transistors in the first pull-down sense amplifier ( 12_1 ) are NMOS transistors. 18. Memory according to claim 16, characterized in that the drain of the fifth transistor (T5) with the drain of the tenth transistor (T10) is connected and the drain of the sixth transistor (T6) with the drain of the eleventh transistor tors (T11) is connected.   19. Memory according to claim 10, characterized in that the second pulldown sense amplifier ( 14_1 ) has the same system as the first pulldown sense amplifier ( 12_1 ) and the first transistor (T1) receives the signal from a main bit line in the second cell array ( 11_2 ) switches within the first and second cell arrays ( 11_1 , 11_2 ).