JP5030993B2 - 発光装置、半導体装置、表示モジュール及び電子機器 - Google Patents
発光装置、半導体装置、表示モジュール及び電子機器 Download PDFInfo
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- JP5030993B2 JP5030993B2 JP2009112374A JP2009112374A JP5030993B2 JP 5030993 B2 JP5030993 B2 JP 5030993B2 JP 2009112374 A JP2009112374 A JP 2009112374A JP 2009112374 A JP2009112374 A JP 2009112374A JP 5030993 B2 JP5030993 B2 JP 5030993B2
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Description
I=μC0W/L(VGS−VTH)2/2
図2に本発明の発光パネルの構成を、ブロック図で示す。100は画素部であり、複数の画素101がマトリクス状に形成されている。また102は信号線駆動回路、103は走査線駆動回路である。
また図5は、書き込み期間Taと表示期間TdにおけるトランジスタTr1とトランジスタTr2の接続を、簡単に示した図である。
発光素子に流れる電流は、定電流源107において定められた信号電流Icに応じた大きさであり、流れる電流の大きさに見合った輝度で発光素子104は発光する。発光素子に流れる電流が0に限りなく近かったり、発光素子に流れる電流が逆バイアスの方向に流れたりする場合は、発光素子104は発光しない。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
本実施の形態では、図2に示した発光装置が有する画素101の、図3とは異なる構成について説明する。
このときトランジスタTr1は、ゲートとドレインが接続されているので飽和領域で動作しており、式1が成り立つ。よって、トランジスタTr1のゲート電圧VGSは電流値Icによって定まる。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
本実施の形態では、図2に示した発光装置が有する画素101の、図3、図6とは異なる構成について説明する。本実施の形態は図6におけるTr5とTr6の位置を変えたものである。どちらか一方だけ変えても良い。
このときトランジスタTr1は、ゲートとドレインが接続されているので飽和領域で動作しており、式1が成り立つ。よって、トランジスタTr1のゲート電圧VGSは電流値Icによって定まる。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
本実施の形態では、本発明の第2の構成の発光装置が有する画素の構成について説明する。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
本実施の形態では、本発明の第2の構成の発光装置が有する画素の構成について説明する。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
実施の形態1〜5では、ビデオ信号がアナログの場合について説明したが、デジタルのビデオ信号を用いて駆動させることも可能である。
そして書き込み期間Taと表示期間Tdにおける画素の動作は、図3に示した画素の場合と同じであり、実施の形態1の図4及び図5を参照することができるので、ここでは説明を省略する。
そして書き込み期間Taと表示期間Tdにおける画素の動作は、図3に示した画素の場合と同じであり、実施の形態1の図5を参照することができるので、ここでは説明を省略する。
そして書き込み期間Taと表示期間Tdにおける画素の動作は、図3に示した画素の場合と同じであり、実施の形態1の図5を参照することができるので、ここでは説明を省略する。
、電力密度0.5〜0.8W/cm2で放電させて形成することが出来る。このようにして作製される酸化シリコン膜は、その後400〜500℃の熱アニールによりゲート絶縁膜として良好な特性を得ることが出来る。
ゲート絶縁膜上に残渣を残すことなくエッチングするためには、10〜20%程度の割合でエッチング時間を増加させると良い。W膜に対する酸化窒化シリコン膜の選択比は2〜4(代表的には3)であるので、オーバーエッチング処理により、酸化窒化シリコン膜が露出した面は20〜50nm程度エッチングされることになる。こうして、第1のエッチング処理により第1の導電層と第2の導電層から成る第1の形状の導電層5011〜5016(第1の導電層5011a〜5016aと第2の導電層5011b〜5016b)を形成する。このとき、ゲート絶縁膜5007においては、第1の形状の導電層5011〜5016で覆われない領域は20〜50nm程度エッチングされ薄くなった領域が形成される。(図13(B))
ドーピングの方法はイオンドープ法もしくはイオン注入法で行えば良い。イオンドープ法の条件はドーズ量を1×1013〜5×1014atoms/cm2とし、加速電圧を60〜100keVとして行う。N型を付与する不純物元素として15族に属する元素、典型的にはリン(P)または砒素(As)を用いるが、ここではリン(P)を用いる。この場合、導電層5011〜5014がN型を付与する不純物元素に対するマスクとなり、自己整合的に第1の不純物領域5017〜5025が形成される。第1の不純物領域5017〜5024には1×1020〜1×1021atoms/cm3の濃度範囲でN型を付与する不純物元素を添加する。(図13(B)
)
の濃度は、第1の導電層5026a〜5029aのテーパー部の膜厚に従って緩やかな濃度勾配を有している。なお、第1の導電層5026a〜5029aのテーパー部と重なる半導体層において、第1の導電層5026a〜5029aのテーパー部の端部から内側に向かって若干、不純物濃度が低くなっているものの、ほぼ同程度の濃度である。
熱アニール法では酸素濃度が1ppm以下、好ましくは0.1ppm以下の窒素雰囲気中で400〜700℃、代表的には500〜600℃で行うものであり、本実施例では500℃で4時間の熱処理を行う。ただし、第3の形状の導電層5037〜5042に用いた配線材料が熱に弱い場合には、配線等を保護するため層間絶縁膜(シリコンを主成分とする)を形成した後で活性化を行うことが好ましい。
レーザーアニール法を用いる場合、結晶化の際に用いたレーザーを使用することが可能である。活性化の場合は、移動速度は結晶化と同じにし、0.01〜100MW/cm2程度(好ましくは0.01〜10MW/cm2)のエネルギー密度が必要となる。
なお、配線の位置や半導体層の位置を明確にするために、絶縁膜や層間絶縁膜は省略した。図17のA−A’における断面図が、図15(A)のA−A’に示した部分に相当する。また、図17のB−B’における断面図が、図15(A)のB−B’に示した部分に相当する。また、図17のC−C’における断面図を、図16に示す。
は、一方は配線5102に接続されており、もう一方は信号線Si5060に接続されている。また、ゲート電極5101は配線5107に接続されており、配線5107は第2走査線Pjに接続されている。
は、一方は電源線Vi(5110)に接続されており、もう一方は配線5061に接続されている。また、ゲート電極5104は容量用電極5109に接続されている。
は、一方は電源線Vi(5110)に接続されており、もう一方は配線5062に接続されている。また、ゲート電極5106は容量用電極5109に接続されている。
は、一方は配線5061に接続されており、もう一方は配線5062に接続されている。また、ゲート電極5040は、配線5041を介して第3走査線Rjに接続されている。
記憶回路A603が有する複数のステージのラッチをいくつかのグループに分け、各グループごとに並行して同時にデジタルビデオ信号を入力する、いわゆる分割駆動を行っても良い。なおこのときのグループの数を分割数と呼ぶ。例えば4つのステージごとにラッチをグループに分けた場合、4分割で分割駆動すると言う。
(T.Tsutsui, C.Adachi, S.Saito, Photochemical Processes in Organized Molecular Systems, ed.K.Honda, (Elsevier Sci.Pub., Tokyo,1991) p.437.)
フィルム、マイラーフィルム、ポリエステルフィルムまたはアクリル樹脂フィルムを用いることができる。また、アルミニウムホイルをPVFフィルムやマイラーフィルムで挟んだ構造のシートを用いることもできる。
[POPT]、ポリ[3−(4−オクチルフェニル)−2,2ビチオフェン][PTOPT]等が挙げられる。
発光素子に流れる電流は、定電流源707において定められた信号電流Icに応じた大きさであり、流れる電流の大きさに見合った輝度で発光素子704は発光する。発光素子に流れる電流が0に限りなく近かったり、発光素子に流れる電流が逆バイアスの方向に流れたりする場合は、発光素子704は発光しない。
なお、第1走査線G及び第2走査線Pは選択されていないので、トランジスタTr3及びTr4はオフになっている。
I3=I1×L1/(L1+L6)
また、第1〜3走査線に印加される電圧については、図4に示したタイミングチャートを参照することができる。また図31は、図30に示した画素の、書き込み期間Taと表示期間TdにおけるトランジスタTr1とトランジスタTr2の接続を、簡単に示した図である。
発光素子に流れる電流は、定電流源737において定められた信号電流Icに応じた大きさであり、流れる電流の大きさに見合った輝度で発光素子730は発光する。発光素子に流れる電流が0に限りなく近かったり、発光素子に流れる電流が逆バイアスの方向に流れたりする場合は、発光素子730は発光しない。
なお、第1走査線G及び第2走査線Pは選択されていないので、トランジスタTr3及びTr4はオフになっている。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
また、第1〜3走査線に印加される電圧については、図4に示したタイミングチャートを参照することができる。また図33は、図32に示した画素の、書き込み期間Taと表示期間TdにおけるトランジスタTr1とトランジスタTr2の接続を、簡単に示した図である。
発光素子に流れる電流は、定電流源765において定められた信号電流Icに応じた大きさであり、流れる電流の大きさに見合った輝度で発光素子760は発光する。発光素子に流れる電流が0に限りなく近かったり、発光素子に流れる電流が逆バイアスの方向に流れたりする場合は、発光素子760は発光しない。
なお、第1走査線G及び第2走査線Pは選択されていないので、トランジスタTr3及びTr4はオフになっている。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
また、第1〜3走査線に印加される電圧については、図4に示したタイミングチャートを参照することができる。また図35は、図34に示した画素の、書き込み期間Taと表示期間TdにおけるトランジスタTr1とトランジスタTr2の接続を、簡単に示した図である。
なお、第1走査線G及び第2走査線Pは選択されていないので、トランジスタTr3及びTr4はオフになっている。
1つのフレーム期間において1つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Taが開始されて、上述した動作が繰り返される。
Claims (10)
- nチャネル型の第1のトランジスタと、nチャネル型の第2のトランジスタと、発光素子と、配線と、を有する発光装置であって、
前記第1のトランジスタのゲートと前記第2のトランジスタのゲートとは電気的に接続され、
前記第1のトランジスタのドレインと前記第2のトランジスタのドレインとは電気的に接続され、
前記配線は、ビデオ信号を供給することができる機能を有し、
第1の期間において、
前記第1のトランジスタのゲートと前記第1のトランジスタのドレインとは導通し、かつ、
前記第1のトランジスタのソースと前記第2のトランジスタのソースと前記配線とは導通し、
第2の期間において、
前記第2のトランジスタのソースと発光素子とは導通し、かつ、
前記第1のトランジスタのソースはフローティング状態であることを特徴とする発光装置。 - nチャネル型の第1のトランジスタと、nチャネル型の第2のトランジスタと、発光素子と、配線と、を有する発光装置であって、
前記第1のトランジスタのゲートと前記第2のトランジスタのゲートとは電気的に接続され、
前記第1のトランジスタのドレインと前記第2のトランジスタのドレインとは電気的に接続され、
前記配線は、ビデオ信号を供給することができる機能を有し、
第1の期間において、
前記第1のトランジスタのゲートと前記第1のトランジスタのドレインとは導通し、かつ、
前記第1のトランジスタのソースと前記第2のトランジスタのソースと前記配線とは導通し、
第2の期間において、
前記第1のトランジスタのゲートと前記第1のトランジスタのドレインとは非導通にされ、
第3の期間において、
前記第2のトランジスタのソースと発光素子とは導通し、かつ、
前記第1のトランジスタのソースはフローティング状態であることを特徴とする発光装置。 - 請求項1または請求項2において、
容量素子を有し、
前記容量素子の第1の電極は、前記第2のトランジスタのゲートと電気的に接続され、
前記容量素子の第2の電極は、前記第2のトランジスタのソースと電気的に接続されていることを特徴とする発光装置。 - 請求項3において、
前記第1の期間において、
前記容量素子の第2の電極は、前記第2のトランジスタのソースと導通し、
前記第2の期間において、
前記容量素子の第2の電極は、前記第2のトランジスタのソースと導通していることを特徴とする発光装置。 - nチャネル型の第1のトランジスタと、nチャネル型の第2のトランジスタと、配線と、を有する半導体装置であって、
前記第1のトランジスタのゲートと前記第2のトランジスタのゲートとは電気的に接続され、
前記第1のトランジスタのドレインと前記第2のトランジスタのドレインとは電気的に接続され、
前記配線は、ビデオ信号を供給することができる機能を有し、
第1の期間において、
前記第1のトランジスタのゲートと前記第1のトランジスタのドレインとは導通し、かつ、
前記第1のトランジスタのソースと前記第2のトランジスタのソースと前記配線とは導通し、
第2の期間において、
前記第2のトランジスタのソースと画素電極とは導通し、かつ、
前記第1のトランジスタのソースはフローティング状態であり、
前記画素電極は、発光素子の一部として用いることができることを特徴とする半導体装置。 - nチャネル型の第1のトランジスタと、nチャネル型の第2のトランジスタと、配線と、を有する半導体装置であって、
前記第1のトランジスタのゲートと前記第2のトランジスタのゲートとは電気的に接続され、
前記第1のトランジスタのドレインと前記第2のトランジスタのドレインとは電気的に接続され、
前記配線は、ビデオ信号を供給することができる機能を有し、
第1の期間において、
前記第1のトランジスタのゲートと前記第1のトランジスタのドレインとは導通し、かつ、
前記第1のトランジスタのソースと前記第2のトランジスタのソースと前記配線とは導通し、
第2の期間において、
前記第1のトランジスタのゲートと前記第1のトランジスタのドレインとは非導通にされ、
第3の期間において、
前記第2のトランジスタのソースと画素電極とは導通し、かつ、
前記第1のトランジスタのソースはフローティング状態であり、
前記画素電極は、発光素子の一部として用いることができることを特徴とする半導体装置。 - 請求項5または請求項6において、
容量素子を有し、
前記容量素子の第1の電極は、前記第2のトランジスタのゲートと電気的に接続され、
前記容量素子の第2の電極は、前記第2のトランジスタのソースと電気的に接続されていることを特徴とする半導体装置。 - 請求項7において、
前記第1の期間において、
前記容量素子の第2の電極は、前記第2のトランジスタのソースと導通し、
前記第2の期間において、
前記容量素子の第2の電極は、前記第2のトランジスタのソースと導通していることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一に記載の発光装置、または、請求項5乃至請求項8のいずれか一に記載の半導体装置と、FPCと、を有する表示モジュール。
- 請求項1乃至請求項4のいずれか一に記載の発光装置、請求項5乃至請求項8のいずれか一に記載の半導体装置、または、請求項9に記載の表示モジュールと、アンテナ、スピーカー、操作キー、または、バッテリと、を有する電子機器。
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KR20030019194A (ko) | 2003-03-06 |
US7046240B2 (en) | 2006-05-16 |
US20060256046A1 (en) | 2006-11-16 |
US20090021539A1 (en) | 2009-01-22 |
US20140225884A1 (en) | 2014-08-14 |
TW546600B (en) | 2003-08-11 |
CN1407629A (zh) | 2003-04-02 |
US7411586B2 (en) | 2008-08-12 |
JP5448277B2 (ja) | 2014-03-19 |
US20030062524A1 (en) | 2003-04-03 |
US8704736B2 (en) | 2014-04-22 |
US8482491B2 (en) | 2013-07-09 |
CN101257743B (zh) | 2011-05-25 |
CN100371962C (zh) | 2008-02-27 |
CN101257743A (zh) | 2008-09-03 |
JP2009169442A (ja) | 2009-07-30 |
KR100910166B1 (ko) | 2009-07-30 |
US8982021B2 (en) | 2015-03-17 |
JP2012155327A (ja) | 2012-08-16 |
US20140015738A1 (en) | 2014-01-16 |
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