JP4959116B2 - 選択トランジスタを有するeepromの製造方法 - Google Patents
選択トランジスタを有するeepromの製造方法 Download PDFInfo
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- JP4959116B2 JP4959116B2 JP2004064441A JP2004064441A JP4959116B2 JP 4959116 B2 JP4959116 B2 JP 4959116B2 JP 2004064441 A JP2004064441 A JP 2004064441A JP 2004064441 A JP2004064441 A JP 2004064441A JP 4959116 B2 JP4959116 B2 JP 4959116B2
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- Prior art keywords
- gate
- pattern
- interlayer dielectric
- active region
- conductive film
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- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000010410 layer Substances 0.000 claims description 74
- 239000011229 interlayer Substances 0.000 claims description 62
- 230000002093 peripheral effect Effects 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims 5
- 210000004027 cell Anatomy 0.000 description 36
- 238000005530 etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 210000000352 storage cell Anatomy 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
54 第1活性領域
GSL 接地選択ライン
SSL 列選択ライン
WL ワードライン
CSL 共通ソースライン
60a 第1導電膜パターン
60b 下部ゲートパターン
60f 浮遊ゲート
62a 第1ゲート層間誘電膜
62b 第2ゲート層間誘電膜
68a 制御ゲート電極
68b 上部ゲートパターン
70a 第1ハードマスクパターン
70b 第2ハードマスクパターン
78 ビットラインプラグ
Claims (4)
- 半導体基板に素子分離膜を形成して複数個の平行な活性領域を画定する段階と、
前記活性領域上に第1導電膜パターンを形成する段階と、
前記第1導電膜パターンが形成された基板上にコンフォーマルなゲート層間誘電膜を形成する段階と、
前記ゲート層間誘電膜をパターニングして前記活性領域の上部を横切り、隣り合う一対の選択ラインが形成される領域に重畳されるようにオープニングを形成する段階と、
前記オープニングが形成された基板の全面に第2導電膜を形成する段階と、
前記第2導電膜、前記ゲート層間誘電膜及び前記第1導電膜パターンを順次にパターニングして、前記活性領域の上部を横切るワードラインと、前記オープニングに一部重畳して前記オープニングと平行に前記活性領域の上部を横切る一対の選択ラインを形成する段階とを含むことを特徴とする不揮発性記憶素子の製造方法。 - 前記ゲート層間誘電膜上にマスク導電膜をコンフォーマルに形成する段階をさらに含み、前記オープニングは前記マスク導電膜及び前記ゲート層間誘電膜を順次にパターニングして形成することを特徴とする請求項1に記載の不揮発性記憶素子の製造方法。
- 前記ワードライン及び前記一対の選択ラインを形成する段階は、
前記ゲート層間誘電膜をエッチング阻止膜として使用して前記第2導電膜及び前記オープニングに露出した前記第1導電膜パターンをパターニングして、前記活性領域の上部を横切る制御ゲート電極と、前記制御ゲート電極と隣接して前記活性領域の上部を横切る上部ゲートパターンを形成する段階と、
前記ゲート層間誘電膜及び前記第1導電膜をパターニングして前記制御ゲート電極及び前記上部ゲートパターンの下部に各々整列された浮遊ゲート及び下部ゲートパターンを形成する段階とを含むことを特徴とする請求項1に記載の不揮発性記憶素子の製造方法。 - セル領域及び周辺領域が定義された半導体基板に素子分離膜を形成して、前記セル領域に複数個の平行な第1活性領域を画定し、前記周辺領域に第2活性領域を画定する段階と、
前記半導体基板上に第1導電膜を形成する段階と、
前記セル領域の前記第1導電膜をパターニングして前記第1活性領域上に第1導電膜パターンを形成する段階と、
前記第1導電膜パターンが形成された基板上にコンフォーマルなゲート層間誘電膜を形成する段階と、
前記ゲート層間誘電膜をパターニングして前記第1活性領域の上部を横切り、隣り合う一対の選択ラインが形成される領域に重畳するようにオープニングを形成すると同時に前記周辺領域の第1導電膜を露出させる段階と、
前記オープニングが形成された基板の全面に第2導電膜を形成する段階と、
前記第2導電膜、前記ゲート層間誘電膜、前記第1導電膜パターン及び前記周辺領域の前記第1導電膜を順次にパターニングして、前記第1活性領域の上部を横切るワードラインと、前記オープニングに一部重畳して前記オープニングと平行に前記第1活性領域の上部を横切る一対の選択ラインと、前記第2活性領域の上部を横切る周辺回路ゲートパターンを形成する段階とを含むことを特徴とする不揮発性記憶素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0014853A KR100487560B1 (ko) | 2003-03-10 | 2003-03-10 | 선택 트랜지스터를 갖는 이이피롬 및 그 제조방법 |
KR2003-014853 | 2003-03-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004274062A JP2004274062A (ja) | 2004-09-30 |
JP4959116B2 true JP4959116B2 (ja) | 2012-06-20 |
Family
ID=36584505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004064441A Expired - Fee Related JP4959116B2 (ja) | 2003-03-10 | 2004-03-08 | 選択トランジスタを有するeepromの製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7061044B2 (ja) |
JP (1) | JP4959116B2 (ja) |
KR (1) | KR100487560B1 (ja) |
CN (1) | CN100403542C (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
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US8421143B2 (en) | 2000-09-26 | 2013-04-16 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having element isolating region of trench type |
JP2002176114A (ja) * | 2000-09-26 | 2002-06-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4377676B2 (ja) * | 2003-12-24 | 2009-12-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR100650817B1 (ko) * | 2004-04-19 | 2006-11-27 | 에스티마이크로일렉트로닉스 엔.브이. | 난드형 플래쉬 메모리 소자 및 그 제조 방법 |
US7348236B2 (en) * | 2004-06-28 | 2008-03-25 | Micron Technology, Inc. | Formation of memory cells and select gates of NAND memory arrays |
KR100655285B1 (ko) * | 2004-11-04 | 2006-12-08 | 삼성전자주식회사 | 적층 게이트를 가지는 반도체 소자 및 그 제조방법 |
US7283392B2 (en) | 2005-04-26 | 2007-10-16 | Samsung Electronics Co., Ltd. | NAND flash memory device and methods of its formation and operation |
KR100805053B1 (ko) * | 2005-05-23 | 2008-02-20 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조방법 |
KR100697286B1 (ko) * | 2005-05-31 | 2007-03-20 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 형성 방법 |
KR100799029B1 (ko) * | 2005-07-26 | 2008-01-28 | 주식회사 하이닉스반도체 | 자기 정렬 플로팅 게이트를 갖는 플래쉬 메모리 소자의제조방법 |
KR100660543B1 (ko) * | 2005-10-24 | 2006-12-22 | 삼성전자주식회사 | 낸드형 플래시 메모리 장치 및 그 제조 방법 |
JP4664813B2 (ja) * | 2005-12-21 | 2011-04-06 | 株式会社東芝 | 半導体記憶装置 |
CN100461376C (zh) * | 2006-02-14 | 2009-02-11 | 力晶半导体股份有限公司 | 非易失存储器的制造方法 |
CN100452362C (zh) * | 2006-02-14 | 2009-01-14 | 力晶半导体股份有限公司 | 非易失存储器及其制造方法 |
KR100782488B1 (ko) * | 2006-08-24 | 2007-12-05 | 삼성전자주식회사 | 매립 배선들을 갖는 반도체소자 및 그 제조방법 |
KR100806344B1 (ko) * | 2006-10-20 | 2008-03-03 | 삼성전자주식회사 | 비휘발성 기억 소자 및 그 형성 방법 |
KR100822803B1 (ko) * | 2006-10-20 | 2008-04-18 | 삼성전자주식회사 | 비휘발성 기억 장치 및 그 제조 방법 |
KR100882741B1 (ko) * | 2007-05-16 | 2009-02-09 | 삼성전자주식회사 | 불휘발성 메모리 장치의 제조 방법 및 불휘발성 메모리장치 |
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
KR101426845B1 (ko) * | 2007-12-05 | 2014-08-14 | 삼성전자주식회사 | 공통 소스를 포함하는 비휘발성 기억 소자 |
US8390049B2 (en) * | 2008-10-21 | 2013-03-05 | Macronix International Co., Ltd. | Structure of semiconductor device |
TWI409958B (zh) * | 2008-11-03 | 2013-09-21 | Macronix Int Co Ltd | 一種半導體元件結構 |
US8169827B2 (en) * | 2009-02-20 | 2012-05-01 | Hynix Semiconductor Inc. | NAND flash memory string apparatus and methods of operation thereof |
JP2012204591A (ja) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | 膜形成方法および不揮発性記憶装置 |
US9397209B2 (en) | 2012-10-22 | 2016-07-19 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method of forming a large pattern and a plurality of fine gate lines located between the large patterns |
TWI493713B (zh) * | 2012-10-22 | 2015-07-21 | Macronix Int Co Ltd | 半導體結構與其製造方法 |
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IT1196997B (it) * | 1986-07-25 | 1988-11-25 | Sgs Microelettronica Spa | Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati |
JPH07183411A (ja) * | 1993-11-09 | 1995-07-21 | Sony Corp | 積層ゲート型不揮発性半導体記憶装置 |
US5894146A (en) * | 1995-02-28 | 1999-04-13 | Sgs-Thomson Microelectronics, S.R.L. | EEPROM memory cells matrix with double polysilicon level and relating manufacturing process |
US6159800A (en) * | 1997-04-11 | 2000-12-12 | Programmable Silicon Solutions | Method of forming a memory cell |
IT1302282B1 (it) * | 1998-09-29 | 2000-09-05 | St Microelectronics Srl | Cella di memoria eeprom comprendente transistore di selezione contensione di soglia regolata mediante impianto, e relativo processo di |
JP3878361B2 (ja) * | 1999-06-29 | 2007-02-07 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
US6218689B1 (en) * | 1999-08-06 | 2001-04-17 | Advanced Micro Devices, Inc. | Method for providing a dopant level for polysilicon for flash memory devices |
JP2002176114A (ja) * | 2000-09-26 | 2002-06-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US6541324B1 (en) * | 2001-11-02 | 2003-04-01 | Silicon Storage Technology, Inc. | Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region |
-
2003
- 2003-03-10 KR KR10-2003-0014853A patent/KR100487560B1/ko not_active IP Right Cessation
-
2004
- 2004-03-08 JP JP2004064441A patent/JP4959116B2/ja not_active Expired - Fee Related
- 2004-03-09 US US10/797,754 patent/US7061044B2/en not_active Expired - Fee Related
- 2004-03-10 CN CNB2004100430716A patent/CN100403542C/zh not_active Expired - Fee Related
-
2006
- 2006-01-27 US US11/341,073 patent/US7344944B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20060128070A1 (en) | 2006-06-15 |
CN100403542C (zh) | 2008-07-16 |
US20040178456A1 (en) | 2004-09-16 |
US7344944B2 (en) | 2008-03-18 |
US7061044B2 (en) | 2006-06-13 |
KR20040080019A (ko) | 2004-09-18 |
JP2004274062A (ja) | 2004-09-30 |
KR100487560B1 (ko) | 2005-05-03 |
CN1534789A (zh) | 2004-10-06 |
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