JP4723714B2 - 半導体集積回路装置およびその検査方法 - Google Patents

半導体集積回路装置およびその検査方法 Download PDF

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Publication number
JP4723714B2
JP4723714B2 JP2000305402A JP2000305402A JP4723714B2 JP 4723714 B2 JP4723714 B2 JP 4723714B2 JP 2000305402 A JP2000305402 A JP 2000305402A JP 2000305402 A JP2000305402 A JP 2000305402A JP 4723714 B2 JP4723714 B2 JP 4723714B2
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JP
Japan
Prior art keywords
data
trimming
fuse element
register
circuit
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Expired - Fee Related
Application number
JP2000305402A
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English (en)
Japanese (ja)
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JP2002117694A (ja
JP2002117694A5 (https=
Inventor
和英 米谷
勝 小柳
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000305402A priority Critical patent/JP4723714B2/ja
Priority to US09/971,371 priority patent/US6490219B2/en
Publication of JP2002117694A publication Critical patent/JP2002117694A/ja
Priority to US10/272,243 priority patent/US6665226B2/en
Publication of JP2002117694A5 publication Critical patent/JP2002117694A5/ja
Application granted granted Critical
Publication of JP4723714B2 publication Critical patent/JP4723714B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2000305402A 2000-10-04 2000-10-04 半導体集積回路装置およびその検査方法 Expired - Fee Related JP4723714B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000305402A JP4723714B2 (ja) 2000-10-04 2000-10-04 半導体集積回路装置およびその検査方法
US09/971,371 US6490219B2 (en) 2000-10-04 2001-10-03 Semiconductor integrated circuit device and method of manufacturing thereof
US10/272,243 US6665226B2 (en) 2000-10-04 2002-10-15 Semiconductor integrated circuit device and method of manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000305402A JP4723714B2 (ja) 2000-10-04 2000-10-04 半導体集積回路装置およびその検査方法

Publications (3)

Publication Number Publication Date
JP2002117694A JP2002117694A (ja) 2002-04-19
JP2002117694A5 JP2002117694A5 (https=) 2007-11-22
JP4723714B2 true JP4723714B2 (ja) 2011-07-13

Family

ID=18786272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000305402A Expired - Fee Related JP4723714B2 (ja) 2000-10-04 2000-10-04 半導体集積回路装置およびその検査方法

Country Status (2)

Country Link
US (2) US6490219B2 (https=)
JP (1) JP4723714B2 (https=)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328447B1 (ko) * 2000-02-21 2002-03-16 박종섭 안티퓨즈 리페어 회로
US6166981A (en) * 2000-02-25 2000-12-26 International Business Machines Corporation Method for addressing electrical fuses
JP3884374B2 (ja) * 2002-12-06 2007-02-21 株式会社東芝 半導体装置
DE10325769B4 (de) * 2003-06-05 2007-01-04 Zentrum Mikroelektronik Dresden Ag Anordnung und Verfahren zum Abgleich einer kalibrierbaren Stromquelle
US7089136B2 (en) * 2003-07-18 2006-08-08 International Business Machines Corporation Method for reduced electrical fusing time
JP3964841B2 (ja) * 2003-08-29 2007-08-22 株式会社東芝 半導体集積回路装置
JP2005092915A (ja) * 2003-09-12 2005-04-07 Toshiba Corp 半導体集積回路装置およびその情報記憶方法
US20060044899A1 (en) * 2004-08-27 2006-03-02 Ellis Robert W Method and apparatus for destroying flash memory
CN100481439C (zh) * 2004-10-27 2009-04-22 联咏科技股份有限公司 使用一次可程式化元件达到多次程式化的装置与方法
JP4828901B2 (ja) * 2005-09-22 2011-11-30 株式会社東芝 半導体集積回路装置
JP2007102848A (ja) * 2005-09-30 2007-04-19 Toshiba Corp 半導体集積回路装置
JP2007102865A (ja) * 2005-09-30 2007-04-19 Toshiba Corp 半導体集積回路装置
JP2008053259A (ja) * 2006-08-22 2008-03-06 Fujitsu Ltd 半導体集積回路及びその試験方法
JP5003106B2 (ja) * 2006-11-06 2012-08-15 セイコーエプソン株式会社 記憶回路の検査方法
JP2008305517A (ja) * 2007-06-11 2008-12-18 Hitachi Ulsi Systems Co Ltd 半導体集積回路装置
US7532027B2 (en) * 2007-09-28 2009-05-12 Adtron, Inc. Deliberate destruction of integrated circuits
KR101586325B1 (ko) * 2009-11-09 2016-02-03 삼성전자주식회사 트림 회로 및 이를 포함하는 반도체 메모리 장치
US9343184B2 (en) 2014-04-07 2016-05-17 Micron Technology, Inc. Soft post package repair of memory devices
US9741403B2 (en) * 2014-11-12 2017-08-22 Micron Technology, Inc. Apparatuses and methods to perform post package trim
US9349491B1 (en) 2015-04-17 2016-05-24 Micron Technology, Inc. Repair of memory devices using volatile and non-volatile memory
US10832791B2 (en) 2019-01-24 2020-11-10 Micron Technology, Inc. Apparatuses and methods for soft post-package repair
US10629282B1 (en) * 2019-06-16 2020-04-21 Elite Semiconductor Memory Technology Inc. E-fuse circuit
US11984185B2 (en) 2021-04-07 2024-05-14 Micron Technology, Inc. Apparatuses and methods for zone-based soft post-package repair

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2773271B2 (ja) * 1989-07-26 1998-07-09 日本電気株式会社 半導体記憶装置
JP2720718B2 (ja) * 1992-07-09 1998-03-04 株式会社デンソー 半導体センサ装置
US5682346A (en) * 1995-03-29 1997-10-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having suitable writing efficiency
JPH0935493A (ja) * 1995-07-15 1997-02-07 Toshiba Corp 半導体メモリ装置、マイクロコントローラ及び半導体メモリ装置の製造方法
US5677917A (en) * 1996-04-29 1997-10-14 Motorola, Inc. Integrated circuit memory using fusible links in a scan chain
JP2000163999A (ja) * 1998-11-20 2000-06-16 Fujitsu Ltd セルフタイミングコントロール回路
JP4437565B2 (ja) * 1998-11-26 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体集積回路装置、半導体集積回路装置の設計方法、及び、記録媒体
JP3526446B2 (ja) * 2000-06-09 2004-05-17 株式会社東芝 フューズプログラム回路
JP3814464B2 (ja) * 2000-06-09 2006-08-30 株式会社東芝 半導体メモリ集積回路
JP2002094368A (ja) * 2000-09-18 2002-03-29 Mitsubishi Electric Corp 半導体集積回路装置
JP2002150789A (ja) * 2000-11-09 2002-05-24 Hitachi Ltd 不揮発性半導体記憶装置
US6373771B1 (en) * 2001-01-17 2002-04-16 International Business Machines Corporation Integrated fuse latch and shift register for efficient programming and fuse readout

Also Published As

Publication number Publication date
US20030031075A1 (en) 2003-02-13
JP2002117694A (ja) 2002-04-19
US6665226B2 (en) 2003-12-16
US20020051400A1 (en) 2002-05-02
US6490219B2 (en) 2002-12-03

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