JP4662474B2 - データ処理デバイス - Google Patents

データ処理デバイス Download PDF

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Publication number
JP4662474B2
JP4662474B2 JP2006033513A JP2006033513A JP4662474B2 JP 4662474 B2 JP4662474 B2 JP 4662474B2 JP 2006033513 A JP2006033513 A JP 2006033513A JP 2006033513 A JP2006033513 A JP 2006033513A JP 4662474 B2 JP4662474 B2 JP 4662474B2
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JP
Japan
Prior art keywords
data strobe
strobe signal
signal circuit
inverted data
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2006033513A
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English (en)
Japanese (ja)
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JP2007213375A5 (https=
JP2007213375A (ja
Inventor
隆文 別井
直人 田岡
元大 諏訪
重純 松井
憲彦 杉田
義治 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2006033513A priority Critical patent/JP4662474B2/ja
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to US11/616,966 priority patent/US8091061B2/en
Publication of JP2007213375A publication Critical patent/JP2007213375A/ja
Publication of JP2007213375A5 publication Critical patent/JP2007213375A5/ja
Application granted granted Critical
Publication of JP4662474B2 publication Critical patent/JP4662474B2/ja
Priority to US13/310,217 priority patent/US8386992B2/en
Priority to US13/748,167 priority patent/US8694949B2/en
Priority to US14/182,821 priority patent/US8898613B2/en
Priority to US14/519,967 priority patent/US9530457B2/en
Priority to US15/351,580 priority patent/US9792959B2/en
Priority to US15/351,600 priority patent/US10020028B2/en
Priority to US16/010,770 priority patent/US10726878B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
JP2006033513A 2006-02-10 2006-02-10 データ処理デバイス Expired - Lifetime JP4662474B2 (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP2006033513A JP4662474B2 (ja) 2006-02-10 2006-02-10 データ処理デバイス
US11/616,966 US8091061B2 (en) 2006-02-10 2006-12-28 Microcomputer having memory interface circuits and memory devices on a module board
US13/310,217 US8386992B2 (en) 2006-02-10 2011-12-02 Data processing device
US13/748,167 US8694949B2 (en) 2006-02-10 2013-01-23 Data processing device
US14/182,821 US8898613B2 (en) 2006-02-10 2014-02-18 Data processing device
US14/519,967 US9530457B2 (en) 2006-02-10 2014-10-21 Data processing device
US15/351,580 US9792959B2 (en) 2006-02-10 2016-11-15 Data processing device
US15/351,600 US10020028B2 (en) 2006-02-10 2016-11-15 Data processing device
US16/010,770 US10726878B2 (en) 2006-02-10 2018-06-18 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006033513A JP4662474B2 (ja) 2006-02-10 2006-02-10 データ処理デバイス

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010271403A Division JP4979097B2 (ja) 2010-12-06 2010-12-06 マルチチップモジュール

Publications (3)

Publication Number Publication Date
JP2007213375A JP2007213375A (ja) 2007-08-23
JP2007213375A5 JP2007213375A5 (https=) 2010-03-04
JP4662474B2 true JP4662474B2 (ja) 2011-03-30

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JP2006033513A Expired - Lifetime JP4662474B2 (ja) 2006-02-10 2006-02-10 データ処理デバイス

Country Status (2)

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US (8) US8091061B2 (https=)
JP (1) JP4662474B2 (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4662474B2 (ja) * 2006-02-10 2011-03-30 ルネサスエレクトロニクス株式会社 データ処理デバイス
WO2008039526A2 (en) * 2006-09-25 2008-04-03 Flextronics Ap, Llc Bi-directional regulator
JP5288783B2 (ja) * 2007-12-12 2013-09-11 キヤノン株式会社 ボンディングパッド配置方法、半導体チップ及びシステム
JP5197080B2 (ja) * 2008-03-19 2013-05-15 ルネサスエレクトロニクス株式会社 半導体装置及びデータプロセッサ
US8031042B2 (en) 2008-05-28 2011-10-04 Flextronics Ap, Llc Power converter magnetic devices
US8586873B2 (en) * 2010-02-23 2013-11-19 Flextronics Ap, Llc Test point design for a high speed bus
CN104488135A (zh) * 2012-08-01 2015-04-01 申泰公司 多层传输线
KR102032887B1 (ko) * 2012-12-10 2019-10-16 삼성전자 주식회사 반도체 패키지 및 반도체 패키지의 라우팅 방법
CN104636229A (zh) * 2013-11-13 2015-05-20 华为技术有限公司 调整ddr线序的方法以及系统
JP2015099890A (ja) * 2013-11-20 2015-05-28 株式会社東芝 半導体装置、及び半導体パッケージ
JP2015111360A (ja) 2013-12-06 2015-06-18 ソニー株式会社 半導体モジュール
JP6300420B2 (ja) 2014-09-26 2018-03-28 ルネサスエレクトロニクス株式会社 電子装置
JP6317855B2 (ja) 2015-06-26 2018-04-25 ルネサスエレクトロニクス株式会社 電子装置
JP6543129B2 (ja) 2015-07-29 2019-07-10 ルネサスエレクトロニクス株式会社 電子装置
US10734314B2 (en) 2015-08-31 2020-08-04 Aisin Aw Co., Ltd. Semiconductor device and semiconductor module
JP6669547B2 (ja) * 2016-03-23 2020-03-18 京セラ株式会社 配線基板
KR102509048B1 (ko) 2016-04-26 2023-03-10 에스케이하이닉스 주식회사 반도체 패키지
WO2018063684A1 (en) * 2016-09-30 2018-04-05 Intel Corporation 3d high-inductive ground plane for crosstalk reduction
CN106375525A (zh) * 2016-11-30 2017-02-01 深圳天珑无线科技有限公司 一种抗扰电路
KR102371893B1 (ko) * 2017-05-18 2022-03-08 삼성전자주식회사 반도체 메모리 칩, 반도체 메모리 패키지, 및 이를 이용한 전자 시스템
US20190115293A1 (en) * 2018-12-12 2019-04-18 Intel Corporation Multiple ball grid array (bga) configurations for a single integrated circuit (ic) package
JP7279464B2 (ja) 2019-03-28 2023-05-23 株式会社アイシン 電子基板
WO2020248125A1 (zh) * 2019-06-11 2020-12-17 华为技术有限公司 电路板及电子设备
CN111182722B (zh) * 2020-02-26 2021-01-29 王致刚 一种模块化拼接的mcu应用电路板
KR102813418B1 (ko) * 2020-04-17 2025-05-27 에스케이하이닉스 주식회사 입출력 패드를 포함하는 메모리 장치
JP7424492B2 (ja) * 2020-07-02 2024-01-30 日本電信電話株式会社 配線構造
JP7507061B2 (ja) 2020-10-29 2024-06-27 ルネサスエレクトロニクス株式会社 電子装置および半導体装置
CN113191110B (zh) * 2021-05-07 2023-08-11 瓴盛科技有限公司 一种针对T型拓扑结构的DDR4地址控制线映射和Ball排列方法
JP7681233B2 (ja) * 2021-05-14 2025-05-22 京セラドキュメントソリューションズ株式会社 電子機器

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0597601A1 (en) * 1992-11-13 1994-05-18 National Semiconductor Corporation Reflexively sizing memory bus interface
US5867726A (en) * 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
JP3417808B2 (ja) * 1997-08-25 2003-06-16 富士通株式会社 Ｌｓｉパッケージの配線構造
JP3746161B2 (ja) * 1998-11-19 2006-02-15 富士通株式会社 半導体装置
JP3803204B2 (ja) * 1998-12-08 2006-08-02 寛治 大塚 電子装置
JP2000332369A (ja) * 1999-05-25 2000-11-30 Mitsui Mining & Smelting Co Ltd プリント回路板及びその製造方法
JP2001015704A (ja) * 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
JP2001094032A (ja) * 1999-09-21 2001-04-06 Matsushita Electronics Industry Corp 半導体装置
US6484290B1 (en) * 1999-11-03 2002-11-19 Feiya Technology Corp. IC package similar IDE interface solid state disk module and optimized pin design
JP2001217508A (ja) * 2000-01-31 2001-08-10 Toshiba Corp プリント基板
JP2002041452A (ja) * 2000-07-27 2002-02-08 Hitachi Ltd マイクロプロセッサ、半導体モジュール及びデータ処理システム
US6806733B1 (en) 2001-08-29 2004-10-19 Altera Corporation Multiple data rate interface architecture
CN100395715C (zh) * 2001-11-30 2008-06-18 富士通天株式会社 微型计算机的逻辑开发装置
US6972590B2 (en) * 2002-05-30 2005-12-06 Hewlett-Packard Development Company, L.P. Data bus with separate matched line impedances and method of matching line impedances
US6807650B2 (en) * 2002-06-03 2004-10-19 International Business Machines Corporation DDR-II driver impedance adjustment control algorithm and interface circuits
JP2004030438A (ja) * 2002-06-27 2004-01-29 Renesas Technology Corp マイクロコンピュータ
KR100546339B1 (ko) * 2003-07-04 2006-01-26 삼성전자주식회사 차동 데이터 스트로빙 모드와 데이터 반전 스킴을 가지는단일 데이터 스트로빙 모드를 선택적으로 구현할 수 있는반도체 장치
US20050050375A1 (en) 2003-08-29 2005-03-03 Mark Novak Memory interface system and method
JP3739375B2 (ja) * 2003-11-28 2006-01-25 沖電気工業株式会社 半導体装置及びその製造方法
JP4387403B2 (ja) * 2004-03-19 2009-12-16 株式会社ルネサステクノロジ 電子回路
JP4489485B2 (ja) * 2004-03-31 2010-06-23 株式会社ルネサステクノロジ 半導体装置
JP4647243B2 (ja) * 2004-05-24 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
DE602005026421D1 (de) * 2004-10-15 2011-03-31 Sony Computer Entertainment Inc Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem
US7380052B2 (en) * 2004-11-18 2008-05-27 International Business Machines Corporation Reuse of functional data buffers for pattern buffers in XDR DRAM
US20060149923A1 (en) * 2004-12-08 2006-07-06 Staktek Group L.P. Microprocessor optimized for algorithmic processing
US20060136658A1 (en) * 2004-12-16 2006-06-22 Simpletech, Inc. DDR2 SDRAM memory module
JP4662474B2 (ja) * 2006-02-10 2011-03-30 ルネサスエレクトロニクス株式会社 データ処理デバイス
JP2008299476A (ja) * 2007-05-30 2008-12-11 Fujitsu Microelectronics Ltd 半導体集積回路
WO2011016157A1 (ja) * 2009-08-07 2011-02-10 パナソニック株式会社 半導体装置および電子装置
US9412423B2 (en) * 2012-03-15 2016-08-09 Samsung Electronics Co., Ltd. Memory modules including plural memory devices arranged in rows and module resistor units
US9042188B2 (en) * 2013-04-01 2015-05-26 Arm Limited Memory controller and method of calibrating a memory controller

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US20180301172A1 (en) 2018-10-18
US20140160826A1 (en) 2014-06-12
US9530457B2 (en) 2016-12-27
US20120079238A1 (en) 2012-03-29
US8386992B2 (en) 2013-02-26
US10020028B2 (en) 2018-07-10
US8694949B2 (en) 2014-04-08
JP2007213375A (ja) 2007-08-23
US20070192559A1 (en) 2007-08-16
US20150036406A1 (en) 2015-02-05
US20170062021A1 (en) 2017-03-02
US20170062020A1 (en) 2017-03-02
US10726878B2 (en) 2020-07-28
US20130128647A1 (en) 2013-05-23
US8898613B2 (en) 2014-11-25
US9792959B2 (en) 2017-10-17
US8091061B2 (en) 2012-01-03

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