DE602005026421D1 - Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem - Google Patents

Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem

Info

Publication number
DE602005026421D1
DE602005026421D1 DE602005026421T DE602005026421T DE602005026421D1 DE 602005026421 D1 DE602005026421 D1 DE 602005026421D1 DE 602005026421 T DE602005026421 T DE 602005026421T DE 602005026421 T DE602005026421 T DE 602005026421T DE 602005026421 D1 DE602005026421 D1 DE 602005026421D1
Authority
DE
Germany
Prior art keywords
devices
multiprocessor system
supporting multiple
multiple configurations
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005026421T
Other languages
English (en)
Inventor
Takeshi Yamazaki
Scott Douglas Clark
Charles Ray Johns
James Allan Kahle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
International Business Machines Corp
Original Assignee
Sony Computer Entertainment Inc
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc, International Business Machines Corp filed Critical Sony Computer Entertainment Inc
Publication of DE602005026421D1 publication Critical patent/DE602005026421D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
DE602005026421T 2004-10-15 2005-10-14 Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem Active DE602005026421D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61906904P 2004-10-15 2004-10-15
PCT/JP2005/019347 WO2006041218A2 (en) 2004-10-15 2005-10-14 Methods and apparatus for supporting multiple configurations in a multi-processor system

Publications (1)

Publication Number Publication Date
DE602005026421D1 true DE602005026421D1 (de) 2011-03-31

Family

ID=36148726

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005026421T Active DE602005026421D1 (de) 2004-10-15 2005-10-14 Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem

Country Status (9)

Country Link
US (2) US7802023B2 (de)
EP (1) EP1805627B1 (de)
JP (1) JP4286826B2 (de)
KR (1) KR100875030B1 (de)
CN (1) CN101057223B (de)
AT (1) ATE498867T1 (de)
DE (1) DE602005026421D1 (de)
TW (1) TWI321414B (de)
WO (1) WO2006041218A2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7233998B2 (en) * 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
CA2559584A1 (en) 2004-03-13 2005-09-29 Cluster Resources, Inc. System and method of providing a self-optimizing reservation in space of compute resources
US8782654B2 (en) 2004-03-13 2014-07-15 Adaptive Computing Enterprises, Inc. Co-allocating a reservation spanning different compute resources types
US20070266388A1 (en) 2004-06-18 2007-11-15 Cluster Resources, Inc. System and method for providing advanced reservations in a compute environment
US8176490B1 (en) 2004-08-20 2012-05-08 Adaptive Computing Enterprises, Inc. System and method of interfacing a workload manager and scheduler with an identity manager
US8271980B2 (en) 2004-11-08 2012-09-18 Adaptive Computing Enterprises, Inc. System and method of providing system jobs within a compute environment
US7418541B2 (en) * 2005-02-10 2008-08-26 International Business Machines Corporation Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor
US7467204B2 (en) * 2005-02-10 2008-12-16 International Business Machines Corporation Method for providing low-level hardware access to in-band and out-of-band firmware
US7392350B2 (en) * 2005-02-10 2008-06-24 International Business Machines Corporation Method to operate cache-inhibited memory mapped commands to access registers
US8863143B2 (en) 2006-03-16 2014-10-14 Adaptive Computing Enterprises, Inc. System and method for managing a hybrid compute environment
US9231886B2 (en) 2005-03-16 2016-01-05 Adaptive Computing Enterprises, Inc. Simple integration of an on-demand compute environment
EP1872249B1 (de) 2005-04-07 2016-12-07 Adaptive Computing Enterprises, Inc. Zugang auf anfrage zu computerressourcen
JP2007148709A (ja) * 2005-11-28 2007-06-14 Hitachi Ltd プロセッサシステム
JP4662474B2 (ja) 2006-02-10 2011-03-30 ルネサスエレクトロニクス株式会社 データ処理デバイス
US7814279B2 (en) * 2006-03-23 2010-10-12 International Business Machines Corporation Low-cost cache coherency for accelerators
US8041773B2 (en) 2007-09-24 2011-10-18 The Research Foundation Of State University Of New York Automatic clustering for self-organizing grids
US7873066B2 (en) * 2009-01-26 2011-01-18 International Business Machines Corporation Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip
US8487655B1 (en) * 2009-05-05 2013-07-16 Cypress Semiconductor Corporation Combined analog architecture and functionality in a mixed-signal array
US8179161B1 (en) 2009-05-05 2012-05-15 Cypress Semiconductor Corporation Programmable input/output circuit
US9069929B2 (en) 2011-10-31 2015-06-30 Iii Holdings 2, Llc Arbitrating usage of serial port in node card of scalable and modular servers
US9465771B2 (en) 2009-09-24 2016-10-11 Iii Holdings 2, Llc Server on a chip and node cards comprising one or more of same
US9077654B2 (en) * 2009-10-30 2015-07-07 Iii Holdings 2, Llc System and method for data center security enhancements leveraging managed server SOCs
US9054990B2 (en) 2009-10-30 2015-06-09 Iii Holdings 2, Llc System and method for data center security enhancements leveraging server SOCs or server fabrics
US20130107444A1 (en) 2011-10-28 2013-05-02 Calxeda, Inc. System and method for flexible storage and networking provisioning in large scalable processor installations
US8599863B2 (en) 2009-10-30 2013-12-03 Calxeda, Inc. System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US20110103391A1 (en) 2009-10-30 2011-05-05 Smooth-Stone, Inc. C/O Barry Evans System and method for high-performance, low-power data center interconnect fabric
US9876735B2 (en) 2009-10-30 2018-01-23 Iii Holdings 2, Llc Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US9648102B1 (en) 2012-12-27 2017-05-09 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US11720290B2 (en) 2009-10-30 2023-08-08 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9680770B2 (en) 2009-10-30 2017-06-13 Iii Holdings 2, Llc System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US9311269B2 (en) 2009-10-30 2016-04-12 Iii Holdings 2, Llc Network proxy for high-performance, low-power data center interconnect fabric
US10877695B2 (en) 2009-10-30 2020-12-29 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US8625295B2 (en) 2011-01-24 2014-01-07 General Electric Company Fieldbus interface circuit board supporting multiple interface types and terminations
US20150058524A1 (en) * 2012-01-04 2015-02-26 Kenneth C. Creta Bimodal functionality between coherent link and memory expansion
CN105051707A (zh) 2013-04-01 2015-11-11 惠普发展公司，有限责任合伙企业 外部存储器控制器
US11126372B2 (en) 2013-04-01 2021-09-21 Hewlett Packard Enterprise Development Lp External memory controller
US9383932B2 (en) * 2013-12-27 2016-07-05 Intel Corporation Data coherency model and protocol at cluster level
US9727464B2 (en) 2014-11-20 2017-08-08 International Business Machines Corporation Nested cache coherency protocol in a tiered multi-node computer system
US9886382B2 (en) 2014-11-20 2018-02-06 International Business Machines Corporation Configuration based cache coherency protocol selection
US20180365070A1 (en) * 2017-06-16 2018-12-20 International Business Machines Corporation Dynamic throttling of broadcasts in a tiered multi-node symmetric multiprocessing computer system
CN107688471B (zh) * 2017-08-07 2021-06-08 北京中科睿芯科技集团有限公司 一种动态调整数据流架构的资源带宽的计算系统及其方法
NO344681B1 (en) * 2017-09-05 2020-03-02 Numascale As Coherent Node Controller
US20190042455A1 (en) * 2018-05-04 2019-02-07 Intel Corporation Globally addressable memory for devices linked to hosts
KR20200066774A (ko) 2018-12-03 2020-06-11 삼성전자주식회사 반도체 장치

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530932A (en) * 1994-12-23 1996-06-25 Intel Corporation Cache coherent multiprocessing computer system with reduced power operating features
US7933295B2 (en) * 1999-04-13 2011-04-26 Broadcom Corporation Cable modem with voice processing capability
US6487619B1 (en) * 1999-10-14 2002-11-26 Nec Corporation Multiprocessor system that communicates through an internal bus using a network protocol
US6574725B1 (en) * 1999-11-01 2003-06-03 Advanced Micro Devices, Inc. Method and mechanism for speculatively executing threads of instructions
US6526322B1 (en) * 1999-12-16 2003-02-25 Sirf Technology, Inc. Shared memory architecture in GPS signal processing
US6795896B1 (en) * 2000-09-29 2004-09-21 Intel Corporation Methods and apparatuses for reducing leakage power consumption in a processor
US6526491B2 (en) * 2001-03-22 2003-02-25 Sony Corporation Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US7233998B2 (en) * 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US7394823B2 (en) * 2001-11-20 2008-07-01 Broadcom Corporation System having configurable interfaces for flexible system configurations
US7093080B2 (en) * 2003-10-09 2006-08-15 International Business Machines Corporation Method and apparatus for coherent memory structure of heterogeneous processor systems
US7321958B2 (en) * 2003-10-30 2008-01-22 International Business Machines Corporation System and method for sharing memory by heterogeneous processors
US8108564B2 (en) * 2003-10-30 2012-01-31 International Business Machines Corporation System and method for a configurable interface controller
US7143246B2 (en) * 2004-01-16 2006-11-28 International Business Machines Corporation Method for supporting improved burst transfers on a coherent bus

Also Published As

Publication number Publication date
US7802023B2 (en) 2010-09-21
ATE498867T1 (de) 2011-03-15
TWI321414B (en) 2010-03-01
CN101057223A (zh) 2007-10-17
TW200631355A (en) 2006-09-01
WO2006041218A2 (en) 2006-04-20
EP1805627A2 (de) 2007-07-11
WO2006041218A3 (en) 2007-04-26
KR20070073825A (ko) 2007-07-10
CN101057223B (zh) 2011-09-14
JP2006120147A (ja) 2006-05-11
US8010716B2 (en) 2011-08-30
KR100875030B1 (ko) 2008-12-19
US20100312969A1 (en) 2010-12-09
EP1805627B1 (de) 2011-02-16
JP4286826B2 (ja) 2009-07-01
US20060092957A1 (en) 2006-05-04

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