ATE498867T1 - Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem - Google Patents

Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem

Info

Publication number
ATE498867T1
ATE498867T1 AT05795763T AT05795763T ATE498867T1 AT E498867 T1 ATE498867 T1 AT E498867T1 AT 05795763 T AT05795763 T AT 05795763T AT 05795763 T AT05795763 T AT 05795763T AT E498867 T1 ATE498867 T1 AT E498867T1
Authority
AT
Austria
Prior art keywords
devices
processor system
supporting multiple
multiple configurations
interface
Prior art date
Application number
AT05795763T
Other languages
English (en)
Inventor
Takeshi Yamazaki
Scott Clark
Charles Johns
James Kahle
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE498867T1 publication Critical patent/ATE498867T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
AT05795763T 2004-10-15 2005-10-14 Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem ATE498867T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61906904P 2004-10-15 2004-10-15
PCT/JP2005/019347 WO2006041218A2 (en) 2004-10-15 2005-10-14 Methods and apparatus for supporting multiple configurations in a multi-processor system

Publications (1)

Publication Number Publication Date
ATE498867T1 true ATE498867T1 (de) 2011-03-15

Family

ID=36148726

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05795763T ATE498867T1 (de) 2004-10-15 2005-10-14 Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem

Country Status (9)

Country Link
US (2) US7802023B2 (de)
EP (1) EP1805627B1 (de)
JP (1) JP4286826B2 (de)
KR (1) KR100875030B1 (de)
CN (1) CN101057223B (de)
AT (1) ATE498867T1 (de)
DE (1) DE602005026421D1 (de)
TW (1) TWI321414B (de)
WO (1) WO2006041218A2 (de)

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US7814279B2 (en) * 2006-03-23 2010-10-12 International Business Machines Corporation Low-cost cache coherency for accelerators
US8041773B2 (en) 2007-09-24 2011-10-18 The Research Foundation Of State University Of New York Automatic clustering for self-organizing grids
US7873066B2 (en) * 2009-01-26 2011-01-18 International Business Machines Corporation Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip
US8179161B1 (en) 2009-05-05 2012-05-15 Cypress Semiconductor Corporation Programmable input/output circuit
US8487655B1 (en) * 2009-05-05 2013-07-16 Cypress Semiconductor Corporation Combined analog architecture and functionality in a mixed-signal array
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US9054990B2 (en) 2009-10-30 2015-06-09 Iii Holdings 2, Llc System and method for data center security enhancements leveraging server SOCs or server fabrics
US9077654B2 (en) 2009-10-30 2015-07-07 Iii Holdings 2, Llc System and method for data center security enhancements leveraging managed server SOCs
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US11720290B2 (en) 2009-10-30 2023-08-08 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US10877695B2 (en) 2009-10-30 2020-12-29 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9648102B1 (en) 2012-12-27 2017-05-09 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9680770B2 (en) 2009-10-30 2017-06-13 Iii Holdings 2, Llc System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US8625295B2 (en) 2011-01-24 2014-01-07 General Electric Company Fieldbus interface circuit board supporting multiple interface types and terminations
US9092594B2 (en) 2011-10-31 2015-07-28 Iii Holdings 2, Llc Node card management in a modular and large scalable server system
EP2801032B1 (de) * 2012-01-04 2020-01-01 Intel Corporation Bimodale funktionalität zwischen kohärenten links und speichererweiterung
US11126372B2 (en) 2013-04-01 2021-09-21 Hewlett Packard Enterprise Development Lp External memory controller
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Also Published As

Publication number Publication date
EP1805627A2 (de) 2007-07-11
KR100875030B1 (ko) 2008-12-19
JP2006120147A (ja) 2006-05-11
TW200631355A (en) 2006-09-01
US7802023B2 (en) 2010-09-21
CN101057223B (zh) 2011-09-14
WO2006041218A2 (en) 2006-04-20
KR20070073825A (ko) 2007-07-10
JP4286826B2 (ja) 2009-07-01
US20100312969A1 (en) 2010-12-09
EP1805627B1 (de) 2011-02-16
TWI321414B (en) 2010-03-01
US8010716B2 (en) 2011-08-30
DE602005026421D1 (de) 2011-03-31
WO2006041218A3 (en) 2007-04-26
CN101057223A (zh) 2007-10-17
US20060092957A1 (en) 2006-05-04

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