JP4644173B2 - トランジスタの製造方法 - Google Patents
トランジスタの製造方法 Download PDFInfo
- Publication number
- JP4644173B2 JP4644173B2 JP2006247813A JP2006247813A JP4644173B2 JP 4644173 B2 JP4644173 B2 JP 4644173B2 JP 2006247813 A JP2006247813 A JP 2006247813A JP 2006247813 A JP2006247813 A JP 2006247813A JP 4644173 B2 JP4644173 B2 JP 4644173B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- semiconductor substrate
- sidewall spacer
- layer
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 112
- 125000006850 spacer group Chemical group 0.000 claims description 89
- 239000000463 material Substances 0.000 claims description 77
- 239000000758 substrate Substances 0.000 claims description 64
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 15
- 230000000873 masking effect Effects 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000004528 spin coating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 77
- 238000002955 isolation Methods 0.000 description 14
- 239000012212 insulator Substances 0.000 description 12
- 238000000926 separation method Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000007373 indentation Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- IJKVHSBPTUYDLN-UHFFFAOYSA-N dihydroxy(oxo)silane Chemical compound O[Si](O)=O IJKVHSBPTUYDLN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910017090 AlO 2 Inorganic materials 0.000 description 1
- 229910018516 Al—O Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 108091006149 Electron carriers Proteins 0.000 description 1
- 235000003976 Ruta Nutrition 0.000 description 1
- 240000005746 Ruta graveolens Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000007853 buffer solution Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- -1 connection plugs Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 235000005806 ruta Nutrition 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本発明は、概略的には、半導体装置に関するものであり、より詳細には、性能向上のためトランジスタにおける応力を調整する装置および方法に関するものである。
半導体装置は、コンピュータおよび携帯電話など、多くの電子機器において使用されている。装置を小型化および高速化し続けることが、半導体産業におけるひとつの目標である。各構成間の物理的距離が小さくなるため、装置が小さくなればなるほどその処理速度は速くなる。また、銅のような高導電率の物質は、アルミニウムのような低伝導率の物質に取り代わられつつある。さらに、半導体装置の処理速度を向上させるためのその他の試みとしては、電子や正孔などの半導体キャリアの移動度を向上させることが挙げられる。
上述のように、従来の技術において、溝はほとんどトランジスタのゲートをエッチングすることによって形成されている。これらの溝には、シリコンと異なる格子定数を有するエピタキシャルSiGeまたはその他の材料が充填される。異なる格子定数または熱膨張率が原因で物理的な応力が発生し、トランジスタチャネルに対して該応力が与えられる。その結果として、キャリアの移動度が向上するため、トランジスタの性能の向上に繋がる。
本発明に係る好ましい実施形態の構造および利用について以下に詳細な説明を行う。しかし、本発明が、多種多様の明確な記載を統合し得る、多くの適用可能な発明概念を提供することを理解されるであろう。以下において明確に記載する実施形態は、本発明を製造および利用するための特定の一例に過ぎず、本発明の適用範囲を限定するものではない。
Claims (18)
- チャネル領域に応力が印加されたMOSトランジスタの製造方法であって、
半導体基板を覆うように、該半導体基板から電気的に絶縁されたゲート電極を形成する工程;
該半導体基板を覆うように、該ゲート電極の側壁に沿って第1側壁スペーサを形成する工程;
該半導体基板を覆うように、該第1側壁スペーサと隣接する犠牲側壁スペーサを形成する工程;
該半導体基板を覆う平坦化層であって、該犠牲側壁スペーサと隣接する、該平坦化層を形成する工程;
該犠牲側壁スペーサを、該側壁スペーサおよび該平坦化層に対して選択的に除去する工程;
該犠牲側壁スペーサが除去されて露出した該半導体基板の領域をエッチングして、くぼみを形成する工程;
該くぼみに、該半導体基板の材料とは異なる格子定数を有する材料からなる半導体材料をエピタキシャル成長させることによって、該チャネル領域に応力を印加する工程;および
該半導体材料をエピタキシャル成長させた後に、該平坦化層を除去する工程;
を包含するMOSトランジスタの製造方法。 - 上記犠牲側壁スペーサを形成する上記工程が低温の酸化物材料を堆積させる工程を含む請求項1に記載のMOSトランジスタの製造方法。
- 上記平坦化層を形成する上記工程がドープされたシリコンガラス層を堆積させる工程を含む請求項1に記載のMOSトランジスタの製造方法。
- 上記犠牲側壁スペーサを除去する上記工程がウェットエッチングを行う工程を含む請求項1に記載のMOSトランジスタの製造方法。
- 上記平坦化層を形成する工程において、化学的−機械的研磨を行う工程によって該平坦化層が平坦化される請求項1に記載のMOSトランジスタの製造方法。
- 上記ゲート電極を形成する上記工程が、該ゲート電極を覆う硬質のマスクを形成する工程を含み、化学的−機械的研磨を行う上記工程が、該硬質のマスクの一部を除去する工程を含む請求項5に記載のMOSトランジスタの製造方法。
- 上記半導体基板がシリコンであり、かつ該半導体材料をエピタキシャル成長させることによって、上記チャネル領域に応力を印加する上記工程が上記くぼみをシリコンゲルマニウムで充填する工程を含む請求項1に記載のMOSトランジスタの製造方法。
- 上記くぼみをシリコンゲルマニウムで充填する上記工程が、ドープされたシリコンゲルマニウムを、該くぼみに選択的に成長させる工程を含む請求項7に記載のMOSトランジスタの製造方法。
- 上記半導体基板がシリコンであり、かつ該半導体材料をエピタキシャル成長させることによって、上記チャネル領域に応力を印加する上記工程が上記くぼみをシリコンカーボンで充填する工程を含む請求項1に記載のMOSトランジスタの製造方法。
- 上記平坦化層を除去する工程の後に、上記第1側壁スペーサと隣接する上記半導体基板にソース/ドレイン領域を形成する工程を、さらに含む請求項1に記載のMOSトランジスタの製造方法。
- 上記犠牲側壁スペーサを形成する上記工程の前に、上記第1側壁スペーサ、上記ゲート電極および上記半導体基板を覆うマスク層を形成する工程をさらに包含し、かつ該犠牲側壁スペーサを除去する上記工程が該マスク層および上記平坦化層を残して該犠牲側壁スペーサを選択的にエッチングする工程を含む請求項1に記載のMOSトランジスタの製造方法。
- チャネル領域に応力が印加されたMOSトランジスの製造方法であって、
半導体基板を覆うように、該半導体基板から電気的に絶縁されたゲート電極を形成する工程;
該半導体基板を覆うように、該ゲート電極の側壁に沿って第1側壁スペーサを形成する工程;
該ゲート電極および該第1側壁スペーサを含めて、該半導体基板を覆うようにマスキング層を形成する工程;
該半導体基板を覆っている該マスキング層を覆うように、第1側壁スペーサと隣接した犠牲側壁スペーサを形成する工程;
該半導体基板を覆っている該マスクキング層を覆う平坦化層であって、該平坦化層の一部が該犠牲側壁スペーサと隣接する、該平坦化層を形成する工程;
該犠牲側壁スペーサを、該マスキング層および該平坦化層に対して選択的に除去する工程;
該犠牲側壁スペーサが除去されて露出した該マスキング層および該露出したマスキング層の下部にある該半導体基板の領域をエッチングして、くぼみを形成する工程;
該くぼみを形成した後に、該平坦化層を除去する工程;および
該マスキング層を堆積マスクとして用いて、該半導体基板の材料とは異なる格子定数を有する材料からなる半導体材料を、該くぼみにエピタキシャル成長させることによって、該チャネル領域に応力を印加する工程
を包含するMOSトランジスタの製造方法。 - 上記平坦化層を形成する上記工程がレジスト層を形成する工程を含む請求項12に記載のMOSトランジスタの製造方法。
- 上記平坦化層を形成する上記工程が、さらに上記レジスト層をエッチバックする工程を含む請求項13に記載のMOSトランジスタの製造方法。
- 上記レジスト層を形成する工程が、該レジスト層をスピン塗布する工程を含む請求項14に記載のMOSトランジスタの製造方法。
- 上記マスキング層が、シリコン窒化物から構成されている請求項12に記載のMOSトランジスタの製造方法。
- 上記平坦化層を形成する上記工程が、酸素を含む材料の堆積および化学的−機械的研磨を行う工程を含む請求項12に記載のMOSトランジスタの製造方法。
- 上記半導体基板がシリコンから構成され、かつ上記半導体材料がSiGeまたはSiCから構成されている請求項12に記載のMOSトランジスタの製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/224,825 US8003470B2 (en) | 2005-09-13 | 2005-09-13 | Strained semiconductor device and method of making the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007110098A JP2007110098A (ja) | 2007-04-26 |
JP4644173B2 true JP4644173B2 (ja) | 2011-03-02 |
Family
ID=37487523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006247813A Expired - Fee Related JP4644173B2 (ja) | 2005-09-13 | 2006-09-13 | トランジスタの製造方法 |
Country Status (4)
Country | Link |
---|---|
US (4) | US8003470B2 (ja) |
EP (3) | EP1763073B1 (ja) |
JP (1) | JP4644173B2 (ja) |
CN (1) | CN1945854B (ja) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7553732B1 (en) * | 2005-06-13 | 2009-06-30 | Advanced Micro Devices, Inc. | Integration scheme for constrained SEG growth on poly during raised S/D processing |
US20060281271A1 (en) * | 2005-06-13 | 2006-12-14 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device having an epitaxial layer and device thereof |
US7572705B1 (en) | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
US7696019B2 (en) * | 2006-03-09 | 2010-04-13 | Infineon Technologies Ag | Semiconductor devices and methods of manufacturing thereof |
JP2007243105A (ja) * | 2006-03-13 | 2007-09-20 | Sony Corp | 半導体装置およびその製造方法 |
DE102006015075A1 (de) * | 2006-03-31 | 2007-10-11 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Bereitstellung von Verspannungsquellen in MOS-Transistoren in unmittelbarer Nähe zu einem Kanalgebiet |
US7763517B2 (en) * | 2007-02-12 | 2010-07-27 | Macronix International Co., Ltd. | Method of forming non-volatile memory cell |
JP5286701B2 (ja) | 2007-06-27 | 2013-09-11 | ソニー株式会社 | 半導体装置および半導体装置の製造方法 |
US9640666B2 (en) * | 2007-07-23 | 2017-05-02 | GlobalFoundries, Inc. | Integrated circuit employing variable thickness film |
US7652336B2 (en) | 2007-08-06 | 2010-01-26 | International Business Machines Corporation | Semiconductor devices and methods of manufacture thereof |
JP5389346B2 (ja) * | 2007-10-11 | 2014-01-15 | 富士通セミコンダクター株式会社 | Mos電界効果トランジスタおよびその製造方法 |
US7923365B2 (en) * | 2007-10-17 | 2011-04-12 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon |
JP5107680B2 (ja) * | 2007-11-16 | 2012-12-26 | パナソニック株式会社 | 半導体装置 |
US7786518B2 (en) * | 2007-12-27 | 2010-08-31 | Texas Instruments Incorporated | Growth of unfaceted SiGe in MOS transistor fabrication |
US8293631B2 (en) * | 2008-03-13 | 2012-10-23 | International Business Machines Corporation | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing |
US7892932B2 (en) * | 2008-03-25 | 2011-02-22 | International Business Machines Corporation | Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure |
US7772095B2 (en) * | 2008-05-28 | 2010-08-10 | International Business Machines Corporation | Integrated circuit having localized embedded SiGe and method of manufacturing |
KR101399099B1 (ko) * | 2008-06-02 | 2014-05-26 | 삼성전자주식회사 | 콘택 구조체를 포함하는 반도체 소자 및 그 형성 방법 |
KR101035614B1 (ko) * | 2008-10-23 | 2011-05-19 | 주식회사 동부하이텍 | 플래시 메모리 소자의 제조방법 |
US8106456B2 (en) * | 2009-07-29 | 2012-01-31 | International Business Machines Corporation | SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics |
JP5434360B2 (ja) * | 2009-08-20 | 2014-03-05 | ソニー株式会社 | 半導体装置及びその製造方法 |
US20110049582A1 (en) * | 2009-09-03 | 2011-03-03 | International Business Machines Corporation | Asymmetric source and drain stressor regions |
KR101674179B1 (ko) * | 2010-04-06 | 2016-11-10 | 삼성전자주식회사 | 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 형성 방법 |
CN102214574B (zh) * | 2010-04-07 | 2013-06-12 | 中国科学院微电子研究所 | 一种半导体器件的制造方法 |
CN102314927B (zh) * | 2010-07-06 | 2014-02-05 | 中国科学院物理研究所 | 一种磁性随机存储单元阵列、存储器及其读写方法 |
US8361859B2 (en) * | 2010-11-09 | 2013-01-29 | International Business Machines Corporation | Stressed transistor with improved metastability |
US8941182B2 (en) * | 2011-06-07 | 2015-01-27 | Globalfoundries Inc. | Buried sublevel metallizations for improved transistor density |
US8697557B2 (en) * | 2011-06-07 | 2014-04-15 | Globalfoundries Inc. | Method of removing gate cap materials while protecting active area |
US8921944B2 (en) * | 2011-07-19 | 2014-12-30 | United Microelectronics Corp. | Semiconductor device |
CN102903638B (zh) * | 2011-07-29 | 2016-03-30 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
FR2985089B1 (fr) * | 2011-12-27 | 2015-12-04 | Commissariat Energie Atomique | Transistor et procede de fabrication d'un transistor |
CN103367151B (zh) * | 2012-03-30 | 2015-12-16 | 中国科学院微电子研究所 | 使源/漏区更接近沟道区的mos器件及其制作方法 |
US8841190B2 (en) | 2012-03-30 | 2014-09-23 | The Institute of Microelectronics Chinese Academy of Science | MOS device for making the source/drain region closer to the channel region and method of manufacturing the same |
US8866230B2 (en) * | 2012-04-26 | 2014-10-21 | United Microelectronics Corp. | Semiconductor devices |
CN103632973B (zh) * | 2012-08-23 | 2017-01-25 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US9419126B2 (en) * | 2013-03-15 | 2016-08-16 | GlobalFoundries, Inc. | Integrated circuits and methods for fabricating integrated circuits with active area protection |
CN104103586B (zh) * | 2013-04-10 | 2017-03-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN104143512B (zh) * | 2013-05-09 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管的制作方法 |
CN104517822B (zh) * | 2013-09-27 | 2017-06-16 | 中芯国际集成电路制造(北京)有限公司 | 一种半导体器件的制造方法 |
US9379214B2 (en) * | 2014-02-14 | 2016-06-28 | Semi Solutions Llc | Reduced variation MOSFET using a drain-extension-last process |
US10123723B2 (en) | 2014-03-10 | 2018-11-13 | InnerSpace Neuro Solutions, Inc. | Air line protection coupling for a catheter |
US9941388B2 (en) * | 2014-06-19 | 2018-04-10 | Globalfoundries Inc. | Method and structure for protecting gates during epitaxial growth |
TWI555120B (zh) | 2014-10-14 | 2016-10-21 | 力晶科技股份有限公司 | 半導體元件及其製作方法 |
US10008582B2 (en) * | 2016-11-28 | 2018-06-26 | Globalfoundries Inc. | Spacers for tight gate pitches in field effect transistors |
CN109473429B (zh) * | 2018-10-26 | 2021-08-03 | 中国科学院微电子研究所 | 半导体器件及其制造方法及包括其的电子设备 |
US11289375B2 (en) | 2020-03-23 | 2022-03-29 | International Business Machines Corporation | Fully aligned interconnects with selective area deposition |
CN116799005B (zh) * | 2023-08-22 | 2023-11-28 | 合肥晶合集成电路股份有限公司 | 一种半导体结构及其制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03272182A (ja) * | 1990-03-22 | 1991-12-03 | Matsushita Electron Corp | 半導体装置の製造方法 |
JPH0479337A (ja) * | 1990-07-23 | 1992-03-12 | Oki Electric Ind Co Ltd | 半導体素子およびその製造方法 |
US6417056B1 (en) * | 2001-10-18 | 2002-07-09 | Chartered Semiconductor Manufacturing Ltd. | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge |
US20050184345A1 (en) * | 2003-07-25 | 2005-08-25 | Chun-Chieh Lin | Strained-channel semiconductor structure and method of fabricating the same |
US20050194699A1 (en) * | 2004-03-03 | 2005-09-08 | International Business Machines Corporation | Mobility enhanced cmos devices |
JP2006121074A (ja) * | 2004-10-20 | 2006-05-11 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2008504677A (ja) * | 2004-06-24 | 2008-02-14 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 改良した歪みシリコンcmosデバイスおよび方法 |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5364497A (en) * | 1993-08-04 | 1994-11-15 | Analog Devices, Inc. | Method for fabricating microstructures using temporary bridges |
US5679610A (en) * | 1994-12-15 | 1997-10-21 | Kabushiki Kaisha Toshiba | Method of planarizing a semiconductor workpiece surface |
DE19720008A1 (de) * | 1997-05-13 | 1998-11-19 | Siemens Ag | Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung |
US6214675B1 (en) * | 1999-02-08 | 2001-04-10 | Lucent Technologies Inc. | Method for fabricating a merged integrated circuit device |
US6136679A (en) * | 1999-03-05 | 2000-10-24 | Taiwan Semiconductor Manufacturing Company | Gate micro-patterning process |
US6294817B1 (en) * | 1999-12-13 | 2001-09-25 | Infineon Technologies Ag | Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication |
US6448180B2 (en) * | 2000-03-09 | 2002-09-10 | Advanced Micro Devices, Inc. | Deposition of in-situ doped semiconductor film and undoped semiconductor film in the same reaction chamber |
US6403482B1 (en) * | 2000-06-28 | 2002-06-11 | International Business Machines Corporation | Self-aligned junction isolation |
KR20020007848A (ko) * | 2000-07-19 | 2002-01-29 | 박종섭 | 반도체 소자 및 그의 제조 방법 |
JP3872639B2 (ja) | 2000-08-31 | 2007-01-24 | 株式会社村上開明堂 | 電動格納式ドアミラー |
US6495437B1 (en) * | 2001-02-09 | 2002-12-17 | Advanced Micro Devices, Inc. | Low temperature process to locally form high-k gate dielectrics |
US6489206B2 (en) * | 2001-03-22 | 2002-12-03 | United Microelectronics Corp. | Method for forming self-aligned local-halo metal-oxide-semiconductor device |
JP2004538650A (ja) * | 2001-08-10 | 2004-12-24 | スピネカ セミコンダクター, インコーポレイテッド | 基板とのショットキーコンタクトを形成する高誘電率ゲート絶縁層、ソースおよびドレインを有するトランジスタ |
US6621131B2 (en) * | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
US7226504B2 (en) | 2002-01-31 | 2007-06-05 | Sharp Laboratories Of America, Inc. | Method to form thick relaxed SiGe layer with trench structure |
US6583000B1 (en) | 2002-02-07 | 2003-06-24 | Sharp Laboratories Of America, Inc. | Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation |
AU2003238963A1 (en) * | 2002-06-07 | 2003-12-22 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US6812103B2 (en) * | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
US6787464B1 (en) * | 2002-07-02 | 2004-09-07 | Advanced Micro Devices, Inc. | Method of forming silicide layers over a plurality of semiconductor devices |
US7473947B2 (en) * | 2002-07-12 | 2009-01-06 | Intel Corporation | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby |
KR100437856B1 (ko) * | 2002-08-05 | 2004-06-30 | 삼성전자주식회사 | 모스 트랜지스터 및 이를 포함하는 반도체 장치의 형성방법. |
US7279367B1 (en) * | 2004-12-07 | 2007-10-09 | T-Ram Semiconductor, Inc. | Method of manufacturing a thyristor semiconductor device |
US6703648B1 (en) * | 2002-10-29 | 2004-03-09 | Advanced Micro Devices, Inc. | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication |
JP2004153173A (ja) * | 2002-10-31 | 2004-05-27 | Sharp Corp | 半導体装置の製造方法 |
US7090967B2 (en) * | 2002-12-30 | 2006-08-15 | Infineon Technologies Ag | Pattern transfer in device fabrication |
US6825086B2 (en) * | 2003-01-17 | 2004-11-30 | Sharp Laboratories Of America, Inc. | Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner |
US6921913B2 (en) * | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
JP4477886B2 (ja) * | 2003-04-28 | 2010-06-09 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7129539B2 (en) * | 2003-05-15 | 2006-10-31 | Sharp Kabushiki Kaisha | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card |
US20040262683A1 (en) * | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US6891192B2 (en) * | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US20050035369A1 (en) * | 2003-08-15 | 2005-02-17 | Chun-Chieh Lin | Structure and method of forming integrated circuits utilizing strained channel transistors |
DE10339989B4 (de) * | 2003-08-29 | 2008-04-17 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines konformen Abstandselements benachbart zu einer Gateelektrodenstruktur |
US7138320B2 (en) * | 2003-10-31 | 2006-11-21 | Advanced Micro Devices, Inc. | Advanced technique for forming a transistor having raised drain and source regions |
US8097924B2 (en) * | 2003-10-31 | 2012-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same |
KR100583105B1 (ko) * | 2003-12-24 | 2006-05-23 | 주식회사 하이닉스반도체 | 반도체 소자의 화학적 기계적 연마 공정의 종말점 검출 방법 |
US7023059B1 (en) * | 2004-03-01 | 2006-04-04 | Advanced Micro Devices, Inc. | Trenches to reduce lateral silicide growth in integrated circuit technology |
US7195963B2 (en) * | 2004-05-21 | 2007-03-27 | Freescale Semiconductor, Inc. | Method for making a semiconductor structure using silicon germanium |
US7172933B2 (en) * | 2004-06-10 | 2007-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessed polysilicon gate structure for a strained silicon MOSFET device |
US7361563B2 (en) * | 2004-06-17 | 2008-04-22 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device using a selective epitaxial growth technique |
US7413957B2 (en) * | 2004-06-24 | 2008-08-19 | Applied Materials, Inc. | Methods for forming a transistor |
US7135724B2 (en) * | 2004-09-29 | 2006-11-14 | International Business Machines Corporation | Structure and method for making strained channel field effect transistor using sacrificial spacer |
CN100463143C (zh) * | 2005-07-07 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | 具有氧化物间隔层的应变源漏cmos的集成方法 |
-
2005
- 2005-09-13 US US11/224,825 patent/US8003470B2/en not_active Expired - Fee Related
-
2006
- 2006-09-13 JP JP2006247813A patent/JP4644173B2/ja not_active Expired - Fee Related
- 2006-09-13 EP EP20060120572 patent/EP1763073B1/en not_active Expired - Fee Related
- 2006-09-13 CN CN200610143172XA patent/CN1945854B/zh not_active Expired - Fee Related
- 2006-09-13 EP EP14150531.3A patent/EP2720256B1/en not_active Not-in-force
- 2006-09-13 EP EP20100153752 patent/EP2180504B1/en not_active Expired - Fee Related
-
2011
- 2011-07-29 US US13/193,692 patent/US8624334B2/en active Active
-
2013
- 2013-11-22 US US14/087,918 patent/US8946034B2/en not_active Expired - Fee Related
-
2015
- 2015-01-13 US US14/595,977 patent/US9559204B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03272182A (ja) * | 1990-03-22 | 1991-12-03 | Matsushita Electron Corp | 半導体装置の製造方法 |
JPH0479337A (ja) * | 1990-07-23 | 1992-03-12 | Oki Electric Ind Co Ltd | 半導体素子およびその製造方法 |
US6417056B1 (en) * | 2001-10-18 | 2002-07-09 | Chartered Semiconductor Manufacturing Ltd. | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge |
US20050184345A1 (en) * | 2003-07-25 | 2005-08-25 | Chun-Chieh Lin | Strained-channel semiconductor structure and method of fabricating the same |
US20050194699A1 (en) * | 2004-03-03 | 2005-09-08 | International Business Machines Corporation | Mobility enhanced cmos devices |
JP2008504677A (ja) * | 2004-06-24 | 2008-02-14 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 改良した歪みシリコンcmosデバイスおよび方法 |
JP2006121074A (ja) * | 2004-10-20 | 2006-05-11 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20110278680A1 (en) | 2011-11-17 |
JP2007110098A (ja) | 2007-04-26 |
CN1945854B (zh) | 2012-01-11 |
US20150123201A1 (en) | 2015-05-07 |
EP1763073A3 (en) | 2009-08-26 |
US9559204B2 (en) | 2017-01-31 |
EP2180504A2 (en) | 2010-04-28 |
US20140077299A1 (en) | 2014-03-20 |
EP2720256A2 (en) | 2014-04-16 |
EP2180504A3 (en) | 2013-03-13 |
US8003470B2 (en) | 2011-08-23 |
EP2180504B1 (en) | 2015-03-25 |
EP1763073B1 (en) | 2013-06-19 |
EP2720256B1 (en) | 2016-05-25 |
US8946034B2 (en) | 2015-02-03 |
US8624334B2 (en) | 2014-01-07 |
EP1763073A2 (en) | 2007-03-14 |
CN1945854A (zh) | 2007-04-11 |
US20070057324A1 (en) | 2007-03-15 |
EP2720256A3 (en) | 2014-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4644173B2 (ja) | トランジスタの製造方法 | |
US9929269B2 (en) | FinFET having an oxide region in the source/drain region | |
KR101023208B1 (ko) | 인장 변형된 기판을 구비한 mosfet 디바이스와 그제조방법 | |
US7704808B2 (en) | Methods of forming semiconductor-on-insulating (SOI) field effect transistors with body contacts | |
US7928474B2 (en) | Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions | |
US7790548B2 (en) | Methods of fabricating field effect transistors including recessed forked gate structures | |
CN110299358B (zh) | 包括鳍型场效应晶体管的半导体器件及其制造方法 | |
US8835255B2 (en) | Method of forming a semiconductor structure including a vertical nanowire | |
US10199392B2 (en) | FinFET device having a partially dielectric isolated fin structure | |
US11682591B2 (en) | Method for forming transistor structures | |
US20230387246A1 (en) | Methods of forming gate structures with uniform gate length | |
KR20070068736A (ko) | 매몰절연막 상에 형성된 다중 채널을 갖는 모스트랜지스터를 구비하는 반도체 장치 제조 방법 | |
US20090085075A1 (en) | Method of fabricating mos transistor and mos transistor fabricated thereby | |
TWI485783B (zh) | 具有封裝的壓力源區域的半導體裝置及製作方法 | |
US10886406B1 (en) | Semiconductor structure and method of manufacturing the same | |
US20240113164A1 (en) | Film modification for gate cut process | |
TW202416360A (zh) | 半導體裝置及其形成方法 | |
CN116417518A (zh) | 半导体器件以及半导体器件的形成方法 | |
CN107968071A (zh) | 一种半导体器件及其制造方法和电子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100723 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100817 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101025 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101116 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101203 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4644173 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131210 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |