KR101023208B1 - 인장 변형된 기판을 구비한 mosfet 디바이스와 그제조방법 - Google Patents
인장 변형된 기판을 구비한 mosfet 디바이스와 그제조방법 Download PDFInfo
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Abstract
Description
반도체 제조는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)와 같은 반도체 디바이스의 성능을 개선하는 광범위한 기술을 이용한다. 도 1은 종래의 MOSFET 디바이스를 도시한다. 도 1의 MOSFET은 반도체 기판(10) 상에 활성 영역(active area)내에 형성되며, 상기 활성 영역은 얕은 트랜치 분리(12)(shallow trench isolation)에 의해 경계 지어지는바, 상기 얕은 트랜치 분리는 상기 MOSFET의 활성 영역을 상기 기판(10) 위에 제조된 다른 IC 소자들로부터 전기적으로 절연한다.
Claims (11)
- 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법으로서,기판(40)을 제공하는 단계, 여기서 상기 기판(40) 위에는 게이트(54)가 형성되며;스페이서 층을 증착하여 상기 기판(40) 위의 실리콘층(42) 위에 위치한 상기 게이트(54)와 게이트 절연체(56) 주위에 스페이서(60)를 형성하는 단계와;상기 스페이서(60), 상기 게이트(54), 및 상기 실리콘 층(42) 위에 식각 중지 층(63)을 증착하는 단계와; 그리고상기 식각 중지 층(63) 위에 유전체 층(65)을 증착하는 단계를 포함하며,상기 스페이서 층을 증착하는 단계, 식각 중지 층(63)을 증착하는 단계, 그리고 유전체 층(65)을 증착하는 단계 중 적어도 하나의 단계는 고 압축성 증착을 포함하여 상기 실리콘 층(42)의 인장 변형을 증대시키는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제 1항에 있어서,상기 스페이서 층을 증착하는 단계, 식각 중지 층(63)을 증착하는 단계, 및 유전체 층(65)을 증착하는 단계 모두는, 고 압축성 증착 기술을 포함하는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제 2항에 있어서,상기 고 압축성 기술은 높은 이온 충격을 포함하는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제1항에 있어서,상기 스페이서(60)를 형성한 이후에, 높은 이온 충격을 위해 바이어스된 RF 전력을 사용하여 라이너를 증착하는 단계를 더 포함하는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제1항에 있어서,상기 실리콘층(42)은 적어도 200nm의 두께를 구비한 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제1항에 있어서,상기 게이트(54)와 상기 스페이서들(60) 사이에 라이너가 포함되는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제1항에 있어서,상기 식각 중지 층(63)과 유전체 층(65)은 플라즈마 화학 기상 증착(PECVD)을 사용하여 증착되는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제 7항에 있어서,상기 PECVD는 높은 이온 충격을 위하여 바이어스된 RF 전력을 포함하는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제1항에 있어서,상기 식각 중지 층(63)은 실리콘 나이트라이드를 포함하는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제1항에 있어서,상기 기판(40)은 실리콘-게르마늄층을 포함하는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
- 제1항에 있어서,상기 스페이서(60)를 형성한 이후에, 상기 게이트(54)의 양측의 상기 실리콘층(42)에 소스 및 드레인 영역들을 형성하는 단계를 더 포함하며,상기 소스 및 드레인 영역들의 깊이는 상기 실리콘층(42)의 깊이 이상으로 확장되지 않는 것을 특징으로 하는 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET)의 형성 방법.
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US10/346,617 | 2003-01-17 | ||
US10/346,617 US7001837B2 (en) | 2003-01-17 | 2003-01-17 | Semiconductor with tensile strained substrate and method of making the same |
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Also Published As
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US20040142545A1 (en) | 2004-07-22 |
KR20050086961A (ko) | 2005-08-30 |
DE112004000146T5 (de) | 2006-02-02 |
US7001837B2 (en) | 2006-02-21 |
JP2006517343A (ja) | 2006-07-20 |
GB0512330D0 (en) | 2005-07-27 |
US7701019B2 (en) | 2010-04-20 |
DE112004000146B4 (de) | 2010-05-06 |
GB2411768A (en) | 2005-09-07 |
CN1762056B (zh) | 2011-06-01 |
CN1762056A (zh) | 2006-04-19 |
US20060138479A1 (en) | 2006-06-29 |
WO2004068586A1 (en) | 2004-08-12 |
GB2411768B (en) | 2006-04-26 |
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