JP2006517343A - 引張歪み基板を有するmosfetデバイスおよびその作製方法 - Google Patents
引張歪み基板を有するmosfetデバイスおよびその作製方法 Download PDFInfo
- Publication number
- JP2006517343A JP2006517343A JP2006502832A JP2006502832A JP2006517343A JP 2006517343 A JP2006517343 A JP 2006517343A JP 2006502832 A JP2006502832 A JP 2006502832A JP 2006502832 A JP2006502832 A JP 2006502832A JP 2006517343 A JP2006517343 A JP 2006517343A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- silicon
- deposition
- spacer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 77
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 75
- 239000010703 silicon Substances 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 42
- 238000000151 deposition Methods 0.000 claims abstract description 41
- 125000006850 spacer group Chemical group 0.000 claims abstract description 35
- 230000008021 deposition Effects 0.000 claims abstract description 26
- 230000006835 compression Effects 0.000 claims abstract description 24
- 238000007906 compression Methods 0.000 claims abstract description 24
- 239000012212 insulator Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000005669 field effect Effects 0.000 claims abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 5
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 238000010849 ion bombardment Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 101
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 30
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 24
- 230000008569 process Effects 0.000 description 15
- 239000000463 material Substances 0.000 description 12
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- -1 SiO 2 ) Chemical compound 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001803 electron scattering Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (10)
- 金属酸化膜半導体電界効果トランジスタ(MOSFET)を形成するための方法であって、
上部にゲート(54)が形成されている基板(40)を提供するステップと、
前記基板(40)の上部のシリコンの層(42)の上部に位置するゲート(54)およびゲート絶縁物(56)の周りにスペーサ層を堆積させ、スペーサ(60)を形成するステップ、
前記スペーサ(60)、前記ゲート(54)、および前記シリコンの層(42)の上部にエッチ・ストップ層(63)を堆積するステップ、
前記エッチ・ストップ層(63)の上部に絶縁膜(65)を堆積するステップのうちの少なくとも1つの堆積するステップを実行するステップとを有し、
前記スペーサ層の堆積、エッチ・ストップ層(63)の堆積、および絶縁膜(65)の堆積の少なくとも1つは、高圧縮堆積を含んでおり、これによって前記シリコンの層(42)内の引張歪みを増大させる方法。 - スペーサ層の堆積、エッチ・ストップ層(63)の堆積、および絶縁膜(65)の堆積のすべては高圧縮技術を含む請求項1に記載の方法。
- 前記高圧縮技術は高イオン衝突を伴う請求項2に記載の方法。
- 高イオン衝突を得るためバイアスRF電力を使用してライナを堆積するステップをさらに有する請求項1に記載の方法。
- 前記シリコンの層の厚さは少なくとも200nmである請求項1に記載の方法。
- トランジスタの処理方法であって、
シリコン層(42)の上部にゲート(54)を設けるステップであって、前記ゲート(54)は、前記ゲート(54)の近傍の横方向の側壁にスペーサ(60)を有するステップと、
前記ゲート(54)およびスペーサ(60)の上部に、前記シリコン層(42)内に歪みを生じさせる高圧縮堆積でエッチ・ストップ層(63)を形成するステップと、
前記エッチ・ストップ層(63)の上部に、前記シリコン層(42)に歪みを生じさせる高圧縮堆積で絶縁膜(65)を形成するステップと、を有する方法。 - 前記ゲート(54)と前記スペーサ(60)との間にライナが設けられている請求項6に記載の方法。
- 前記エッチ・ストップ層(63)および絶縁膜(65)はプラズマ化学気相成長法(PECVD)を使用して堆積される請求項6に記載の方法。
- 前記PECVDはより高いイオン衝突を得るためバイアスRF電力を伴う請求項8に記載の方法。
- 前記エッチ・ストップ層(63)は窒化シリコンを含む請求項6に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/346,617 US7001837B2 (en) | 2003-01-17 | 2003-01-17 | Semiconductor with tensile strained substrate and method of making the same |
PCT/US2004/000981 WO2004068586A1 (en) | 2003-01-17 | 2004-01-13 | Mosfet device with tensile strained substrate and method of making the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006517343A true JP2006517343A (ja) | 2006-07-20 |
JP2006517343A5 JP2006517343A5 (ja) | 2009-01-15 |
Family
ID=32712194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006502832A Pending JP2006517343A (ja) | 2003-01-17 | 2004-01-13 | 引張歪み基板を有するmosfetデバイスおよびその作製方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US7001837B2 (ja) |
JP (1) | JP2006517343A (ja) |
KR (1) | KR101023208B1 (ja) |
CN (1) | CN1762056B (ja) |
DE (1) | DE112004000146B4 (ja) |
GB (1) | GB2411768B (ja) |
WO (1) | WO2004068586A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008504677A (ja) * | 2004-06-24 | 2008-02-14 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 改良した歪みシリコンcmosデバイスおよび方法 |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6830976B2 (en) | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US7301180B2 (en) | 2001-06-18 | 2007-11-27 | Massachusetts Institute Of Technology | Structure and method for a high-speed semiconductor device having a Ge channel layer |
WO2003001671A2 (en) * | 2001-06-21 | 2003-01-03 | Amberwave Systems Corporation | Improved enhancement of p-type metal-oxide-semiconductor field-effect transistors |
EP1415331A2 (en) * | 2001-08-06 | 2004-05-06 | Massachusetts Institute Of Technology | Formation of planar strained layers |
US6974735B2 (en) | 2001-08-09 | 2005-12-13 | Amberwave Systems Corporation | Dual layer Semiconductor Devices |
US7138649B2 (en) * | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
AU2002331077A1 (en) * | 2001-08-13 | 2003-03-03 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
AU2002349881A1 (en) | 2001-09-21 | 2003-04-01 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
WO2003028106A2 (en) * | 2001-09-24 | 2003-04-03 | Amberwave Systems Corporation | Rf circuits including transistors having strained material layers |
US6657276B1 (en) * | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
AU2003238963A1 (en) * | 2002-06-07 | 2003-12-22 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
AU2003247513A1 (en) | 2002-06-10 | 2003-12-22 | Amberwave Systems Corporation | Growing source and drain elements by selecive epitaxy |
US6982474B2 (en) | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
US7091068B1 (en) * | 2002-12-06 | 2006-08-15 | Advanced Micro Devices, Inc. | Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices |
US20040154083A1 (en) * | 2002-12-23 | 2004-08-12 | Mcvicker Henry J. | Sports pad closure system with integrally molded hooks |
EP1602125B1 (en) * | 2003-03-07 | 2019-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow trench isolation process |
US7303949B2 (en) * | 2003-10-20 | 2007-12-04 | International Business Machines Corporation | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture |
US7462526B2 (en) * | 2003-11-18 | 2008-12-09 | Silicon Genesis Corporation | Method for fabricating semiconductor devices using strained silicon bearing material |
US7053400B2 (en) * | 2004-05-05 | 2006-05-30 | Advanced Micro Devices, Inc. | Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility |
US7321155B2 (en) * | 2004-05-06 | 2008-01-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Offset spacer formation for strained channel CMOS transistor |
DE102004042167B4 (de) * | 2004-08-31 | 2009-04-02 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur, die Transistorelemente mit unterschiedlich verspannten Kanalgebieten umfasst, und entsprechende Halbleiterstruktur |
US20060099763A1 (en) * | 2004-10-28 | 2006-05-11 | Yi-Cheng Liu | Method of manufacturing semiconductor mos transistor device |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US20060172556A1 (en) * | 2005-02-01 | 2006-08-03 | Texas Instruments Incorporated | Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor |
WO2006085245A1 (en) * | 2005-02-11 | 2006-08-17 | Nxp B.V. | Method of forming sti regions in electronic devices |
CN100446282C (zh) * | 2005-09-19 | 2008-12-24 | 深圳帝光电子有限公司 | Led光源产品 |
US7615432B2 (en) * | 2005-11-02 | 2009-11-10 | Samsung Electronics Co., Ltd. | HDP/PECVD methods of fabricating stress nitride structures for field effect transistors |
US7550356B2 (en) * | 2005-11-14 | 2009-06-23 | United Microelectronics Corp. | Method of fabricating strained-silicon transistors |
US7939413B2 (en) * | 2005-12-08 | 2011-05-10 | Samsung Electronics Co., Ltd. | Embedded stressor structure and process |
US7888214B2 (en) * | 2005-12-13 | 2011-02-15 | Globalfoundries Singapore Pte. Ltd. | Selective stress relaxation of contact etch stop layer through layout design |
US20070158739A1 (en) * | 2006-01-06 | 2007-07-12 | International Business Machines Corporation | Higher performance CMOS on (110) wafers |
US20080124880A1 (en) * | 2006-09-23 | 2008-05-29 | Chartered Semiconductor Manufacturing Ltd. | Fet structure using disposable spacer and stress inducing layer |
US7897493B2 (en) * | 2006-12-08 | 2011-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inducement of strain in a semiconductor layer |
US7892928B2 (en) * | 2007-03-23 | 2011-02-22 | International Business Machines Corporation | Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers |
US7745847B2 (en) * | 2007-08-09 | 2010-06-29 | United Microelectronics Corp. | Metal oxide semiconductor transistor |
US8058123B2 (en) | 2007-11-29 | 2011-11-15 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit and method of fabrication thereof |
US20090146194A1 (en) * | 2007-12-05 | 2009-06-11 | Ecole Polytechnique Federale De Lausanne (Epfl) | Semiconductor device and method of manufacturing a semiconductor device |
US8232186B2 (en) * | 2008-05-29 | 2012-07-31 | International Business Machines Corporation | Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure |
JP5381350B2 (ja) * | 2009-06-03 | 2014-01-08 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8236709B2 (en) | 2009-07-29 | 2012-08-07 | International Business Machines Corporation | Method of fabricating a device using low temperature anneal processes, a device and design structure |
TWI419324B (zh) * | 2009-11-27 | 2013-12-11 | Univ Nat Chiao Tung | 具有三五族通道及四族源汲極之半導體裝置及其製造方法 |
US8865576B2 (en) * | 2011-09-29 | 2014-10-21 | Eastman Kodak Company | Producing vertical transistor having reduced parasitic capacitance |
US8759920B2 (en) * | 2012-06-01 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03247767A (ja) * | 1990-02-26 | 1991-11-05 | Fuji Electric Co Ltd | 絶縁膜形成方法 |
JPH0562971A (ja) * | 1991-09-02 | 1993-03-12 | Fuji Electric Co Ltd | 窒化シリコン膜の形成方法 |
JPH05315268A (ja) * | 1992-05-13 | 1993-11-26 | Matsushita Electric Ind Co Ltd | プラズマcvd装置 |
JPH1079387A (ja) * | 1996-08-02 | 1998-03-24 | Applied Materials Inc | シリカ膜のフッ素化による応力制御 |
JPH11288932A (ja) * | 1997-12-31 | 1999-10-19 | Texas Instr Inc <Ti> | 高品質窒化珪素の高速蒸着 |
JPH11340337A (ja) * | 1998-05-27 | 1999-12-10 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JP2000031491A (ja) * | 1998-07-14 | 2000-01-28 | Hitachi Ltd | 半導体装置,半導体装置の製造方法,半導体基板および半導体基板の製造方法 |
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
WO2002047167A1 (fr) * | 2000-12-08 | 2002-06-13 | Hitachi, Ltd. | Dispositif a semi-conducteur |
JP2002176174A (ja) * | 2000-12-08 | 2002-06-21 | Hitachi Ltd | 半導体装置 |
JP2002198368A (ja) * | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US607178A (en) * | 1898-07-12 | Combined plow and harrow | ||
US628113A (en) * | 1898-07-30 | 1899-07-04 | Carl Petersen | Apparatus for indicating the number of conversations through telephones. |
US649221A (en) * | 1899-12-16 | 1900-05-08 | Charles Slingland | Warping-machine. |
US5241214A (en) * | 1991-04-29 | 1993-08-31 | Massachusetts Institute Of Technology | Oxides and nitrides of metastabale group iv alloys and nitrides of group iv elements and semiconductor devices formed thereof |
US5461250A (en) * | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US6288431B1 (en) * | 1997-04-04 | 2001-09-11 | Nippon Steel Corporation | Semiconductor device and a method of manufacturing the same |
US5843816A (en) * | 1997-07-28 | 1998-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell |
US6071784A (en) * | 1997-08-29 | 2000-06-06 | Advanced Micro Devices, Inc. | Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss |
US6215190B1 (en) * | 1998-05-12 | 2001-04-10 | International Business Machines Corporation | Borderless contact to diffusion with respect to gate conductor and methods for fabricating |
US6281132B1 (en) * | 1998-10-06 | 2001-08-28 | Advanced Micro Devices, Inc. | Device and method for etching nitride spacers formed upon an integrated circuit gate conductor |
US6448140B1 (en) * | 1999-02-08 | 2002-09-10 | Taiwan Semiconductor Manufacturing Company | Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess |
US6177338B1 (en) * | 1999-02-08 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Two step barrier process |
US6136688A (en) * | 1999-10-20 | 2000-10-24 | Vanguard International Semiconductor Corporation | High stress oxide to eliminate BPSG/SiN cracking |
US6426285B1 (en) * | 1999-11-03 | 2002-07-30 | Taiwan Semiconductor Manufacturing Company | Method to solve intermetallic dielectric cracks in integrated circuit devices |
US6211083B1 (en) * | 2000-04-17 | 2001-04-03 | Taiwan Semiconductor Manufacturing Company | Use of a novel capped anneal procedure to improve salicide formation |
US6399512B1 (en) * | 2000-06-15 | 2002-06-04 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer |
US6503833B1 (en) * | 2000-11-15 | 2003-01-07 | International Business Machines Corporation | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby |
US6544854B1 (en) * | 2000-11-28 | 2003-04-08 | Lsi Logic Corporation | Silicon germanium CMOS channel |
US6287916B1 (en) * | 2000-12-07 | 2001-09-11 | Lattice Semiconductor Corporation | Method for forming a semiconductor device using LPCVD nitride to protect floating gate from charge loss |
US6724008B2 (en) * | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6432784B1 (en) * | 2001-03-12 | 2002-08-13 | Advanced Micro Devices, Inc. | Method of forming L-shaped nitride spacers |
US6620664B2 (en) * | 2002-02-07 | 2003-09-16 | Sharp Laboratories Of America, Inc. | Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same |
US6492216B1 (en) * | 2002-02-07 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Method of forming a transistor with a strained channel |
US6680496B1 (en) * | 2002-07-08 | 2004-01-20 | Amberwave Systems Corp. | Back-biasing to populate strained layer quantum wells |
US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
US6902991B2 (en) * | 2002-10-24 | 2005-06-07 | Advanced Micro Devices, Inc. | Semiconductor device having a thick strained silicon layer and method of its formation |
US6657223B1 (en) * | 2002-10-29 | 2003-12-02 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
US6611029B1 (en) * | 2002-11-08 | 2003-08-26 | Advanced Micro Devices, Inc. | Double gate semiconductor device having separate gates |
US6787423B1 (en) * | 2002-12-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Strained-silicon semiconductor device |
US7371629B2 (en) * | 2002-12-09 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company | N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications |
US6825529B2 (en) * | 2002-12-12 | 2004-11-30 | International Business Machines Corporation | Stress inducing spacers |
US6730576B1 (en) * | 2002-12-31 | 2004-05-04 | Advanced Micro Devices, Inc. | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer |
-
2003
- 2003-01-17 US US10/346,617 patent/US7001837B2/en not_active Expired - Lifetime
-
2004
- 2004-01-13 CN CN2004800074546A patent/CN1762056B/zh not_active Expired - Lifetime
- 2004-01-13 KR KR1020057013068A patent/KR101023208B1/ko active IP Right Grant
- 2004-01-13 DE DE112004000146T patent/DE112004000146B4/de not_active Expired - Lifetime
- 2004-01-13 WO PCT/US2004/000981 patent/WO2004068586A1/en active Search and Examination
- 2004-01-13 GB GB0512330A patent/GB2411768B/en not_active Expired - Lifetime
- 2004-01-13 JP JP2006502832A patent/JP2006517343A/ja active Pending
-
2006
- 2006-02-17 US US11/356,606 patent/US7701019B2/en not_active Expired - Lifetime
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03247767A (ja) * | 1990-02-26 | 1991-11-05 | Fuji Electric Co Ltd | 絶縁膜形成方法 |
JPH0562971A (ja) * | 1991-09-02 | 1993-03-12 | Fuji Electric Co Ltd | 窒化シリコン膜の形成方法 |
JPH05315268A (ja) * | 1992-05-13 | 1993-11-26 | Matsushita Electric Ind Co Ltd | プラズマcvd装置 |
JPH1079387A (ja) * | 1996-08-02 | 1998-03-24 | Applied Materials Inc | シリカ膜のフッ素化による応力制御 |
JPH11288932A (ja) * | 1997-12-31 | 1999-10-19 | Texas Instr Inc <Ti> | 高品質窒化珪素の高速蒸着 |
JPH11340337A (ja) * | 1998-05-27 | 1999-12-10 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JP2000031491A (ja) * | 1998-07-14 | 2000-01-28 | Hitachi Ltd | 半導体装置,半導体装置の製造方法,半導体基板および半導体基板の製造方法 |
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
WO2002047167A1 (fr) * | 2000-12-08 | 2002-06-13 | Hitachi, Ltd. | Dispositif a semi-conducteur |
JP2002176174A (ja) * | 2000-12-08 | 2002-06-21 | Hitachi Ltd | 半導体装置 |
JP2002198368A (ja) * | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
Non-Patent Citations (2)
Title |
---|
MASAHIKO MAEDA ET AL.: "Stress evaluation of radio frequency-biased plasma-enhanced chemical vapor deposited silicon nitride", JOUNAL OF APPLIED PHYSICS, vol. Volume 83, Number 7, JPN7011002552, 1 April 1998 (1998-04-01), pages 3865 - 3870, ISSN: 0001969479 * |
前田和夫著, VLSIとCVD 半導体デバイスへのCVD技術の応用, vol. 初版, JPN6011036682, 31 July 1997 (1997-07-31), pages 100 - 188, ISSN: 0001969478 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008504677A (ja) * | 2004-06-24 | 2008-02-14 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 改良した歪みシリコンcmosデバイスおよび方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2004068586A1 (en) | 2004-08-12 |
KR20050086961A (ko) | 2005-08-30 |
US20040142545A1 (en) | 2004-07-22 |
US20060138479A1 (en) | 2006-06-29 |
DE112004000146B4 (de) | 2010-05-06 |
US7701019B2 (en) | 2010-04-20 |
DE112004000146T5 (de) | 2006-02-02 |
GB2411768B (en) | 2006-04-26 |
US7001837B2 (en) | 2006-02-21 |
CN1762056A (zh) | 2006-04-19 |
KR101023208B1 (ko) | 2011-03-18 |
GB0512330D0 (en) | 2005-07-27 |
GB2411768A (en) | 2005-09-07 |
CN1762056B (zh) | 2011-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7701019B2 (en) | Tensile strained substrate | |
US6852600B1 (en) | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication | |
JP4843498B2 (ja) | 半導体デバイス構造を製造する方法 | |
US9735269B1 (en) | Integrated strained stacked nanosheet FET | |
US7071065B1 (en) | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication | |
US8003470B2 (en) | Strained semiconductor device and method of making the same | |
US6800910B2 (en) | FinFET device incorporating strained silicon in the channel region | |
US7422950B2 (en) | Strained silicon MOS device with box layer between the source and drain regions | |
US20230335640A1 (en) | Semiconductor structure and associated fabricating method | |
KR100817949B1 (ko) | 반도체 디바이스, 반도체 디바이스 제조 방법 및 비평면 트랜지스터 제조 방법 | |
US7928474B2 (en) | Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions | |
US6943087B1 (en) | Semiconductor on insulator MOSFET having strained silicon channel | |
US7033869B1 (en) | Strained silicon semiconductor on insulator MOSFET | |
US7714396B2 (en) | Metal-oxide semiconductor field effect transistor | |
US8748239B2 (en) | Method of fabricating a gate | |
US7015078B1 (en) | Silicon on insulator substrate having improved thermal conductivity and method of its formation | |
US6900143B1 (en) | Strained silicon MOSFETs having improved thermal dissipation | |
US8440532B2 (en) | Structure and method for making metal semiconductor field effect transistor (MOSFET) with isolation last process | |
CN107919393B (zh) | 一种半导体器件及其制造方法 | |
JP5280434B2 (ja) | 半導体デバイスにおける分離層の形成 | |
TW200847291A (en) | Metal-oxide-semiconductor transistor and method of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A529 | Written submission of copy of amendment under article 34 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A529 Effective date: 20050914 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070110 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081119 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100226 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100413 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100421 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100709 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100716 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100810 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100817 |
|
RD05 | Notification of revocation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7425 Effective date: 20100902 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100913 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20110720 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111121 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120110 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20120406 |