CN1762056A - 具有拉伸应变基片的mosfet器件及其制备方法 - Google Patents
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Abstract
一个示例性实施例涉及一种形成金属氧化物半导体场效应晶体管(MOSFET)的方法。该方法包括提供其上形成有栅极(54)的基片(40)并且至少进行以下沉积步骤中的一种：沉积隔片层并在位于基片(40)上的硅层(42)之上的栅极(54)与栅极绝缘体(56)周围形成隔片(60)；在隔片(60)、栅极(54)与硅层(42)上沉积蚀刻终止层(63)；以及在蚀刻终止层(63)上沉积介电层(65)。沉积隔片、沉积蚀刻终止层(63)与沉积介电层(65)中的至少一个包括高压缩沉积，该高压缩沉积增大了硅层(42)中的拉伸应变。
Description
技术领域
本发明一般涉及集成电路与制备集成电路的方法。更具体地，本发明涉及具有拉伸应变基片(tensile strained substrate)的半导体与制备这种半导体的方法。
背景技术
半导体制备商使用极其多样的技术来改善诸如金属氧化物半导体场效应晶体管(MOSFETs)的半导体器件的性能。图1显示了传统的MOSFET器件。图1的MOSFET制备在被浅槽隔离(shallow trenchisolation)12所限定的有源区内的半导体基片10之上，该浅槽隔离12从制备在基片10上的其它IC组件电隔离出MOSFET的有源区。
MOSFET包含栅极电极14，该栅极电极14通过诸如硅氧化物(silicon oxide)或氧化物-氮化物-氧化物(ONO)的薄第一栅极绝缘体16而与基片10中的沟道区隔离开。为了将栅极14的电阻最小化，栅极14通常由诸如多晶硅的掺杂半导体材料而形成。
MOSFET的源极与漏极提供为形成在栅极14的相对面(opposingsides)的深源极与漏极区(deep source and drain regions)18。源极与漏极硅化物20形成在源极与漏极区18之上，并且包含含有基片半导体材料与诸如钴(Co)或镍(Ni)的金属的化合物，以降低源极与漏极区18的接触电阻。源极与漏极区18形成得足够深以延伸超出源极与漏极硅化物20所形成到的深度。在隔片(spacer)28形成在栅极14与栅极绝缘体16的周围之后注入源极与漏极区18，其用来作为注入掩模以相对于栅极下的沟道区定义出源极与漏极区18的横向位置。
栅极14同样地也有硅化物24形成在其上表面上。包含多晶硅材料及覆盖硅化物的栅极结构有时也称为多晶硅-硅化物栅极(polycidegate)。
MOSFET的源极与漏极还包含浅源极与漏极延伸(shallow sourceand drain extensions)26。随着MOSFET的尺寸缩小，由源极与漏极之间的窄小距离所造成的短沟道效应会导致MOSFET性能的降低。在沟道末端附近使用浅源极与漏极延伸26而非深源极与漏极区有助于降低短沟道效应。浅源极与漏极延伸是在隔片22形成之前注入的，栅极14则作为注入掩模以相对于沟道区18而定义出浅源极与漏极延伸26的横向位置。随后退火期间的扩散会导致浅源极与漏极延伸26在栅极14下略为延伸。
一种用来提高MOSFET性能的选择是提高硅的载流子迁移率，以减小电阻与能耗并增大驱动电流、频率响应以及操作速度。一种已成为近来关注焦点的提高载流子迁移率的方法是使用施加了拉伸应变的硅材料。
“应变(Strained)”硅可通过在硅锗基片上生长硅层来形成。硅锗晶格由于在晶格中存在着较大的锗原子，所以一般比纯硅晶格间隔得更开。因为硅晶格的原子与间隔得更开的硅锗晶格对准，所以在硅层中会产生拉伸应变。硅原子基本上被彼此拉开。施加到硅晶格的拉伸应变量会随着硅锗晶格中锗的比例而增大。
无应变硅(relaxed silicon)有六个相等的价带。将拉伸应变施加到硅晶格会导致四个价带的能量升高，而两个价带的能量降低。作为量子效应的结果，当电子穿越较低的能带时，电子有效地减少30％的重量。因此较低的能带对电流具有较小的阻力。除此之外，电子会从硅原子核受到较小的振动能，这造成电子比在无应变硅中的散射小500至1000倍。结果，与无应变硅相比，应变硅中的载流子迁移率大幅地提高，可使电子的迁移率潜在提高80％或更多而使空穴的迁移率潜在提高20％或更多。已发现迁移率的提高对高达1.5百万伏特/厘米的电场仍可保持。相信这些因素能使器件速度提高35％而不用进一步减小器件尺寸，或能使能耗降低25％而不会降低性能。
使用了应变硅层的MOSFET的例子显示在图2中。该MOSFET制备在基片上，该基片包含其上形成有应变硅的外延层32的硅锗层30。该MOSFET使用了传统的MOSFET结构，该传统的MOSFET结构包括深源极与漏极区18、浅源极与漏极延伸26、栅极氧化物层16、由隔片28、22所围绕的栅极14、硅化物源极与漏极接触20、硅化物栅极接触24以及浅槽隔离12。该MOSFET的沟道区包括在源极与漏极之间提供提高的载流子迁移率的应变硅材料。
图2所示这种类型的应变硅MOSFETs的一个缺点是硅锗的能隙小于硅的能隙。换言之，与在硅晶格中相比，在硅锗晶格中将电子移动到导带中所需的能量平均而言会更低。因而，源极与漏极区形成在硅锗中的器件的结漏泄(junction leakage)会大于源极与漏极区形成在硅中的相当器件的结漏泄。
图2所示这种类型的应变硅MOSFETs的另一个缺点是硅锗的介电常数高于硅的介电常数。因而，加入有硅锗的MOSFETs展现出较高的寄生电容，这增大了器件能耗并减小了驱动电流以及频率响应。
因此，在MOSFET中加入硅锗的设计所取得的优点会被使用硅锗基片所导致的缺点部分抵消。
于是，需要一种MOSFET制备过程，其中，通过在硅顶部上的高度压缩沉积(highly compressive deposition)而将硅予以应变。此外，需要增大在硅MOSFET中的拉伸应变而不改变硅锗层。更进一步，需要用应变硅来提高载流子迁移率。
发明内容
一个示例性实施例涉及一种形成金属氧化物半导体场效应晶体管(MOSFET)的方法。该方法包括提供其上形成有栅极的基片并且至少进行以下沉积步骤中的一种：沉积隔片层并在位于基片上的硅层之上的栅极与栅极绝缘体周围形成隔片；在隔片、栅极与硅层上沉积蚀刻终止层；以及在蚀刻终止层上沉积介电层。沉积隔片、沉积蚀刻终止层与沉积介电层中的至少一个包括高压缩沉积(high compressiondeposition)，该高压缩沉积增大了硅层中的拉伸应变。
另一个示例性实施例涉及一种形成金属氧化物半导体场效应晶体管(MOSFET)的方法，包括提供基片，该基片包含其上形成有硅材料层的硅锗层、形成在该硅层上的至少一层栅极绝缘层与形成在该栅极绝缘层上的栅极导电层。该方法还包括将栅极导电层与栅极绝缘层图案化，以在硅层上形成栅极与栅极绝缘体；在栅极与栅极绝缘体周围形成隔片；在隔片与栅极之上形成蚀刻终止层，以及在高度压缩沉积过程中在蚀刻终止层上形成层间介电层，该高度压缩沉积过程压缩了硅层，导致了硅层中增大的拉伸应变。
又一个示例性实施例涉及一种制备晶体管的方法，该方法包括在硅层上提供栅极，其中该栅极具有紧邻该栅极的横向侧壁的隔片；在该栅极与隔片上形成蚀刻终止层，其中该蚀刻终止层在高压缩沉积中形成，导致硅层中的应变；以及在蚀刻终止层上形成介电层，其中该介电层在高压缩沉积中形成，导致硅层中的应变。
在阅读了以下的附图、详细说明以及所附的权利要求之后，本发明的其它主要特征与优点对本领域技术人员而言将是显而易见的。
附图说明
以下将参照附图来说明本发明的示例性实施例，其中同样的数字表示同样的组件，以及：
图1是依照传统加工所形成的传统MOSFET的示意剖面图；
图2是依照用来形成图1的MOSFET的传统过程所形成的应变硅MOSFET器件的示意剖面图；
图3a-3e是在依照一个示例性实施例来制备MOSFET器件期间所形成的结构的示意剖面图；以及
图4是包含一个示例性实施例与替代性实施例的流程图。
具体实施方式
图3a-3i示意了在依照一个示例性实施例来制备应变硅MOSFET期间所形成的结构。图3a显示了包含硅锗层40的结构，该硅锗层40具有形成在其表面上的硅外延层42。硅锗层40优选具有成分Si1-xGex，其中x约为0.2，并且更一般地是在0.1至0.3的范围。
硅锗层40通常生长在硅晶片上。硅锗可通过，例如，化学气相沉积而生长，使用Si2H6(乙硅烷，disilane)与GeH4(锗烷，germane)作为源气(source gases)，基片温度为600℃至900℃，Si2H6分压为30mPa，GeH4分压为60mPa。SiH4(硅甲烷，silane)可用在替代性的过程中。硅锗材料的生长可用这些比例而起始，或替代性地，GeH4分压可以从低压或零压开始逐渐增加以形成梯度成分。可依照特定的应用来确定硅锗层的厚度。其上生长有应变硅层42的硅锗基片40的上部分应具有均匀的成分。
硅层42优选通过化学气相沉积(CVD)而生长，使用分压为30mPa的Si2H6作为源气，基片温度约为600℃至900℃。硅层42优选生长到200nm的厚度。
如图3a进一步显示，栅极绝缘层44形成在硅层42之上。栅极绝缘层44通常是硅氧化物，但可以是诸如氧化物-氮化物-氧化物(ONO)的另一种材料。氧化物可通过应变硅层的热氧化而生长，但是优选通过化学气相沉积而沉积。
形成在栅极绝缘层44之上的是栅极导电层46。栅极导电层46通常包含多晶硅，但替代性地可包含诸如注入有锗的多晶硅的另一种材料。
在栅极导电层46之上是包含底部硬掩模层48和顶部硬掩模层50的双层硬掩模(bi-layer hardmask)结构，该底部硬掩模层48也被称为底部消反射涂层(bottom antireflective coating，BARC)。底部硬掩模层48通常是硅氧化物(例如，SiO2)，而顶部硬掩模层50则通常是硅氮化物(silicon nitride)(例如，Si3N4)。
硅锗基片还在其中形成有浅槽隔离52。可通过在硅锗层40与硅层42中形成具有楔形(tapered)侧壁的沟槽、进行短暂的热氧化并且随后沉积硅氧化物层至足以填充沟槽的厚度来形成浅槽隔离，该硅氧化物的沉积可通过诸如低压CVD(LPCVD)TEOS或大气压臭氧TEOS。然后，该硅氧化物层通过诸如化学机械抛光(chemical mechanical polishing)或回蚀过程(etch back process)予以致密化与平坦化，以形成与硅层42的表面大致水平的浅槽隔离52。
图3b显示了在将栅极导电层与栅极绝缘层图案化以形成栅极54与自对准的栅极绝缘体56之后的图3a的结构。图案化是利用一系列各向异性蚀刻而进行的，该一系列各向异性蚀刻用光刻胶掩模作为蚀刻掩模来将顶部硬掩模层50图案化，然后用图案化的顶部硬掩模层50作为蚀刻掩模来将底部硬掩模层48图案化，接着用图案化的底部硬掩模层48作为蚀刻掩模来将多晶硅图案化，下一步用栅极54作为硬掩模来将栅极绝缘层图案化。如图3b所示，选择底部硬掩模层48的厚度，使得在将栅极绝缘层图案化后，底部硬掩模层的一部分会留在栅极上以作为保护帽(protective cap)58。
图3c显示了在栅极54、栅极绝缘体56与保护帽58周围形成隔片60之后的图3b的结构。隔片60优选通过沉积保护材料的保形层(conformal layer)，接着各向异性蚀刻以从非垂直表面去除保护材料以留下隔片60而形成。隔片60优选由硅氧化物或硅氮化物而形成。
在一个示例性实施例中，用于形成隔片60的保形层是利用等离子增强化学气相沉积(PEVCD)过程而沉积的。该PECVD过程优选是将拉伸应变加入到硅层42的高压缩沉积。高压缩沉积可通过会对硅层42导致较高速的离子轰击和压缩(higher ion bombardment and compression)的偏压RF电源(biased RF power)而实现。
图3d显示了在栅极54、保护帽58、隔片60和硅层42上保形地沉积蚀刻终止层(ESL)63之后的图3c的结构。在一个示例性实施例中，蚀刻终止层63是在具有高压缩的PEVCD过程中沉积的，以增大硅层42中的拉伸应变。高压缩沉积可用增强的离子轰击来实现。
图3e显示了沉积层间介电(ILD)层65之后的图3d的结构。ILD层65保形地沉积在蚀刻终止层63之上。优选地，ILD层65是在高度压缩的PECVD过程中沉积的。高压缩沉积增大硅层42中的压缩，加入拉伸应变，并且由此增强载流子迁移率。
可以沉积其它的层，诸如衬里层(liner layer)或另一隔片层。这些附加层也可用高压缩沉积技术来沉积，以增大在硅层42中的拉伸应变。
虽然图3a-3e所示的过程代表目前优选的实施例，但可实施许多不同的变化。因而，可以实施依照本发明的许多不同的实施例。通常而言，这样的实施例包含MOSFET，该MOSFET包括在硅锗层上的应变硅沟道区，以及提供在栅极相对面而形成在硅区中的源极与漏极区。源极与漏极区的深度没有延伸超出硅区的深度，因而减小了传统硅锗应用中的不利的结漏泄和寄生电容。
在一个替代性的实施例中，在处理了硅锗之后可使用扩散炉，以通过运行湿氧化清洗周期(wet oxidation clean-up cycle)来处理非-SiGe材料。该湿氧化周期包括高温H2O氧化以将Ge转变为挥发性的Ge-氧化物。可重复这样的过程以将污染降低到检测极限之下。
在另一个替代性的实施例中，应变硅技术可以结合完全耗尽的(fully-depleted)绝缘体上硅(SOI)。然而，存在着一个挑战，因为应变硅是由下面的SiGe层所支撑的，当去除了SiGe后应变可能消失。通过引入具有与SiGe类似的晶格常数的单晶高-k材料，可以维持应变。例如，20％SiGe可用DySiO3或GdSiO3来实现。
在另一个替代性的实施例中，将环氧树酯封盖(epoxy seal)或另一种合适材料的封盖施加到硅芯片的上表面。通过改变封盖材料的特性，可改变硅芯片中的应力以引入拉伸应力。如上所述，拉伸应力会改善载流子迁移率，从而提高器件的速度。另一种增大拉伸应力的方法是使用圆拱形的(dome-shaped)金属基片，在该圆拱形的金属基片之上可以放置芯片。圆拱形状可通过冲压(stamping)或蚀刻而制成。圆拱形状给硅芯片提供物理应力(physical stress)，从而产生拉伸应力。
图4显示了包含图3a-3e的优选实施例、前述替代性实施例及其它替代性实施例的流程图。首先，在操作80中提供基片，该基片包括其上形成有硅层的硅锗层。该基片还包括形成在应变硅层上的栅极绝缘体与形成在栅极绝缘体上的栅极。在操作82中，沉积隔片层以及在栅极与栅极绝缘体周围形成隔片。在一个示例性实施例中，隔片层是以高度压缩的形式沉积的，在下方的硅层中导致压缩，从而导致拉伸应变。
在操作84中，在栅极、隔片以及硅层之上保形地提供蚀刻终止层。在一个示例性实施例中，蚀刻终止层是以高压缩形式沉积的，增大了硅层中的拉伸应变。在操作86中，层间介电层(ILD)沉积在蚀刻终止层之上。替代性地，可以沉积任一层材料。在一个示例性实施例中，ILD层是在高压缩PECVD过程中沉积的。操作82、84以及86的沉积中的至少一个可使用高压缩沉积。或者，高压缩沉积可用在所有三个操作82，84与86中。在操作88中，加工该结构，包括形成许多不同特征中的任一个，诸如源极与漏极区的接触、金属互连、IMD层和钝化层。
对本领域的普通技术人员而言显而易见的是，在上述过程中所说明的任务没有必要排除其它的任务，而是进一步的任务可依照所要形成的特定结构而并入到上述过程中。例如，中间的加工任务，诸如在加工任务之间钝化层或保护层的形成与去除、光刻胶掩模和其它掩模层的形成与去除、掺杂与反掺杂、清洗、平坦化以及其它任务，可以与上述特定说明的任务一起进行。
在示例性实施例的说明中所描述的过程并不需要在整个基片上进行，诸如在整个晶片上，而是可在基片的部分之上选择性地进行。因此，虽然示意在附图中并在上面加以说明的实施例目前是优选的，但应该了解的是，这些实施例仅是作为例子而提供的。本发明并不限于特定的实施例，而是延伸到落入所要求保护的发明与等价物的范围之内的各种不同的变化、组合和排列。
Claims (10)
1.一种形成金属氧化物半导体场效应晶体管(MOSFET)的方法，包括：
提供基片(40)，所述基片(40)上形成有栅极(54)；以及
进行以下沉积步骤中的至少一个：
沉积隔片层并在位于所述基片(40)上的硅层(42)之上的栅极(54)与栅极绝缘体(56)的周围形成隔片(60)；
在所述隔片(60)、栅极(54)与硅层(42)之上沉积蚀刻终止层(63)；以及
在所述蚀刻终止层(63)之上沉积介电层(65)；
其中，沉积隔片层、沉积蚀刻终止层(63)与沉积介电层(65)中的至少一个包括高压缩沉积，由此所述硅层(42)的拉伸应变增大。
2.如权利要求1所述的方法，其中，沉积隔片层、沉积蚀刻终止层(63)与沉积介电层(65)都包括高压缩技术。
3.如权利要求2所述的方法，其中，所述高压缩技术包括高速离子轰击。
4.如权利要求1所述的方法，进一步包括利用用于高速离子轰击的偏压RF电源来沉积衬里。
5.如权利要求1所述的方法，其中，所述硅层具有至少200nm的厚度。
6.一种制备晶体管的方法，包括：
在硅层(42)之上提供栅极(54)，所述栅极(54)具有紧邻所述栅极(54)的横向侧壁的隔片(60)；
在所述栅极(54)与隔片(60)上形成蚀刻终止层(63)，其中，所述蚀刻终止层(63)是在高压缩沉积中形成的，在所述硅层(42)内导致应变；以及
在所述蚀刻终止层(63)之上形成介电层(65)，其中，所述介电层(65)是在高压缩沉积中形成的，在所述硅层(42)内导致应变。
7.如权利要求6所述的方法，其中，衬里包括在所述栅极(54)与隔片(60)之间。
8.如权利要求6所述的方法，其中，所述蚀刻终止层(63)与介电层(65)是利用等离子增强化学气相沉积(PEVCD)而沉积的。
9.如权利要求8所述的方法，其中，所述PEVCD包括用于较高速的离子轰击的偏压RF电源。
10.如权利要求6所述的方法，其中，所述蚀刻终止层(63)包含硅氮化物。
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-
2003
- 2003-01-17 US US10/346,617 patent/US7001837B2/en not_active Expired - Lifetime
-
2004
- 2004-01-13 DE DE112004000146T patent/DE112004000146B4/de not_active Expired - Lifetime
- 2004-01-13 KR KR1020057013068A patent/KR101023208B1/ko active IP Right Grant
- 2004-01-13 GB GB0512330A patent/GB2411768B/en not_active Expired - Lifetime
- 2004-01-13 WO PCT/US2004/000981 patent/WO2004068586A1/en active Search and Examination
- 2004-01-13 JP JP2006502832A patent/JP2006517343A/ja active Pending
- 2004-01-13 CN CN2004800074546A patent/CN1762056B/zh not_active Expired - Lifetime
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- 2006-02-17 US US11/356,606 patent/US7701019B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US20040142545A1 (en) | 2004-07-22 |
| DE112004000146T5 (de) | 2006-02-02 |
| US7001837B2 (en) | 2006-02-21 |
| CN1762056B (zh) | 2011-06-01 |
| US7701019B2 (en) | 2010-04-20 |
| JP2006517343A (ja) | 2006-07-20 |
| GB2411768B (en) | 2006-04-26 |
| KR20050086961A (ko) | 2005-08-30 |
| GB0512330D0 (en) | 2005-07-27 |
| KR101023208B1 (ko) | 2011-03-18 |
| WO2004068586A1 (en) | 2004-08-12 |
| US20060138479A1 (en) | 2006-06-29 |
| GB2411768A (en) | 2005-09-07 |
| DE112004000146B4 (de) | 2010-05-06 |
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