CN100365766C - 厚应变硅层及含有厚应变硅层的半导体结构的形成方法 - Google Patents

厚应变硅层及含有厚应变硅层的半导体结构的形成方法 Download PDF

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CN100365766C
CN100365766C CNB2003801080501A CN200380108050A CN100365766C CN 100365766 C CN100365766 C CN 100365766C CN B2003801080501 A CNB2003801080501 A CN B2003801080501A CN 200380108050 A CN200380108050 A CN 200380108050A CN 100365766 C CN100365766 C CN 100365766C
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silicon layer
germanium
strained silicon
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strained
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CN1732556A (zh
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汪海宏
P·R·贝塞尔
J-S·古
M·V·努
E·N·帕东
相奇
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Abstract

在硅锗层(40)上生长应变硅层(50)，并在与应变硅(50)同一个连续的原位沉积过程中在应变硅(50)上生长硅锗层(52)。在形成应变硅层(50)之前，在下硅锗层(40)内形成浅沟槽隔离(48)。该两层硅锗层(40，52)在应变硅层(50)的两个表面上有效地提供两层基片，用来维持应变硅层(50)的拉伸应变，并防止在加工中可能会因温度变化而产生的错配位错的形成。因此，对于硅锗层(40，52)给定的锗含量，能生长的应变硅(50)的临界厚度可有效加倍，而在随后的加工中不会有显著的错配位错。在形成应变硅层(50)之前形成浅沟槽隔离(48)避免了应变硅层(50)受到极端的热应力，并进一步减少了错配位错的形成。

Description

厚应变硅层及含有厚应变硅层的半导体结构的形成方法
技术领域
本发明涉及半导体集成电路，特别是涉及含有应变硅(strainedsilicon)的半导体器件。
背景技术
对改进电子器件性能的持续需求可通过致力于减小单个半导体电路组件尺寸的硅加工与器件技术的进步来加以解决。不过，经济限制与物理限制使得持续减小器件尺寸更加困难，所以正在寻求替换的解决方案以使器件的性能能持续增加。
提高MOSFET性能的一个选择是增强硅的载流子迁移率(carriermobility)以减小电阻与能耗并增加驱动电流、频率响应与运行速度。近来已成为关注焦点的一种增强载流子迁移率的方法是使用作用有拉伸应变(tensile strain)的硅材料。通过在硅锗基片上生长一层硅可形成“应变”硅。由于晶格中存在较大的锗原子，所以硅锗晶格一般比纯硅晶格有更宽的间隔。因为硅晶格的原子与伸展更宽的硅锗晶格对齐，所以在硅层内产生了拉伸应变。硅原子基本上被相互拉开。作用于硅晶格的拉伸应变量会随着硅锗晶格中锗原子比例的增加而增加。
无应变硅(relaxed silicon)有六个相等的价带。作用于硅晶格的拉伸应变造成四个价带能量增加而二个价带能量减少。由于量子效应所造成的结果，当电子通过较低的能带时电子有效重量减少了百分之30。因此较低的能带对电子流动有较低的电阻。此外，电子受到较少的来自硅原子核的振动能，造成电子散射率比无应力硅少500到1000倍。结果，与无应变硅相比，应变硅内的载流子迁移率大幅增加，使电子迁移率可增加80％或更多，空穴迁移率可增加20％或更多。已发现迁移率对于达1.5兆伏/厘米的电流场可持续增加。相信这些因素可使器件速度增加35％而不需进一步减小器件尺寸，或可使能耗减小25％而不会降低性能。
图1显示了利用应变硅层的MOSFET的例子。该MOSFET制造在一基片上，该基片包含其上形成有应变硅外延层12的硅锗层10。该MOSFET具有常规的MOSFET结构，包括深源极与漏极区14，浅源极与漏极延伸16，栅氧化物层18，由隔片22、24包围的栅极20，硅化物源极与漏极接触26，硅化物栅极接触28和浅沟槽隔离30。该MOSFET的沟道区包括应变硅材料，在源极与漏极间提供增强的载流子迁移率。
尽管应变硅的理论上的优势大有可为，但是应变硅的制造与加工有许多问题。问题之一是会因温度改变而在应变硅内形成“错配位错(misfit dislocations)”。错配位错是有效释放作用在硅晶格上应变的硅晶格内的位错。错配位错主要是由应变硅晶格与下方硅锗支持层晶格之间的失配(mismatch)所造成。应变硅层内的错配位错量可能会因热因素而增加。由热因素引起错配位错的一个例子是在沉积应变硅层之后的冷却期间。产生错配位错的另一个例子是在暴露于高温期间，例如1000℃或更高，诸如在形成浅沟槽隔离期间。相信如此高温会造成硅锗基片的锗含量的耗尽(depletion)，导致在上面的应变硅内形成错配位错。错配位错的形成率随温度上升而呈指数增加。
已确定应变硅层具有临界厚度，大于此厚度则错配位错显著地变得更可能产生。临界厚度取决于作用在硅晶格上的拉伸应变量，因此取决于下面的硅锗层的锗含量。例如，已确定约具20％锗含量的硅锗层可维持约200埃的临界厚度而没有显著错配位错的风险，而约具30％锗含量的硅锗层只能维持约80埃的临界厚度。
因此将目前的应变硅技术应用到MOSFET设计被相互矛盾的限制所阻碍，因为应变硅载流子迁移率可通过增加下层的锗含量而增强，但是应变硅的临界厚度却因增加下层的锗含量而减小。这些矛盾使得实际应用难以实现。例如，依经验确定至少需要约70埃的应变硅才能有效改善MOSFET的性能。然而，为了解决加工期间硅的消耗，最初所形成的厚度必须大致加倍，并且为了避免在这种厚度的层膜内的错配位错，下层的锗含量必须限制到约20％。已发现作用于应变硅层的应变对空穴迁移率具有相对较小的效果，因此应变硅在PMOS器件中难以提供有效的应用。除了上述考虑之外，应变硅层的拉伸应变及其载流子迁移率会通过错配位错的形成而进一步退化，该错配位错由加工期间通常会遇到的升温与降温所造成，诸如在形成浅沟槽隔离期间。因此，尽管可以平衡应变硅技术的限制因素以在某些应用中有限地提高载流子迁移率，但是目前技术并不提供可赋予足够应变以显著增强载流子迁移率而又不会引进降低迁移率的缺陷及应变松弛(strainrelaxation)的方法。
发明内容
因此本发明的一个目的是提供厚度大于常规临界厚度的应变硅层，但却不具有厚度大于常规临界厚度的应变硅层所特有的错配位错量。
本发明的另一个目的是提供一种MOSFET器件，其含有厚度大于常规临界厚度的应变硅层。
根据本发明的实施例，在硅锗层上生长应变硅层之前先在硅锗层内形成浅沟槽隔离。随后，在一个连续的原位沉积过程中，在硅锗层上制备应变硅层并在应变硅层上形成第二硅锗层。此方式在应变硅层的两个表面上有效地提供两层基片，用来维持应变硅层的拉伸应变并防止错配位错的形成。因此，对于硅锗层给定的锗含量，能生长的应变硅的厚度可有效加倍，并且不会因随后的加热和冷却而有易于形成显著的错配位错的极大风险。此外，在生长应变硅层之前形成浅沟槽隔离避免应变硅层受到浅沟槽隔离生长的热循环，因此进一步保护了应变硅层。
根据本发明的一个实施例，在两层硅锗层中间形成应变硅层。最初提供具有第一硅锗层的基片。然后在第一硅锗层上形成应变硅层，并在一个连续的原位沉积过程中在应变硅层上形成第二硅锗层。第一与第二硅锗层维持应变硅层的拉伸应变，并在随后对应变硅层冷却和加热期间防止错配位错的形成。
根据本发明的另一个实施例，一种半导体结构包括第一硅锗层，生长在第一硅锗层上的应变硅层，以及生长在应变硅层上的第二硅锗层。第一与第二硅锗层维持应变硅层的拉伸应变，并防止在应变硅层内形成错配位错。
根据本发明的又一个实施例，形成了一个包括厚应变硅层的半导体器件。最初提供具有第一硅锗层的基片。在第一硅锗层内形成浅沟槽隔离。然后在第一硅锗层上形成应变硅层，并在与应变硅层一个连续的原位沉积过程中在应变硅层上形成第二硅锗层。第一与第二硅锗层维持应变硅层的拉伸应变，并在随后对应变硅层冷却和加热期间防止错配位错的形成。随后去除第二硅锗层，并在浅沟槽隔离间形成包含应变硅层的MOSFET。
根据本发明的又一个实施例，一个MOSFET包括沟道区，形成在沟道区上的栅绝缘层，形成在栅绝缘层上的栅极，以及位于沟道区相对两侧的源极与漏极区。至少MOSFET的沟道区包含厚度大于临界厚度的应变硅层，该临界厚度依据其上形成有应变硅层的硅锗层的锗含量加以确定。
附图说明
与下面的附图一起说明本发明的实施例，其中：
图1显示了一个具有根据常规加工所形成的应变硅层的MOSFET；
图2a，2b，2c，2d，2e，2f，2g，2h，2i，2j，2k和2L显示了根据本发明第一优选实施例制造MOSFET期间所形成的结构；
图3显示了根据另一个实施例所形成的结构；
图4显示了包含第一优选实施例与其它实施例的工艺流程；以及
图5显示了包含第一优选实施例与其它实施例的工艺流程。
具体实施方式
图2a-2L显示了根据本发明一个优选实施例制造应变硅MOSFET期间所形成的结构。图2a显示了包含硅锗层40的结构。硅锗层40优选具有成分Si1-xGex，其中x约为0.3，更通常是在0.1到0.4的范围内。通常是在硅晶片(未显示)上生长并支撑硅锗层40。例如，可通过以Si2H6(乙硅烷)与GeH4(四氢化锗)作为气源(source gases)的化学气相沉积来生长硅锗，基片温度为600-900℃，Si2H6分压为30毫帕，GeH4分压为60毫帕。在其它过程中可使用SiH4(硅烷)。使用这些比例可使硅锗层40开始生长，或者GeH4的分压可以从低压或零压开始逐渐增大以形成梯度成分，该梯度成分的上部与随后形成的应变硅层形成一个结(junction)，并具有所需的锗含量(例如，30％)。
形成在硅锗层40上的是一个双层硬掩模结构(bi-layer hardmaskstructure)，包括下硬掩模层42，亦称为下消反射涂层(BARC)，和上硬掩模层44。下硬掩模层42通常为硅氧化物(silicon oxide)(例如，二氧化硅)，而上硬掩模层44通常为硅氮化物(silicon nitride)(例如，Si3N4)。
图2b显示了用双层硬掩模将硅锗层40形成图形以得到具有渐缩侧壁(tapered sidewalls)的沟槽46之后的图2a的结构。图2c显示了从硅锗层40去除双层硬掩模材料，并接着在沟槽中形成浅沟槽隔离48之后的图2b的结构。浅沟槽隔离48的形成可通过对硅锗进行简短的热氧化，随后沉积硅氧化物层，使其厚度足以填满沟槽，诸如低压CVD(LPCVD)TEOS或大气压力臭氧TEOS。然后将硅氧化物层致密化并平坦化，例如通过化学机械抛光或者回蚀过程(etch back process)，使浅沟槽隔离48与硅锗层40的表面大致水平。形成浅沟槽隔离48的典型处理可能要利用超过1000℃的温度。通过在形成应变硅之前形成浅沟槽隔离48，应变硅不会受到此温度的影响，因此排除了浅沟槽隔离的处理作为错配位错可能的来源。
图2d显示了进行回蚀过程以从硅锗层40表面去除材料之后的图2c的结构。图2e显示了在硅锗层40上形成应变硅层50并且在应变硅层50上形成上硅锗层52之后的图2d的结构。实施产生图2d结构的回蚀以去除硅锗层40的一部份，使得硅锗层40的上表面相对于浅沟槽隔离48的上表面较低，而使浅沟槽隔离48的上表面与随后形成的上硅锗层52的上表面大致水平。然而，去除量是可以变化的。
应变硅层50优选通过选择性外延生长以化学气相沉积(CVD)过程来生长，例如使用Si2H6作为气源，分压为30毫帕，基片温度约为600到900℃。应变硅层50与上硅锗层52在一个连续的原位过程中生长，在上硅锗层52形成之前对应变硅层50的冷却或加热优选最少。它的实现可通过在生长所需厚度的应变硅层之后，将锗气源(例如四氢化锗)引入沉积室，以将沉积材料的成分从硅变为具有所需锗含量的硅锗，而不显著改变应变硅层的温度。考虑到生长在应变硅层上硅锗的厚度，也希望将在最佳应变硅沉积温度与最佳硅锗沉积温度之间的任何温度变化加以分级(grade)，使得在应变硅层的上表面有适量的硅锗，以便当发生温度变化时用来支撑应变硅层。形成的上硅锗层52在与应变硅层50的结处的锗含量与下硅锗层40的相同(例如约30％)，以提供对应变硅层50内所产生的拉伸应变的最大支持，但以后如有需要可以分级。上硅锗层52的厚度可根据特定的应用而确定。
如上所述，约具30％锗含量的硅锗层能支持约80埃的应变硅层，而不会在冷却或随后的热处理期间有显著错配位错的风险。与此不同，具有约30％锗含量的下硅锗层40与上硅锗层52支持优选实施例的应变硅层50的两面。因此可形成厚度大于约80埃的应变硅层50，通常是超过约140埃，并有可能高达约160埃，而不会在冷却或随后的热处理期间有显著错配位错的风险。
图2f显示了去除第二硅锗层，并随后形成数层不同材料之后的图2e的结构。可通过与硅相比对硅锗有很高蚀刻选择性的选择性湿法蚀刻来去除上硅锗层。或者，可通过高度可控的氧化过程来氧化硅锗，诸如用热蒸汽，随后在HF溶液中去除。在进一步处理之前，在冷却期间存在的上硅锗层可在冷却期间提供对错配位错形成的额外阻力。所形成的材料层包括形成在应变硅层50上的栅绝缘层54。栅绝缘层54通常为硅氧化物，但也可以是另外的材料，诸如氧化物-氮化物-氧化物(ONO)。氧化物可通过应变硅层的热氧化来生长，或通过化学气相沉积来沉积。形成在栅绝缘层54上的是栅导电层56。栅导电层56通常包括多晶硅，但也可包括另外的材料，诸如注入有锗(implanted withgermanium)的多晶硅。在栅导电层56上的是双层硬掩模结构，包括下硬掩模层58，亦称为下消反射涂层(BARC)，和上硬掩模层60。下硬掩模层58通常为硅氧化物(例如，SiO2)，而上硬掩模层60通常为硅氮化物(例如，Si3N4)。
图2g显示了将栅导电层和栅绝缘层形成图形以得到栅极62和自对准栅绝缘体64(a self-aligned gate insulator)之后的图2f的结构。利用一系列各向异性蚀刻来形成图形，用光刻胶掩模作为蚀刻掩模将上硬掩模层形成图形，然后用已形成图形的上硬掩模层作为蚀刻掩模将下硬掩模层形成图形，然后用已形成图形的下硬掩模层作为蚀刻掩模将栅导电层形成图形，然后用栅极62作为硬掩模将栅绝缘层形成图形。
图2h显示了在栅极62和栅绝缘体64周围形成薄第一栅隔片(thinfirst gate spacer)66之后的图2g的结构。薄第一栅隔片66的形成优选通过沉积保护材料的保形层(conformal layer)，并随后用各向异性蚀刻从非垂直表面去除保护材料而在栅极62和栅绝缘体64周围形成薄第一栅隔片66。薄第一栅隔片66优选由硅氧化物或硅氮化物形成。
图2i显示了注入掺杂剂以在应变硅层50内在沟道区相对两侧形成浅源极与漏极延伸68之后的图2h的结构。在浅源极与漏极延伸68注入之前可注入光环区(halo region)(未显示)。光环区的掺杂剂与源极与漏极延伸68的掺杂剂导电性相反。通过缩减在源极与漏极延伸68末端的耗尽区(depletion region)，光环区有助于抑制短沟道“穿通(punchthrough)”效应。光环区的注入优选低能量并与基片表面呈小角度，使得光环区在栅极62之下延伸以越过源极与漏极延伸68末端在退火后的预期位置。与源极与漏极延伸68相同，光环区形成在沟道区相对两侧，并且向沟道区延伸以越过将形成的源极与漏极延伸的末端。
图2j显示了在栅极62和薄第一隔片66周围形成第二隔片70，并随后注入掺杂剂以在应变硅层50与硅锗层40内形成深源极与漏极区72之后的图2i的结构。在深源极与漏极区72注入期间，第二隔片70作为注入掩模以界定深源极与漏极区72相对于MOSFET沟道区的位置。深源极与漏极区72的深度延伸越过应变硅层50而进入下硅锗层40内。
图2k显示了进行快速热退火(RTA)以将应变硅层50与硅锗层40退火并且将注入到浅源极与漏极延伸68和深源极与漏极区72内掺杂剂激活之后的图2j的结构。在退火期间，在应变硅层50与硅锗层40内会发生注入掺杂剂的某些扩散。
图2L显示了在源极与漏极区72上形成硅化物接触74并在栅极62上形成硅化物接触76之后的图2k的结构。硅化物接触由包括半导体材料与金属的化合物形成。通常使用诸如钴(Co)的金属，然而也可使用诸如镍(Ni)的其它金属。硅化物接触的形成是通过在基片上沉积金属的薄保形层，然后退火以促进硅化物形成在金属与下面的半导体材料之间的接触点，随后去除残留金属。
图3显示了图2a-2L实施例的替换实施例。图3实施例与图2a-2L实施例的不同之处在于省略了在图2c的硅锗层上进行回蚀处理以产生图2d的结构。结果，下硅锗层40的上表面与浅沟槽隔离48的上表面大致水平，并且随后通过在硅锗层40上的选择性生长而形成的应变硅层50延伸越过浅沟槽隔离48的上表面。由于使用了选择性生长过程，所以在硅氧化物浅沟槽隔离48上很少或没有发生硅的生长。因此浅沟槽隔离48上的区域保持为空，并在随后的处理中当施加诸如BPSG的保护层时加以填充。
因此器件的构建不限于图2a-2L的实施例。图4显示了形成包含图2a-2L优选实施例、前述替换实施例及其它可选择实施例的应变硅层的工艺流程。最初提供基片(80)。基片包括第一硅锗层。然后在第一硅锗层上形成应变硅层(82)。应变硅层的厚度优先大于依据第一硅锗层的锗含量所确定的常规临界厚度。然后在与应变硅同一个连续的原位沉积过程中在应变硅层上形成第二硅锗层(84)。第一与第二硅锗层维持应变硅层的拉伸应变并防止在应变硅层内形成错配位错，即使应变硅层的厚度超过临界厚度。
图5显示了形成包括图2a-2L优选实施例、图3替换实施例及其它可选择实施例的半导体器件的工艺流程。最初提供基片(90)。基片包括第一硅锗层。然后在硅锗层内形成浅沟槽隔离(92)。随后在第一硅锗层上形成应变硅层(94)，并在与应变硅层同一个连续的原位沉积过程中在应变硅层上形成第二硅锗层(96)。在形成应变硅层之前，可在第一硅锗层上进行回蚀处理。然后去除第二硅锗层(98)，并在浅沟槽隔离间形成包括应变硅层的MOSFET(100)。
依据其它实施例可按需求实现额外特征。在一个实施例中，用晶体高-k介电层(crystalline high-k dielectric layer)来取代氧化物或氧化物-氮化物-氧化物栅绝缘层，该晶体高-k介电层的晶格常数可与下硅锗层的相比拟，因此对应变硅层内的拉伸应变提供了额外的支持。例如，对于20％的硅锗层，晶体DyScO3或GaScO3的栅绝缘层提供了适当的晶格。可通过分子束外延(MBE)生长此类晶体。在另一个实施例中，晶体高-k介电层可用作绝缘体上硅构建中的介电基片，也可用作此类构建中的栅绝缘材料。
对本领域普通技术人员显而易见的是，上面过程中所描述的任务不一定会排斥其它任务，相反，可依据所要形成的特定结构将其它任务并入上面过程中。例如，诸如在加工任务间钝化层或保护层的形成与去除、光刻胶掩模与其它掩模层的形成与去除、掺杂与反掺杂、清洗、平坦化以及其它任务的中间加工可与上述特定任务一起进行。另外，过程不需要在整个基片上进行，诸如整个晶片，相反，可在基片部分上选择性进行。因此，尽管目前优选上述示意在附图中的实施例，但是应了解这些实施例只是用于示例而提供的。本发明并不限于特定的实施例，而是涵括落在本发明权利要求及其等价物范围之内的不同的修改、组合及排列。

Claims (5)

1.一种形成半导体器件的方法，包括：
提供包含第一硅锗层(40)的基片；
在所述第一硅锗层(40)内形成浅沟槽隔离(48)；
在所述第一硅锗层(40)上形成应变硅层(50)；以及
在与所述应变硅层(50)原位的单一连续沉积过程中，在所述应变硅层(50)上形成第二硅锗层(52)，
其中所述第一(40)与第二(52)硅锗层支持所述应变硅层(50)的拉伸应变，并且防止在所述应变硅层(50)内形成错配位错。
2.如权利要求1所述的方法，其中所述第一硅锗层(40)具有成分Si1-xGex，其中x在0.1到0.4的范围内。
3.如权利要求1所述的方法，其中所述应变硅层(50)的厚度超过依据所述第一硅锗层(40)的锗含量所确定的临界厚度。
4.如权利要求1所述的方法，进一步包括：
去除所述第二硅锗层(52)；以及
在所述浅沟槽隔离(48)间形成包含所述应变硅层(50)的金属氧化物半导体场效应晶体管。
5.如权利要求4所述的方法，其中在形成所述应变硅层(50)之前，去除所述第一硅锗层(40)的一部份以使所述第一硅锗层(40)的上表面相对于所述浅沟槽隔离(48)的上表面较低。
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