CN100459160C - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN100459160C
CN100459160C CNB2005100763865A CN200510076386A CN100459160C CN 100459160 C CN100459160 C CN 100459160C CN B2005100763865 A CNB2005100763865 A CN B2005100763865A CN 200510076386 A CN200510076386 A CN 200510076386A CN 100459160 C CN100459160 C CN 100459160C
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silicon substrate
film
mixed crystal
sige mixed
semiconductor device
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CN1822392A (zh
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田村直义
岛宗洋介
畑田明良
片上朗
岛昌司
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Fujitsu Semiconductor Ltd
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Abstract

一种半导体器件，包括：栅电极，经由栅极绝缘膜形成在与沟道区域对应的硅衬底上；p型源极和漏极区域，形成在栅电极上的侧壁绝缘膜各外侧的硅衬底中；一对SiGe混晶区域，形成在侧壁绝缘膜各外侧的硅衬底中且与硅衬底为外延关系，以便分别被源极区域和漏极区域围绕，每个所述SiGe混晶区域生长到栅极绝缘膜和硅衬底之间的栅极绝缘膜界面的水平面之上的水平面，其中在SiGe混晶区域的各上表面上设置压应力膜。

Description

半导体器件
相关申请的交叉参考
本申请基于在2005年2月18日提交的日本在先申请号2005-042870，在此通过参考并入其全部内容。
技术领域
一般来说，本发明涉及半导体器件，更具体地，涉及一种通过应用应力而具有提高的运行速度的半导体器件及这种半导体器件的制造方法。
背景技术
随着器件微型化领域的进展，现在已经可以实现栅极长度等于或小于100nm的非常微小且超快速的半导体器件。
利用这种非常微小且超快速的晶体管，栅电极正下方的沟道区域的面积比常规半导体器件要小得多，由此，穿过沟道区域的电子或空穴的迁移率受到施加于此沟道区域的应力的严重影响。
由此，人们已经进行了各种尝试，以优化施加于沟道区域的应力，期望进一步提高半导体器件的运行速度。
在使用硅衬底作为沟道区域的半导体器件中，空穴的迁移率一般小于电子的迁移率，由此，在设计半导体集成电路时，提高p沟道MOS晶体管(其中空穴被用作载流子)的运行速度变得特别重要。
对于这种p沟道MOS晶体管，众所周知，通过对沟道区域施加单轴压应力可提高载流子的迁移率，并且提出使用图1的构造作为对沟道区域施加压应力的方式。
参照图1，在硅衬底1上经由栅极绝缘膜2形成栅电极3，并且栅电极3横向两侧的硅衬底1中形成p型扩散区域1a和1b，从而限定沟道区域。而且，在栅电极3的侧壁表面上形成侧壁绝缘膜3A和3B，从而同时覆盖部分硅衬底1的表面。
由此，扩散区域1a和1b分别用作MOS晶体管的源极延伸区域和漏极延伸区域，并且通过施加于栅电极3的栅极电压，控制穿过位于栅电极3正下方的沟道区域的空穴从扩散区域1a到扩散区域1b的流动。
而且，在图1的构造中，在侧壁绝缘膜3A和3B各外侧的硅衬底11中，形成有SiGe混晶区域1A和1B，其与硅衬底1为外延关系，并且在分别与扩散区域1a和扩散区域1b连续的SiGe混晶区域1A和1B中形成p型源极和漏极区域。
由于在图1构造的MOS晶体管中SiGe混晶区域1A和1B具有大于硅衬底1的晶格常数，所以SiGe混晶区域1A和1B被施加有如图1中箭头a所示的压应力，结果，SiGe混晶区域1A和1B在大体上垂直硅衬底1表面的方向上会经受形变，如箭头b所示。
由于SiGe混晶区域1A和1B由此被外延形成在硅衬底1上，箭头b所示的SiGe混晶区域1A和1B的这种形变会导致如箭头c所示的硅衬底沟道区域中的对应形变，而沟道区域中的这种形变会导致产生如箭头d所示的沟道区域中的单轴压应力。
作为施加于图1的MOS晶体管沟道区域的这种单轴压应力的结果，构成沟道区域的Si晶体的对称性被局部调整，以及作为对称性的这种局部调整结果，在价带中重空穴和轻空穴解除简并。由此，导致沟道区域中空穴迁移率的增大，从而提高了晶体管的运行速度。
应当注意，这种通过局部产生的应力引起的沟道区域中空穴迁移率的增大尤其会显著出现在栅极长度等于或小于100nm的非常微小的半导体器件中。
图2表示基于这种原理并且在非专利文献1中有所描述的p沟道MOS晶体管的构造。在该图中，那些与先前描述过的部分对应的部分由相同的标号表示，并且省略其描述。
参照图2，SiGe混晶区域1A和1B被外延地形成，以便将填充在硅衬底1中形成的各个沟槽直到高于硅衬底1和栅电极2之间的界面(在图中如虚线L所示)的水平面。
而且，应当注意，SiGe混晶区域1A和1B的相互面对的侧表面1As和1Bs被形成为具有弯曲的形状，从而使得在SiGe混晶区域1A和1B之间的距离从栅极绝缘膜2的下表面在硅衬底1的向下方向上连续增大。
而且，在图2的常规构造中，生长到高于前述水平面L的水平面的SiGe混晶区域1A和1B直接形成有硅化物层4。相似的硅化物层4还形成在多晶硅栅电极3上。
参考文献
(专利文献1)美国专利6621131
(专利文献2)日本特开专利申请2004-31753
(专利文献3)日本特开专利申请8-167718
(专利文献4)日本特开专利申请2003-179157
(非专利文献1)汤普森(Thompson)，S.E.等人，IEEE Transactionson Electron Devices，vol.51，No.11，2004年11月，pp.1790-1797
发明内容
本发明提供一种这样的具有应力沟道区域的p沟道MOS晶体管的构造，其中沟道区域的应力能被进一步增大。
在第一方案中，本发明提供一种半导体器件，包括：
硅衬底，具有由器件隔离区域限定的器件区域，并且在所述器件区域中包括沟道区域；
栅电极，经由栅极绝缘膜形成在与所述沟道区域对应的所述硅衬底上，所述栅电极在其一对相对的侧壁表面上分别承载一对侧壁绝缘膜；
P型源极和漏极延伸区域，跨越所述沟道区域形成在所述栅电极各横向侧的所述硅衬底中；
P型源极和漏极区域，与所述源极延伸区域和所述漏极延伸区域连续地分别形成在所述侧壁绝缘膜的各外侧的所述硅衬底中；以及
一对SiGe混晶区域，形成在所述侧壁绝缘膜各外侧的所述硅衬底中且与所述硅衬底为外延关系，以便分别被所述源极区域和所述漏极区域围绕，
每个所述SiGe混晶区域生长到所述栅极绝缘膜和所述硅衬底之间的栅极绝缘膜界面的水平面之上的水平面，
其中在所述一对SiGe混晶区域的各上表面上设置压应力膜。
按照本发明，通过在SiGe混晶区域各上表面上设置这样的压应力膜，在平行于所述硅衬底的平面中、在与被限定为连接所述源极区域和所述漏极区域的方向的沟道方向垂直的方向上，压缩SiGe混晶区域，结果，每个SiGe混晶区域在前述沟道方向上经受扩张，而SiGe混晶区域在沟道方向上的这种扩张也在沟道方向上导致沟道区域的压缩。由此，按照参照图1所述的机制，由SiGe混晶区域施加于沟道区域的压应力被进一步增强，并且在沟道区域中的空穴迁移率被进一步提高。由此，应当注意，由于在SiGe混晶区域的外侧、在沟道方向上形成有器件隔离结构，因此在向外方向即在远离沟道方向的方向上SiGe混晶区域的扩张基本上被这种器件隔离结构阻止，并且仅在朝向沟道区域的方向上产生SiGe混晶区域的扩张。
由此，应当注意，这种压应力膜在形成于SiGe混晶区域的侧壁表面上时，通过压应力膜的收缩会导致SiGe混晶区域在垂直于衬底的方向上压缩，由此，减少了在图1中箭头c所示的垂直方向上沟道区域的扩张形变。由此，减小了由于沟道区域的这种扩张形变而产生的图1所示压应力d的大小。
由此，通过本发明，在SiGe混晶区域的侧壁表面上形成张应力膜，用于减少垂直于衬底表面作用于SiGe混晶层的压应力。而且在栅电极的侧壁表面上形成类似的张应力膜，从而使得张应力膜从向上方向朝着沟道区域推动栅电极。由此，减少了在向上和向下方向上在沟道区域中形成的压应力。
而且，按照本发明，沿着器件隔离结构(设置于沟道区域的右边和左边)的器件隔离沟槽形成的张应力膜的厚度在相邻于沟道区域的部分上增大。由此，能够通过在朝着沟道区域的方向在沟道区域右部和左部填充器件隔离沟槽的器件隔离绝缘体，减少横向施加于沟道区域的压应力。由此，通过在沟道方向上在沟道区域的两端部分由所述一对SiGe混晶区域施加于沟道区域的压应力，增强了沟道区域在前述横向方向上的扩张。由此，通过参照图1所述的压应力d进一步增强了空穴迁移率的提高。
当结合附图阅读下述具体描述时，本发明的其他目的和进一步的特征将变得显而易见。
附图说明
图1是示出使用SiGe混晶层作为压应力源的半导体器件的原理图；
图2是示出使用SiGe混晶层作为压应力源的的常规半导体器件的构造图；
图3是示出按照本发明实施例的p沟道MOS晶体管的构造平面图；
图4A-4C是以横截面视图示出图3的p沟道MOS晶体管的构造图；
图5是示出图3的p沟道MOS晶体管的特性图；
图6是说明图3的p沟道MOS晶体管另一特点的图；
图7A-7I是示出在图3的p沟道MOS晶体管中器件隔离结构的形成过程图；以及
图8是示出在集成在与图3的p沟道MOS晶体管相同的硅衬底上的n沟道MOS晶体管的构造图。
具体实施方式
图3以平面图示出按照本发明实施例的p沟道MOS晶体管10的整体构造，而图4A和4B以分别沿图3的A-A’和B-B’线所得的横截面视图示出p沟道MOS晶体管10。而且，图4C以沿图3的C-C’线所得的横截面视图示出p沟道MOS晶体管10。
参照图3并且进一步参照图4A-4C，在具有由STI器件隔离结构10I限定的n-型器件区域10A的硅衬底11上形成p沟道MOS晶体管10，其中器件区域10A中包括p沟道MOS晶体管10的沟道区域10CH。而且，器件区域10A相对于周围的器件隔离区域10I向上突出，并且形成一台式结构M，如图3中由粗线所示。
由此，器件隔离结构10I包括在硅衬底11中形成的器件隔离沟槽11T，并且在器件隔离沟槽11T的表面上形成热氧化线性膜11i，其中，经由其中积聚张应力并且形成于热氧化线性膜11i上的SiN线性膜11N，利用CVD氧化膜11CVD填充热氧化线性膜11i内部的空隙。下面将参照后边的实施例详细说明本发明的器件隔离结构10I的特征。
特别地，参照图4C，在沟道区域10CH上经由通常为约1.2nm厚的SiON的栅极绝缘膜12，形成p+型多晶硅栅电极13，并且在与多晶硅栅电极13各侧壁表面相邻的硅衬底11中，形成p型源极和漏极延伸区域10a和10b，从而使得源极和漏极延伸区域10a和10b在沟道方向上排列。
而且，多晶硅栅电极13在其各侧壁表面上承载通常10nm厚的CVD氧化膜13A和13B，其中CVD氧化膜13A和13B继续延伸并覆盖在器件区域10A中露出的硅衬底11的表面。而且，在CVD氧化膜13A和13B各外侧上形成SiN侧壁绝缘膜13C和13D。而且，在与SiN侧壁绝缘膜13C和13D各外边缘相对应的硅衬底11中形成p+型源极和漏极区域10c和10d。
而且，构成器件区域10A的台式结构M在SiN侧壁绝缘膜13C和13D的各外边缘处，被进行干蚀刻工艺与湿蚀刻工艺相结合的蚀刻工艺，使得蚀刻不会超出源极和漏极区域10c和10d之外进行。由此，形成沟槽11TA和11TB，从而使得每个沟槽11TA和11TB由多个Si晶面限定，并且包含于源极区域10c或漏极区域10d之内。
而且，与硅衬底11外延地形成p型SiGe混晶区域11SGA和11SGB，其含有浓度优选为等于或大于20％的Ge，从而使得SiGe混晶区域11SGA和11SGB分别填充沟槽11TA和11TB，并构成源极和漏极区域10c和10d的一部分。应当注意，能够通过低压CVD工艺形成这种SiGe混晶外延区域11SGA和11SGB，该低压CVD工艺在400-550℃的衬底温度下使用SiH4和GeH4气体作为气体源，同时与以1-10Pa的分压提供的HCl蚀刻气体一起，分别以1-10Pa和0.1-10Pa的分压向处理容器提供SiH4气体和GeH4气体。
在图4A-4C的实例中，应当注意，SiGe混晶区域11SGA和11SGB被形成为在向上方向上从硅衬底11和栅极绝缘膜12之间的界面突出至少20nm的距离。
应当注意，这样形成的SiGe混晶区域11SGA和11SGB由晶面限定，其中在栅电极13一侧的侧壁表面由斜面限定，比如Si(111)面形成的斜面，以使得与栅电极侧壁表面的距离在向上方向上增加。而且，SiGe混晶区域11SGA或11SGB与前述倾斜侧壁表面相对的侧壁表面形成为相邻于器件隔离结构10I，并且形成台式结构M的侧壁表面。
尽管这种p型SiGe混晶区域11SGA和11SGB可通过在外延生长之后由离子注入工艺引入p型杂质元素来形成，更优选地，在外延生长时添加含p型元素比如乙硼烷的气体作为掺杂气体。
而且，通过刚好在形成沟槽11TA和11TB之后但是在形成SiGe混晶区域11SGA和11SGB之前形成p+型源极和漏极区域11c和11d，能够防止具有较小带隙的p型SiGe混晶区域11SGA或11SGB与n型Si晶体形成的器件区域10A直接接触，并且能够抑制在p-n结界面处结漏电流的出现。
在栅电极13的上表面上，通过使用金属Ni膜的硅化处理形成镍硅化物膜13S，并且同样通过使用金属Ni膜的硅化处理在p型SiGe混晶区域11SGA和11SGB上形成镍锗硅化物(NiGeSi)层11SGS。
而且，在本实施例中，应当注意形成有压应力膜14，以便覆盖整个p沟道MOS晶体管，如图4A-4C所示。
通过形成这种压应力膜14，构成p+型源极和漏极区域一部分的SiGe混晶区域11SGA和11SGB在沟道区域的两端于硅衬底的平面内沿垂直于沟道方向的方向上经受压应力，如图4B的箭头e所示，结果，SiGe混晶区域11SGA和11SGB形变从而导致在沟道方向上的扩张。
由此，如从图4C的横截面视图所能看到的，SiGe混晶区域11SGA和11SGB各外端基本上由器件隔离结构11I所固定，由此，SiGe混晶区域11SGA和11SGB的这种形变使得主要在沟道区域10CH中产生压应力。由此，参照图1所述的压应力d被进一步增强。
优选地，这种压应力膜14积聚绝对值等于或大于1.5GPa的应力，同时应当注意，这种压应力膜14例如可通过这样来形成：在250Pa的气压下在400℃的衬底温度下，同时分别以600SCCM和1400SCCM的流速供应SiH4和NH3作为气体源而形成80nm厚的SiN膜。
另一方面，参照图4B，请注意这种压应力膜14当形成在相对于衬底表面构成一角度的表面上时，比如SiGe混晶区域11SGA或11SGB的侧壁表面上时，会起到朝着硅衬底11向下挤压SiGe混晶区域11SGA或11SGB的作用。
当这种情况发生时，SiGe混晶区域11SGA或11SGB的扩张(其相应地导致沟道区域中产生压应力，参照图1所述(见图4B中的箭头c))被抑制或减小，结果，在沟道方向施加于沟道区域的水平压应力d的大小被减少。
由此，通过该实施例，表现出膨胀趋向的张应力膜15局部地形成于与衬底表面构成一角度的表面上，从而使得作用在此表面上的压应力膜14的压应力至少被部分抵消掉。应当注意，也在栅电极13侧壁表面的侧壁绝缘膜13A和13B的外侧上形成这种张应力膜。
由此，成功避免了这样的问题：通过压应力膜14的压应力，栅电极13从上方挤压沟道区域10CH，导致在图1的水平方向上作用的压应力d的大小减少。
优选地，这种张应力膜14在其中积聚大小等于或大于1GPa的应力，其中这种张应力膜15例如可通过如下方式来形成：在3×104Pa的气压下在500℃的衬底温度下，同时使用流速分别为200SCCM和700SCCM的SiH4和NH3作为气体源来形成100nm厚的SiN膜，之后对其进行回蚀刻处理。
作为前述构造的结果，达到0.9GPa大小的压应力在沟道方向上被施加于沟道区域10CH，并且由此，p沟道MOS晶体管单位栅极宽度的饱和电流从600μA/μm的值(对应没有设置这种压应力膜14和张应力膜15的情况)增加到640μa/μm的值。
另一方面，在张应力膜15的厚度增加至超过80nm的情况下，会出现如图5所示的排出(drain-off)电流增大。这里，应当注意图5示出栅极长度和栅极宽度分别设为40nm和500nm、具有50nm厚并且积聚1.0GPa的压应力的SiN膜被用作压应力膜14以及积聚1.5GPa的张应力的SiN膜被用作张应力膜15的情况下，排出电流和漏极饱和电流之间的关系，其中张应力膜15的厚度进行各种变化。
从图5可以得出：张应力膜15的厚度优选地设定为等于或小于80nm。
图6是示出p沟道MOS晶体管10的构造的另一图，其中应当注意，图6对应于图4B的横截面。而且，图6中的“原始Si表面水平面”代表图4C中的硅衬底11和栅极绝缘膜12之间的界面A。
参照图6，构成图3的台式结构M一部分的SiGe混晶区域11SGA或11SGB利用形成的沟槽11TA或11TB从低于界面A的水平面B开始生长深度DSiGe，其中该生长继续到超过前述界面A的高度U。由此，优选地设定高度U超过20nm，以便按照参照图1所述的机制，以足够大的大小向沟道区域10CH施加压应力d。而且，尽管在本实施例中器件隔离结构10I被形成为比界面A低深度DSTI_1的水平面，优选地，深度DSTI_1满足关系DSiGe＜DSTI_1，使得器件隔离结构10I中的CVD氧化膜11CVD的高度不会超过水平面B。
通过设置这样的位置关系，能够避免在Ni金属膜被沉积在SiGe混晶11SGA或11SGB上用于形成硅化物膜11SGS的情况下、由Ni金属膜中的Ni原子导致经由SiGe混晶区域11SGA或11SGB深入扩散到构成器件隔离结构10I的热氧化膜11i所产生的器件隔离特性恶化的问题。
而且，在本实施例中，应当注意构成器件隔离结构10I的SiN膜11N的上部、在沟道区域10CH右部和左部具有增大的膜厚，如图4A的横截面图中用圆环所示。
参照图4A，应当注意，在图4A的横截面图中、在垂直于图平面的方向上，通过位于图4A的平面上方和下方的SiGe混晶区域11SGA和11SGB施加压应力。现在，为了利用这样的压应力有效增大沟道区域中的空穴迁移率，有必要使得Si晶体对应于沟道区域10CH在图4A平面内的横向方向上发生形变。
另一方面，在位于沟道区域10CH右侧和左侧的器件隔离结构10I中，通过高密度等离子体CVD工艺形成的CVD氧化膜11CVD在其中积聚压应力，并且作为结果，沟道区域10CH经受来自位于沟道区域10CH右侧和左侧的器件隔离结构10I的压应力，以抵抗其所需的形变。
尽管由CVD氧化膜11CVD所导致的这种压应力可通过在SiN膜11N(形成于器件隔离结构10I中)中积聚反作用张应力在某种程度上被抵消，但是本实施例通过局部增大位于沟道区域10CH横向边缘处(如图4A中的圆环)的SiN膜11N的厚度，能够抑制由CVD氧化膜11CVD所引起的这种不需要的压应力。
图7A-7I是示出本发明的p沟道MOS晶体管10的制造工艺(包括器件隔离结构10I的形成步骤)的图，其中图7A-7F和图7H表示图3的A-A’横截面，而图7G和7I表示图3的B-B’横截面。
参照图7A，通过干蚀刻工艺同时使用在硅衬底11上经由热氧化膜11OX1形成的SiN膜11SN1作为掩模，在硅衬底11中对应于待形成器件隔离结构10I之处，形成第一浅器件隔离沟槽11T1，并且在去除SiN膜11SN1和热氧化膜11OX1之后，在图7B的步骤中形成新的热氧化膜11OX2和新的SiN膜11SN2，其中在图7B的步骤中，通过回蚀刻SiN膜11SN2和下面的热氧化膜11OX2在器件隔离沟槽11T1中形成自对准开口11To。
而且，在图7C的步骤中，在使用SiN膜11SN2作为掩模的同时，硅衬底11在前述开口11To中被进行干蚀刻工艺，并且在第一器件隔离沟槽11T1中形成第二器件隔离沟槽11T2，从而使得第二器件隔离沟槽11T2延伸到硅衬底11中。由此，第一和第二器件隔离沟槽11T1和11T2构成器件隔离沟槽11T。
而且，在图7C的步骤中，在这样形成的器件隔离沟槽11T的表面上形成热氧化膜11i和CVDSiN膜11N，并且CVD氧化膜11CVD通过高密度等离子体CVD工艺被沉积在SiN膜11N上。而且，CVD氧化膜11CVD被图案化，使得CVD氧化膜11CVD除了其填充器件隔离沟槽11T的部分，从硅衬底11的表面被去除。
而且，在图7D的步骤中，SiN膜11SN2和热氧化膜11OX2通过CMP工艺被去除，并且CVD氧化膜11CVD被平坦化。而且，在新露出的硅衬底11表面上形成高质量SiON栅极绝缘膜12。
而且，在图7E的步骤中，在栅极绝缘膜12上沉积多晶硅膜，并且作为图案化此多晶硅膜的结果，形成多晶硅栅电极13。
而且，在图7F的步骤中，在多晶硅栅电极13的侧壁表面上形成CVD氧化膜的侧壁绝缘膜13A和13B(未示出)，并且通过沉积和回蚀刻工艺进一步在其上形成CVD SiN膜的侧壁绝缘膜13C和13D。通过这种侧壁绝缘膜的形成，能够看出在CVD氧化膜11CVD的表面上产生凹陷。
而且，在图7G的步骤中，通过结合干蚀刻工艺和湿蚀刻工艺的蚀刻工艺，在硅衬底11中待形成源极和漏极区域10c和10d的部分中，形成沟槽11TA和11TB，并且由此，硅衬底的水平面从图6的水平面A降低到水平面B。
而且，在通过离子注入工艺形成源极和漏极区域10c和10d之后，按照前面所述的条件进行SiGe混晶层的外延生长，并且由此，SiGe混晶区域11SGA和11SGB分别外延形成在沟槽11TA和11TB中。
而且，在同时进行的图7H和7I的步骤中，在多晶硅栅电极13上且在SiGe混晶区域11SGA和11SGB上沉积Ni金属膜，并且在多晶硅栅电极13上形成硅化物膜13S，以及通过使得Ni金属膜与下面的多晶硅或SiGe混晶产生反应在SiGe混晶区域11SGA和11SGB上形成NiGeSi层11SGS。
通过这样形成的p沟道MOS晶体管，能够看出在其中积聚张应力的SiN膜11N的厚度在形成于沟道区域10CH左侧和右侧的器件隔离结构10I中、对应于其与沟道区域10CH相邻的部分而局部增大，并且通过CVD氧化膜11CVD施加于沟道区域10CH的压应力被减少。
图8示出与图4A-4C的p沟道MOS晶体管一起形成于相同的硅衬底11上的n沟道MOS晶体管20的构造。
参照图8，n沟道MOS晶体管形成于硅衬底11中由器件隔离结构10I限定的p-型器件区域10B中，并且包括：与SiON栅极绝缘膜12相同并且形成于对应于器件区域10B中的沟道区域的硅衬底上的SiON栅极绝缘膜22，以及形成于栅极绝缘膜22上的n+型多晶硅栅电极23，其中在器件区域10B中的沟道区域横向两侧的硅衬底11中形成n型源极和漏极延伸区域21a和21b。
而且，多晶硅栅电极23具有由与CVD氧化膜13A和13B相同的CVD氧化膜23A和23B覆盖的各侧壁表面，并且与SiN侧壁绝缘膜13C和13D相同的SiN绝缘膜23C和23D形成于CVD氧化膜23A和23B的各外侧。
而且，n+型源极和漏极区域21c和21d形成在SiN侧壁绝缘膜23C和23D的各外侧、对应于器件区域10B的硅衬底11中，其中通过硅化工艺在源极和漏极区域21c和21d的各表面上形成硅化物膜21SC。而且，硅化物膜21SC还形成于多晶硅栅电极13上。
而且，图12的n沟道MOS晶体管20在其整个表面上形成有张应力膜15(与图4A-4C的p沟道MOS晶体管10一起使用)，并且由此，双轴张应力被施加于栅电极正下方的沟道区域。由此，相比没有施加这种应力的情况相比，提高了n沟道MOS晶体管的运行速度。
由此，在制造于共同的硅衬底上承载图4A-4C的p沟道MOS晶体管10和n沟道MOS晶体管20的半导体集成电路的情况下，在器件区域10A和10B上形成各器件结构之后在硅衬底11上均匀地沉积张应力膜15，已经形成n沟道MOS晶体管20的区域被抗蚀掩模覆盖，之后进行回蚀刻工艺。由此，在n沟道MOS晶体管区域上、进一步在p沟道MOS晶体管的区域中与衬底表面形成一角度的表面上，留下张应力膜15。
而且，在这样的结构上均匀地沉积压应力膜14，之后进行去除工艺，用以从n沟道MOS晶体管的区域去除压应力膜。由此，仅在p沟道MOS晶体管上留下压应力膜14。
通过这样的工艺，能够在共同的衬底上制造含有p沟道MOS晶体管和n沟道MOS晶体管的半导体集成电路，其中通过施加各个应力，每个晶体管中的运行速度得到提高，而不会使其制造工艺复杂。
而且，本发明不仅限于这里所述的实施例，而是在不脱离本发明的范围之内可进行各种变化和改型。

Claims (10)

1.一种半导体器件，其特征在于：
硅衬底，具有由器件隔离区域限定的器件区域，并且在所述器件区域中包括沟道区域；
栅电极，经由栅极绝缘膜形成在与所述沟道区域对应的所述硅衬底上，所述栅电极在其一对相对的侧壁表面上分别承载一对侧壁绝缘膜；
P型源极和漏极延伸区域，跨越所述沟道区域形成在所述栅电极各横向侧的所述硅衬底中；
P型源极和漏极区域，与所述源极延伸区域和所述漏极延伸区域连续地分别形成在所述侧壁绝缘膜各外侧的所述硅衬底中；以及
一对SiGe混晶区域，形成在所述侧壁绝缘膜各外侧的所述硅衬底中且与所述硅衬底为外延关系，以便分别被所述源极区域和所述漏极区域围绕；
每个所述SiGe混晶区域生长到所述栅极绝缘膜和所述硅衬底之间的栅极绝缘膜界面的水平面之上的水平面；
其中，在所述一对SiGe混晶区域的各上表面上设置压应力膜。
2.如权利要求1所述的半导体器件，其中每个所述SiGe混晶区域生长到比所述栅极绝缘膜界面高20nm或20nm以上的水平面。
3.如权利要求1或2所述的半导体器件，其中每个所述SiGe混晶区域在其侧壁表面上承载张应力膜。
4.如权利要求3所述的半导体器件，其中所述张应力膜具有等于或小于80nm的厚度。
5.如权利要求3所述的半导体器件，其中所述张应力膜积聚等于或大于1GPa的张应力。
6.如权利要求1或2所述的半导体器件，其中所述压应力膜积聚等于或大于1.5GPa的压应力。
7.如权利要求1或2所述的半导体器件，其中形成所述一对SiGe混晶区域，从而在包含所述源极区域和所述漏极区域的横截面图中，所述一对SiGe混晶区域的底边缘位于构成所述器件隔离区域的器件隔离绝缘体的上水平面。
8.如权利要求1或2所述的半导体器件，其中所述器件隔离区域形成STI隔离结构，其包括形成在所述硅衬底中的器件隔离沟槽和填充所述器件隔离沟槽的器件隔离绝缘体，所述器件隔离沟槽在其内表面上承载其中积聚张应力的张应力膜，所述张应力膜在所述沟道区域两端部分处与所述张应力膜的其他区域相比，具有增加的膜厚。
9.如权利要求1或2所述的半导体器件，其中所述压应力膜包含氮和氧。
10.如权利要求1或2所述的半导体器件，其中在所述硅衬底上形成n沟道MOS晶体管，所述n沟道MOS晶体管完全被张应力膜覆盖。
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