CN1956214A - 场效应晶体管及其制造方法 - Google Patents

场效应晶体管及其制造方法 Download PDF

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CN1956214A
CN1956214A CNA2006101412470A CN200610141247A CN1956214A CN 1956214 A CN1956214 A CN 1956214A CN A2006101412470 A CNA2006101412470 A CN A2006101412470A CN 200610141247 A CN200610141247 A CN 200610141247A CN 1956214 A CN1956214 A CN 1956214A
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fet
semiconductor
mosfet
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high mobility
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朱慧珑
程慷果
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International Business Machines Corp
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Abstract

本发明提供了一种场效应晶体管(FET)，包括源极侧半导体；漏极侧半导体；和栅极。源极侧半导体由高迁移率半导体材料构成，并且漏极侧半导体由低泄漏半导体材料构成。在一个实施例中，FET是金属氧化物半导体场效应晶体管(MOSFET)。本发明还提供了用于制造该FET的方法。

Description

场效应晶体管及其制造方法
技术领域
本发明涉及半导体器件。更具体地说，本发明涉及金属氧化物半导体场效应晶体管。
背景技术
当MOSFET(金属氧化物半导体场效应晶体管)晶体管的尺寸缩小时，它们一直面临挑战。即使取得了将MOSFET沟道的长度缩短到约25nm的进步，迁移率始终是关键参数。同样，在沟道中电荷的传输仍旧远离轨道，所以当电子或空穴从源极向漏极转移时会发现电子或空穴的散射。这是因为尺寸缩小通过增加沟道掺杂(晕圈掺杂)和垂直电场降低了迁移率。当栅极长度缩的越来越小时，短沟道效应变得更明显并且功耗增加。
为了提高MOSFET器件的性能，可以在MOSFET的沟道中使用锗(Ge)或硅锗(SiGe)作为半导体材料。然而，虽然Ge或SiGe场效应晶体管(FET)表现出高性能或电子和/或空穴的高迁移率，但是这样的FET还表现出高的结泄漏，该泄漏增加VLSL和计算机芯片的支持功率。因此，当支持功耗保持很高时很难提高器件性能。
发明内容
本发明的一个目的是提供在小尺度下具有提高的特性的场效应晶体管(FET)。
本发明的另一个目的是提供在小尺度下具有高迁移率的FET晶体管。
本发明的再一个目的是提供具有减小的短沟道效应和减小的功耗的FET晶体管。
本发明的另一个目的是提供制造在小尺度下具有高迁移率，减小的短沟道效应和减小的功耗的FET晶体管的方法。
通过包括源极侧半导体，漏极侧半导体和栅极的场效应晶体管(FET)获得本发明的这些和其它目的和优点。源极侧半导体由高迁移率半导体材料构成，并且漏极侧半导体由低泄漏半导体材料构成。在一个实施例中，FET是金属氧化物半导体场效应晶体管(MOSFET)。本发明还提供了用于制造该FET的方法
附图说明
图1是本发明的MOSFET的实施例的截面图。
图2A是制造本发明的MOSFET的实施例的方法的第一步的截面图。
图2B是制造本发明的MOSFET的实施例的方法的第二步的截面图。
图2C是制造本发明的MOSFET的实施例的方法的第三步的截面图。
图2D是制造本发明的MOSFET的实施例的方法的第四步的截面图。
图2E是制造本发明的MOSFET的实施例的方法的第五步的截面图。
图2F是制造本发明的MOSFET的实施例的方法的第六步的截面图。
图2G是制造本发明的MOSFET的实施例的方法的第七步的截面图。
图2H是制造本发明的MOSFET的实施例的方法的第八步的截面图。
图2I是制造本发明的MOSFET的实施例的方法的第九步的截面图。
图2J是制造本发明的MOSFET的实施例的方法的第十步的截面图。
图2K是制造本发明的MOSFET的实施例的方法的第十一步的截面图。
图2L是制造本发明的MOSFET的实施例的方法的第十二步的截面图。
图2M是制造本发明的MOSFET的实施例的方法的第十三步的截面图。
图2N是根据图2A-2M中示出的方法制造的MOSFET的截面图。
图3是本发明的MOSFET的另一个实施例的截面图。
具体实施方式
参考附图，特别是图1，其提供了本发明的场效应晶体管(FET)的第一实施例，通常由标号100标记。优选该FET为金属氧化物半导体场效应晶体管(MOSFET)。然而，该FET还可以是金属绝缘体半导体场效应晶体管。该FET晶体管可以是n型FET晶体管或p型FET晶体管。在另一个实施例中，该FET是不对称FET。
在另一个实施例中，FET晶体管是短沟道MOSFET晶体管。在优选实施例中，短沟道MOSFET具有的沟道长度优选在约5nm到100nm之间。
再参考图1，MOSFET 100包括绝缘体105，源极110，漏极115和栅极120。栅极120包括栅极导体125，栅极介质130和栅极绝缘体135。MOSFET 100还包括沟道区域190，沟道区域进一步包括第一沟道部分191和第二沟道部分192。第一沟道部分191位于栅极120下的源极110区域中，第二沟道部分192位于栅极120下的漏极115区域中。
绝缘体105和栅极绝缘体135由公知用于半导体器件的任何合适的绝缘材料构成，如氮化物和氧化物。绝缘体105可以是包括例如Ge，SiGe，SiGeC，Ge合金，GaAs，InAs，InP和绝缘体上半导体层的任何合适的材料。栅极导体125由如金属或多晶硅(多晶Si)的合适的导体材料构成。栅极介质130优选由合适的介质材料构成，包括如SiO2，HfO2，ZrO2，Al2O3，TiO2，La2O3，SrTiO3，LaAlO3的氧化物或其任何组合。在另一个实施例中，栅极介质130的介电常数优选比二氧化硅的高5到40倍。
在一个实施例中，源极110和第一沟道部分191由具有高迁移率特性的半导体材料构成。这样的材料包括硅锗(SiGe)和锗(Ge)，当与如硅的其它半导体材料比较时，这两者都表现出高的电子迁移率。在另一个实施例中，源极110由具有约10％到约50％的锗的SiGe构成。可以用如SiGeC，Ge合金，GaAs，InAs，InP和其它III-V族或II-VI化合物半导体的其它高迁移率半导体材料制造源极110。
在另一个实施例中，源极110由电子迁移率为纯硅的1.1到2倍的材料构成。
在另一个实施例中，漏极115和第二沟道部分192由具有低泄漏特性的半导体材料构成。这样的材料包括硅(Si)和碳化硅(SiC)，这两者都表现出穿过栅极介质130的低电流泄漏。适合于制造漏极115的其它材料包括GaAs，InAs，InP以及其它III-V族或II-VI化合物半导体。
参考图2A-2N，在绝缘体上硅(SOI)衬底240上制造类似于MOSFET100的MOSFET 200，如图2A所示。SOI衬底240包括具有二氧化硅(SiO2)薄层即掩埋氧化物205掩埋其中的硅层。在掩埋氧化物205顶上的硅层215上制造MOSFET 100。
图2A-2M中示出了制造MOSFET 200利用的方法。图2N中示出了完成后的MOSFET 200，其在结构上类似于MOSFET 100。
参考图2A，在SOI衬底240上首先沉积氧化物层245，并且在氧化物层245上沉积氮化物层250。在一个实施例中，氧化物层245具有约5nm到约10nm的沉积厚度，并且氮化物层250具有约100nm到约150nm的沉积厚度。
参考图2B，在氮化物层250上施加光致抗蚀剂掩膜255，并且移除一部分氮化物层250。可以通过反应离子蚀刻(RIE)完成氮化物层250的移除。参考图2C，沉积氧化物并随后通过如RIE蚀刻，以在氮化物层250的侧壁上形成氧化物隔离物260。
参考图2D，用锗(Ge)掺杂硅层215的一部分，优选通过倾斜Ge注入，以形成Ge掺杂区域265。可以如下执行倾斜Ge注入，注入能量在约10KeV到约80KeV之间，剂量在约2e14和约5e15原子/cm∧2之间，与法线的倾角在约20度和约60度之间。参考图2E，通过沉积和蚀刻形成氮化物隔离物270。优选，氮化物隔离物270的沉积厚度约70nm。
参考图2F，从硅层215蚀刻掉Ge掺杂区域265。参考图2G，在形成漏极层215的硅层215的暴露部分上沉积高迁移率半导体材料层即源极层210，以形成源极210和第一沟道部分291。在一个实施例中，源极层210是SiGe层，其具有比在此实施例由硅构成的漏极层215更高的迁移率。在另一个实施例中，在漏极层215上外延生长源极层210。
参考图2H，通过蚀刻蚀刻掉即移除氧化物隔离物260。参考图2I，在源极层210，氮化物隔离物270，漏极层215和氮化物层250上沉积介质层275。介质层将形成栅极220的一部分(参见图2N)。
参考图2J，在介质层275上沉积导电层280，并且填充在氮化物隔离物270和氮化物层250之间的间隙。优选，导电层280是金属或多晶硅(多晶Si)层。优选，对具有n型沟道的场效应晶体管(nFET)多晶硅材料为n型掺杂，对具有p型沟道的场效应晶体管(pFET)为p型掺杂。参考图2K，部分蚀刻掉导电层280以为栅极220形成栅极导体225(参见图2N)。
参考图2L，蚀刻掉氮化物隔离物270，氮化物层250和部分介质层275。参考图2M，通过蚀刻移除氧化物层245。同样，蚀刻掉介质层275另外的部分以形成栅极介质230。
参考图2N，通过增加绝缘体235完成MOSFET 200。因此，MOSFET200包括用作衬底的掩埋氧化物205，源极210，漏极215和栅极220。栅极220包括导体225，介质230和绝缘体235。优选，绝缘体235由氮化物构成，还可以使用其它材料。
MOSFET 200还包括沟道区域290，沟道区域进一步包括第一沟道部分291和第二沟道部分292。第一沟道部分291位于栅极220下的源极210区域中，第二沟道部分292位于栅极220下的漏极215区域中。
可以通过任何合适的工艺完成形成绝缘体235的最后步骤。例如，可以使用常规工艺以形成绝缘体235，通过沉积氮化物层并且采用各向异性RIE以形成氮化物隔离物。在一个实施例中，利用倾斜晕圈注入。其它的工艺可以包括延伸注入，氮化物隔离物形成，源极/漏极注入，和SD RTA以激活器件中的掺杂剂。
可以采用对制造半导体器件合适的任何已知方式完成上述如氧化物层245和氮化物层250的不同层的沉积。合适的沉积技术的例子包括化学气相沉积(CVD)，等离子体增强CVD(PECVD)和高密度等离子体沉积(HDP)。另外，可以通过任何合适的已知方法完成上述对不同层的蚀刻。在一个实施例中，通过反应离子蚀刻技术完成蚀刻。
参考图3，在一个实施例中，在如硅衬底的体晶片上制造MOSFET300。MOSFET 300包括源极310，漏极315和栅极320。栅极320包括栅极导体325，栅极介质330和栅极绝缘体335。
MOSFET 300还包括沟道区域390，沟道区域进一步包括第一沟道部分391和第二沟道部分392。第一沟道部分391位于栅极320下的源极310区域中，第二沟道部分392位于栅极320下的漏极315区域中。
在一个实施例中，源极310和第一沟道部分391由具有高迁移率特性的半导体材料构成，如硅锗(SiGe)和锗，Ge。漏极315和第二沟道部分392由具有低泄漏特性的半导体材料构成。
提供本发明的MOSFET器件的典型实施例以说明本发明的多个方面。本发明不局限于上述MOSFET晶体管。结构如尺寸和栅极，源极和漏极的位置的变化，落入本发明的范围内。
当与现有的MOSFET器件比较时，本发明的MOSFET器件表现出较好的特性。当MOSFET的几何尺寸减小时更明显。例如，本发明的MOSFET器件表现出较好的迁移率特性，减小的短沟道效应和减小的功耗。本发明的MOSFET器件的另外的优点包括减小电流通过p-n结的泄漏，以及减小阈下泄漏。阈下泄漏的减小还对减小器件的功耗有贡献。
例如，即使将MOSFET沟道的长度减小到接近或等于25nm，本发明的MOSFET器件仍表现出高的迁移率。这是因为尺寸缩小通过增加沟道掺杂(晕圈掺杂)和垂直电场降低迁移率。当栅极长度缩的越来越小时，短沟道效应和功耗变的更明显。
应该明白，本领域的技术人员可以对这里提供的描述进行各种变化，组合和修正。本发明旨在包括落入附加权利要求范围内的所有这样的变化，修正和改变。

Claims (20)

1.一种场效应晶体管(FET)，包括：
源极半导体，具有沟道的第一部分；
漏极半导体，具有所述沟道的第二部分；以及
栅极，
其中所述源极半导体由高迁移率半导体材料构成，并且其中所述漏极半导体由低泄漏半导体材料构成。
2.根据权利要求1的FET，其中所述FET选自：金属氧化物半导体场效应晶体管，金属绝缘体半导体场效应晶体管及其组合。
3.根据权利要求1的FET，其中所述高迁移率半导体材料选自：Ge，SiGe，SiGeC，Ge合金，GaAs，InAs，InP，III-V族化合物半导体，和II-VI化合物半导体。
4.根据权利要求3的FET，其中所述高迁移率半导体材料具有约10％到约50％的Ge。
5.根据权利要求1的FET，其中所述低泄漏半导体材料选自：Si，SiC，GaAs，InAs，InP，III-V族化合物半导体，和II-VI化合物半导体。
6.根据权利要求1的FET，其中所述FET是短沟道MOSFET。
7.根据权利要求6的FET，其中所述短沟道MOSFET的沟道长度在约5nm到约100nm之间。
8.根据权利要求1的FET，其中所述FET在衬底上形成，所述衬底选自：Ge，SiGe，SiGeC，Ge合金，GaAs，InAs，InP和绝缘体上半导体的半导体衬底。
9.根据权利要求1的FET，其中所述FET选自：n型FET和p型FET。
10.根据权利要求1的FET，其中所述FET是不对称FET。
11.一种制造场效应晶体管(FET)的方法，包括如下步骤：
形成具有沟道的第一部分的漏极半导体；
形成具有沟道的第二部分的源极半导体；以及
形成与所述漏极半导体和所述源极半导体相邻的栅极，
其中所述源极半导体由高迁移率半导体材料构成，并且其中所述漏极半导体由低泄漏半导体材料构成。
12.根据权利要求11的方法，其中所述FET选自：金属氧化物半导体场效应晶体管(MOSFET)，金属绝缘体半导体场效应晶体管及其组合。
13.根据权利要求11的方法，其中所述高迁移率半导体材料选自：Ge，SiGe，SiGeC，Ge合金，GaAs，InAs，InP，III-V族化合物半导体，和II-VI化合物半导体。
14.根据权利要求13的方法，其中所述高迁移率半导体材料具有约10％到约50％的Ge。
15.根据权利要求11的方法，其中所述低泄漏半导体材料选自：Si，SiC，GaAs，InAs，InP，III-V族化合物半导体，和II-VI化合物半导体。
16.根据权利要求11的方法，其中所述FET是短沟道MOSFET。
17.根据权利要求16的方法，其中所述短沟道MOSFET的沟道长度在约5nm到约100nm之间。
18.根据权利要求11的方法，其中所述FET在衬底上形成，所述衬底选自：硅衬底和绝缘体上硅衬底。
19.根据权利要求11的方法，其中所述FET选自：n型FET和p型FET。
20.根据权利要求11的方法，其中所述FET是不对称FET。
CNA2006101412470A 2005-10-26 2006-09-29 场效应晶体管及其制造方法 Pending CN1956214A (zh)

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