JP4633706B2 - 電子回路及び電子回路を動作するための方法 - Google Patents
電子回路及び電子回路を動作するための方法 Download PDFInfo
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- JP4633706B2 JP4633706B2 JP2006300257A JP2006300257A JP4633706B2 JP 4633706 B2 JP4633706 B2 JP 4633706B2 JP 2006300257 A JP2006300257 A JP 2006300257A JP 2006300257 A JP2006300257 A JP 2006300257A JP 4633706 B2 JP4633706 B2 JP 4633706B2
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- pll circuit
- pll1
- pll2
- signal
- input
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- 238000000034 method Methods 0.000 title claims description 4
- 101100381996 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) BRO1 gene Proteins 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims 1
- 101100350613 Arabidopsis thaliana PLL1 gene Proteins 0.000 description 17
- 101100082028 Arabidopsis thaliana PLL2 gene Proteins 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
- H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
Claims (4)
- 電子回路であって、該電子回路に、
第1の位相比較器(PC1)および第1の制御可能な発振器(VCO1)を有する第1のPLL回路(PLL1)と、
第2の位相比較器(PC2)および第2の制御可能な発振器(VCO2)を有する第2のPLL回路(PLL2)とが設けられており、
前記第1の制御可能な発振器(VCO1)は、前記第2の制御可能な発振器(VCO2)の引き込みレンジよりも小さい引き込みレンジを有しており、
入力信号(IN)は、前記第1のPLL回路(PLL1)の入力端に供給され、
第1のスイッチ(S1)が、前記第1のPLL回路(PLL1)または前記第2のPLL回路(PLL2)の出力端を該第1のPLL回路(PLL1)のさらに別の入力端に選択的に接続するために設けられており、
第2のスイッチ(S2)が、前記入力信号(IN)または前記第1のPLL回路(PLL1)の出力信号を、選択的に前記第2のPLL回路(PLL2)の入力端に供給するために設けられており、
ロック検出器(LD)が設けられており、前記ロック検出器(LD)は、前記入力信号(IN)が前記第1の制御可能な発振器(VCO1)の出力信号に対してロックしていることを検出し、
前記入力信号(IN)が、前記第1の制御可能な発振器(VCO1)の出力信号に対してロックされた場合には、前記ロック検出器は、前記第1のPLL回路(PLL1)の出力信号が前記第2のPLL回路(PLL2)の入力端に供給され、かつ、前記第2のPLL回路(PLL2)の出力信号が前記第1のPLL回路(PLL1)の入力端に供給されるように、前記第1のスイッチ(S1)および前記第2のスイッチ(S2)を制御し、
前記第2のPLL回路(PLL2)の出力端は、前記第2のPLL回路(PLL)の位相比較器の入力端に接続されており、前記第2のPLL回路(PLL2)の出力が、回路の唯一の出力であること
を特徴とする電子回路。 - 前記第1のPLL回路(PLL1)は、さらに第1のフィルタ(LPF1)を有しており、および/または前記第2のPLL回路(PLL2)は、さらに第2のフィルタ(LPF2)を有していることを特徴とする請求項1に記載の電子回路。
- 分周器(D1)が、入力端子(IN)と前記第1の位相比較器(PC1)との間に設けられており、
分周器(D2)が、前記第1の制御可能な発振器(VCO1)の出力端と前記第1のスイッチ(S1)および第2のスイッチ(S2)のそれぞれの入力端との間に設けられており、ならびに/または
分周器(D3)が、前記第2の制御可能な発振器(VCO2)と、第2の位相比較器(PC2)および第1のスイッチ(S1)のそれぞれの入力端との間に設けられていること
を特徴とする請求項1に記載の電子回路。 - 入力信号(IN)を第1のPLL回路(PLL1)の入力端に供給するステップと、
第2のスイッチ(S2)を介して入力信号(IN)を第2のPLL回路(PLL2)の位相比較器の入力端に供給するステップと、
第2のPLL回路(PLL2)の第2の制御可能な発振器(VCO2)の信号を、第2のPLL回路(PLL2)の第2の位相比較器(PC2)のさらに別の入力端にフィードバックするステップと、
第1のPLL回路(PLL1)の第1の制御可能な発振器(VCO1)の信号を、第1のスイッチ(S1)を介して第1のPLL回路(PLL1)の第1の位相比較器(PC1)のさらに別の入力端にフィードバックするステップと、
入力信号(IN)に関して、前記第1のPLL回路(PLL1)のロック状態をロック検出器(LD)で監視するステップと
を備えており、さらに前記方法は、
前記第1のPLL回路(PLL1)が入力信号(IN)にロックされた場合に、第2のスイッチ(S2)を制御して前記第1のPLL回路(PLL1)の出力信号を前記第2のPLL回路(PLL2)の位相比較器の入力端に供給し、かつ、第1のスイッチ(S1)を制御して前記第2のPLL回路(PLL2)の出力信号を前記第1のPLL回路(PLL1)のさらに別の入力端に供給するステップ
を備えることを特徴とする請求項1乃至3いずれかに記載の電子回路を動作させる方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05110472A EP1783913A1 (en) | 2005-11-08 | 2005-11-08 | Switchable PLL circuit including two loops |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007135208A JP2007135208A (ja) | 2007-05-31 |
JP4633706B2 true JP4633706B2 (ja) | 2011-02-16 |
Family
ID=35453452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006300257A Active JP4633706B2 (ja) | 2005-11-08 | 2006-11-06 | 電子回路及び電子回路を動作するための方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7576576B2 (ja) |
EP (1) | EP1783913A1 (ja) |
JP (1) | JP4633706B2 (ja) |
KR (1) | KR101295657B1 (ja) |
CN (1) | CN1964195B (ja) |
DE (1) | DE602006008246D1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7791422B2 (en) * | 2007-10-17 | 2010-09-07 | Autoliv Asp, Inc. | Voltage controlled oscillator with cascaded emitter follower buffer stages |
US7642822B2 (en) * | 2008-04-03 | 2010-01-05 | Tektronix, Inc. | Analog phase-locked loop |
KR101196706B1 (ko) * | 2009-10-29 | 2012-11-07 | 에스케이하이닉스 주식회사 | 지연 고정 루프 회로를 포함하는 반도체 집적 회로 |
JP5688905B2 (ja) * | 2010-01-26 | 2015-03-25 | 古野電気株式会社 | 基準周波数発生装置 |
JP5016074B2 (ja) * | 2010-02-16 | 2012-09-05 | 日本電波工業株式会社 | Pll回路 |
US8681917B2 (en) | 2010-03-31 | 2014-03-25 | Andrew Llc | Synchronous transfer of streaming data in a distributed antenna system |
US8058916B2 (en) * | 2010-04-15 | 2011-11-15 | Xilinx, Inc. | Lockstep synchronization and maintenance |
TWI443492B (zh) * | 2010-05-17 | 2014-07-01 | Mstar Semiconductor Inc | 時脈產生電路與時脈產生方法 |
CN102545892B (zh) * | 2012-01-18 | 2015-03-11 | 上海华力微电子有限公司 | 一种宽频带锁相环频率综合器电路 |
US8666010B1 (en) * | 2012-09-24 | 2014-03-04 | Xilinx, Inc. | Phase detector for bursty data streams |
WO2014146274A1 (en) * | 2013-03-21 | 2014-09-25 | Telefonaktiebolaget L M Ericsson (Publ) | Method and apparatus for implementing clock holdover |
KR101467547B1 (ko) * | 2013-08-30 | 2014-12-01 | 포항공과대학교 산학협력단 | 주입 고정식 디지털 주파수 신시사이저 회로 |
US9350362B2 (en) | 2013-10-08 | 2016-05-24 | Thomas & Betts International, Llc | Programmable slew rate phase locked loop |
CN106301358B (zh) * | 2015-05-28 | 2019-01-01 | 瑞昱半导体股份有限公司 | 快速锁定的时脉数据回复装置与其方法 |
US10116313B2 (en) * | 2015-08-25 | 2018-10-30 | Intel Corporation | Apparatus and method to mitigate phase and frequency modulation due to inductive coupling |
US10965295B1 (en) * | 2020-05-07 | 2021-03-30 | Shenzhen GOODIX Technology Co., Ltd. | Integer boundary spur mitigation for fractional PLL frequency synthesizers |
US11212072B1 (en) | 2020-12-22 | 2021-12-28 | Xilinx, Inc. | Circuit for and method of processing a data stream |
CN113114231A (zh) * | 2021-05-24 | 2021-07-13 | 浙江赛思电子科技有限公司 | 一种时钟控制电路 |
Citations (3)
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JPH07235873A (ja) * | 1993-10-23 | 1995-09-05 | Alcatel Sel Ag | クロック発生用回路装置 |
JP2003264537A (ja) * | 2002-03-11 | 2003-09-19 | Nef:Kk | Plo制御回路 |
JP2003347938A (ja) * | 2002-05-30 | 2003-12-05 | Yokogawa Electric Corp | Pll回路 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US5184350A (en) * | 1991-04-17 | 1993-02-02 | Raytheon Company | Telephone communication system having an enhanced timing circuit |
EP0560525B1 (en) * | 1992-03-11 | 1997-10-15 | Matsushita Electric Industrial Co., Ltd. | Frequency synthesizer |
JP2710214B2 (ja) * | 1994-08-12 | 1998-02-10 | 日本電気株式会社 | フェーズロックドループ回路 |
JP2944607B2 (ja) * | 1998-02-12 | 1999-09-06 | 日本電気アイシーマイコンシステム株式会社 | ディジタルpll回路とクロックの生成方法 |
US6204732B1 (en) * | 1999-02-09 | 2001-03-20 | Eci Telecom Ltd | Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units |
US6114987A (en) * | 1999-05-29 | 2000-09-05 | Sensor Technologies & Systems, Inc. | Dual-loop linearizer for FM-CW radar |
JP4502165B2 (ja) * | 2001-04-10 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | ロック検出回路 |
US6839860B2 (en) * | 2001-04-19 | 2005-01-04 | Mircon Technology, Inc. | Capture clock generator using master and slave delay locked loops |
US20060001494A1 (en) * | 2004-07-02 | 2006-01-05 | Bruno Garlepp | Cascaded locked-loop circuits deriving high-frequency, low noise clock signals from a jittery, low-frequency reference |
-
2005
- 2005-11-08 EP EP05110472A patent/EP1783913A1/en not_active Withdrawn
-
2006
- 2006-10-09 DE DE602006008246T patent/DE602006008246D1/de active Active
- 2006-11-03 KR KR1020060108462A patent/KR101295657B1/ko active IP Right Grant
- 2006-11-06 JP JP2006300257A patent/JP4633706B2/ja active Active
- 2006-11-07 US US11/593,738 patent/US7576576B2/en active Active
- 2006-11-08 CN CN2006101445027A patent/CN1964195B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07235873A (ja) * | 1993-10-23 | 1995-09-05 | Alcatel Sel Ag | クロック発生用回路装置 |
JP2003264537A (ja) * | 2002-03-11 | 2003-09-19 | Nef:Kk | Plo制御回路 |
JP2003347938A (ja) * | 2002-05-30 | 2003-12-05 | Yokogawa Electric Corp | Pll回路 |
Also Published As
Publication number | Publication date |
---|---|
KR20070049566A (ko) | 2007-05-11 |
EP1783913A1 (en) | 2007-05-09 |
CN1964195B (zh) | 2011-04-06 |
DE602006008246D1 (de) | 2009-09-17 |
CN1964195A (zh) | 2007-05-16 |
KR101295657B1 (ko) | 2013-08-13 |
JP2007135208A (ja) | 2007-05-31 |
US7576576B2 (en) | 2009-08-18 |
US20070103214A1 (en) | 2007-05-10 |
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