DE602006008246D1 - Schaltbarer PLL Schaltkreis mit zwei Loops - Google Patents

Schaltbarer PLL Schaltkreis mit zwei Loops

Info

Publication number
DE602006008246D1
DE602006008246D1 DE602006008246T DE602006008246T DE602006008246D1 DE 602006008246 D1 DE602006008246 D1 DE 602006008246D1 DE 602006008246 T DE602006008246 T DE 602006008246T DE 602006008246 T DE602006008246 T DE 602006008246T DE 602006008246 D1 DE602006008246 D1 DE 602006008246D1
Authority
DE
Germany
Prior art keywords
switchable
loops
pll circuit
pll
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006008246T
Other languages
English (en)
Inventor
Ralf-Detlef Schaefer
Michael Drexler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of DE602006008246D1 publication Critical patent/DE602006008246D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
DE602006008246T 2005-11-08 2006-10-09 Schaltbarer PLL Schaltkreis mit zwei Loops Active DE602006008246D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05110472A EP1783913A1 (de) 2005-11-08 2005-11-08 Schaltbarer PLL Schaltkreis mit zwei Loops

Publications (1)

Publication Number Publication Date
DE602006008246D1 true DE602006008246D1 (de) 2009-09-17

Family

ID=35453452

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006008246T Active DE602006008246D1 (de) 2005-11-08 2006-10-09 Schaltbarer PLL Schaltkreis mit zwei Loops

Country Status (6)

Country Link
US (1) US7576576B2 (de)
EP (1) EP1783913A1 (de)
JP (1) JP4633706B2 (de)
KR (1) KR101295657B1 (de)
CN (1) CN1964195B (de)
DE (1) DE602006008246D1 (de)

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US7791422B2 (en) * 2007-10-17 2010-09-07 Autoliv Asp, Inc. Voltage controlled oscillator with cascaded emitter follower buffer stages
US7642822B2 (en) * 2008-04-03 2010-01-05 Tektronix, Inc. Analog phase-locked loop
KR101196706B1 (ko) * 2009-10-29 2012-11-07 에스케이하이닉스 주식회사 지연 고정 루프 회로를 포함하는 반도체 집적 회로
JP5688905B2 (ja) * 2010-01-26 2015-03-25 古野電気株式会社 基準周波数発生装置
JP5016074B2 (ja) * 2010-02-16 2012-09-05 日本電波工業株式会社 Ｐｌｌ回路
US8681917B2 (en) * 2010-03-31 2014-03-25 Andrew Llc Synchronous transfer of streaming data in a distributed antenna system
US8058916B2 (en) * 2010-04-15 2011-11-15 Xilinx, Inc. Lockstep synchronization and maintenance
TWI443492B (zh) * 2010-05-17 2014-07-01 Mstar Semiconductor Inc 時脈產生電路與時脈產生方法
CN102545892B (zh) * 2012-01-18 2015-03-11 上海华力微电子有限公司 一种宽频带锁相环频率综合器电路
US8666010B1 (en) * 2012-09-24 2014-03-04 Xilinx, Inc. Phase detector for bursty data streams
US9660797B2 (en) 2013-03-21 2017-05-23 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for implementing clock holdover
KR101467547B1 (ko) * 2013-08-30 2014-12-01 포항공과대학교 산학협력단 주입 고정식 디지털 주파수 신시사이저 회로
US9350362B2 (en) 2013-10-08 2016-05-24 Thomas & Betts International, Llc Programmable slew rate phase locked loop
CN106301358B (zh) * 2015-05-28 2019-01-01 瑞昱半导体股份有限公司 快速锁定的时脉数据回复装置与其方法
US10116313B2 (en) * 2015-08-25 2018-10-30 Intel Corporation Apparatus and method to mitigate phase and frequency modulation due to inductive coupling
US10965295B1 (en) 2020-05-07 2021-03-30 Shenzhen GOODIX Technology Co., Ltd. Integer boundary spur mitigation for fractional PLL frequency synthesizers
US11212072B1 (en) 2020-12-22 2021-12-28 Xilinx, Inc. Circuit for and method of processing a data stream
CN113114231A (zh) * 2021-05-24 2021-07-13 浙江赛思电子科技有限公司 一种时钟控制电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184350A (en) * 1991-04-17 1993-02-02 Raytheon Company Telephone communication system having an enhanced timing circuit
DE69314519T2 (de) * 1992-03-11 1998-02-19 Matsushita Electric Ind Co Ltd Frequenzsynthetisierer
DE4336239A1 (de) * 1993-10-23 1995-04-27 Sel Alcatel Ag Schaltungsanordnung für einen Taktgenerator
JP2710214B2 (ja) * 1994-08-12 1998-02-10 日本電気株式会社 フェーズロックドループ回路
JP2944607B2 (ja) * 1998-02-12 1999-09-06 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路とクロックの生成方法
US6204732B1 (en) * 1999-02-09 2001-03-20 Eci Telecom Ltd Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units
US6114987A (en) * 1999-05-29 2000-09-05 Sensor Technologies & Systems, Inc. Dual-loop linearizer for FM-CW radar
JP4502165B2 (ja) * 2001-04-10 2010-07-14 ルネサスエレクトロニクス株式会社 ロック検出回路
US6839860B2 (en) * 2001-04-19 2005-01-04 Mircon Technology, Inc. Capture clock generator using master and slave delay locked loops
JP2003264537A (ja) * 2002-03-11 2003-09-19 Nef:Kk Ｐｌｏ制御回路
JP2003347938A (ja) * 2002-05-30 2003-12-05 Yokogawa Electric Corp Ｐｌｌ回路
US20060001494A1 (en) * 2004-07-02 2006-01-05 Bruno Garlepp Cascaded locked-loop circuits deriving high-frequency, low noise clock signals from a jittery, low-frequency reference

Also Published As

Publication number Publication date
CN1964195B (zh) 2011-04-06
JP4633706B2 (ja) 2011-02-16
US20070103214A1 (en) 2007-05-10
US7576576B2 (en) 2009-08-18
JP2007135208A (ja) 2007-05-31
CN1964195A (zh) 2007-05-16
EP1783913A1 (de) 2007-05-09
KR101295657B1 (ko) 2013-08-13
KR20070049566A (ko) 2007-05-11

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Legal Events

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8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition