DE602005012029D1 - Unsymmetrische Schaltung mit geschalteten Kapazitäten - Google Patents

Unsymmetrische Schaltung mit geschalteten Kapazitäten

Info

Publication number
DE602005012029D1
DE602005012029D1 DE602005012029T DE602005012029T DE602005012029D1 DE 602005012029 D1 DE602005012029 D1 DE 602005012029D1 DE 602005012029 T DE602005012029 T DE 602005012029T DE 602005012029 T DE602005012029 T DE 602005012029T DE 602005012029 D1 DE602005012029 D1 DE 602005012029D1
Authority
DE
Germany
Prior art keywords
unbalanced circuit
switched capacities
capacities
switched
unbalanced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602005012029T
Other languages
English (en)
Inventor
Johann G Gaboriau
Joseph J Weiser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Publication of DE602005012029D1 publication Critical patent/DE602005012029D1/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Amplifiers (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
DE602005012029T 2004-09-10 2005-08-05 Unsymmetrische Schaltung mit geschalteten Kapazitäten Expired - Fee Related DE602005012029D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/938,002 US7477079B2 (en) 2004-09-10 2004-09-10 Single ended switched capacitor circuit

Publications (1)

Publication Number Publication Date
DE602005012029D1 true DE602005012029D1 (de) 2009-02-12

Family

ID=35219363

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005012029T Expired - Fee Related DE602005012029D1 (de) 2004-09-10 2005-08-05 Unsymmetrische Schaltung mit geschalteten Kapazitäten

Country Status (4)

Country Link
US (1) US7477079B2 (de)
EP (1) EP1635468B1 (de)
JP (1) JP2006081165A (de)
DE (1) DE602005012029D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7570181B2 (en) * 2006-06-09 2009-08-04 Cosmic Circuits Private Limited Method and system for input voltage droop compensation in video/graphics front-ends
JP4803735B2 (ja) * 2006-09-14 2011-10-26 ルネサスエレクトロニクス株式会社 Ａ／ｄ変換器およびそれを使用した受信装置
US20100117687A1 (en) * 2008-11-07 2010-05-13 Nuvoton Technology Corporation Track and hold circuits for audio systems and oeprational methods thereof
US7973570B2 (en) * 2008-12-30 2011-07-05 Freescale Semiconductor, Inc. Sample-and-hold (S/H) circuit
US7843232B2 (en) * 2009-02-27 2010-11-30 Atmel Corporation Dual mode, single ended to fully differential converter structure
US8415985B2 (en) * 2011-07-11 2013-04-09 Texas Instruments Incorporated Circuits and methods for sampling and holding differential input signals
WO2013111252A1 (ja) 2012-01-24 2013-08-01 旭化成エレクトロニクス株式会社 サンプリング回路、ａ／ｄ変換器、ｄ／ａ変換器、ｃｏｄｅｃ
US8823564B2 (en) 2012-03-07 2014-09-02 Asahi Kasei Microdevices Corporation Sampling circuit, A/D converter, D/A converter, and codec
US20130322142A1 (en) * 2012-05-31 2013-12-05 General Electric Company Multilevel power converter
JP6009653B2 (ja) * 2013-03-28 2016-10-19 旭化成エレクトロニクス株式会社 デジタル−アナログ変換器及びデジタル−アナログ変換装置
KR102204388B1 (ko) 2014-01-09 2021-01-18 삼성전자주식회사 필터링 특성이 개선된 기준 전압 생성기
KR102423987B1 (ko) * 2017-09-21 2022-07-22 삼성전자주식회사 터미네이션 회로 및 인터페이스 장치
US10333529B1 (en) 2018-08-24 2019-06-25 Semiconductor Components Industries, Llc Method of forming a conversion circuit and structure therefor

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3337241B2 (ja) * 1991-07-26 2002-10-21 テキサス インスツルメンツ インコーポレイテツド 改良型多重チャンネル・センサーインターフェース回路とその製造方法
US5363102A (en) * 1993-03-26 1994-11-08 Analog Devices, Inc. Offset-insensitive switched-capacitor gain stage
US5376936A (en) * 1993-06-16 1994-12-27 Crystal Semiconductor Corporation One-bit switched-capacitor D/A circuit with continuous time linearity
CA2152497C (en) * 1993-11-09 1999-01-12 Lawrence Edwin Connell Method and apparatus for detecting an input signal level
US5479130A (en) * 1994-02-15 1995-12-26 Analog Devices, Inc. Auto-zero switched-capacitor integrator
EP0678980B1 (de) * 1994-04-21 1999-08-04 STMicroelectronics S.r.l. Verzerrungsarme Schaltung mit geschalteten Kapazitäten
JP3852721B2 (ja) * 1997-07-31 2006-12-06 旭化成マイクロシステム株式会社 Ｄ／ａ変換器およびデルタシグマ型ｄ／ａ変換器
US6031399A (en) * 1998-02-13 2000-02-29 National Semiconductor Corporation Selectively configurable analog signal sampler
US6194946B1 (en) * 1998-05-07 2001-02-27 Burr-Brown Corporation Method and circuit for compensating the non-linearity of capacitors
US6147522A (en) * 1998-12-31 2000-11-14 Cirrus Logic, Inc. Reference voltage circuitry for use in switched-capacitor applications
US6351506B1 (en) * 1999-04-19 2002-02-26 National Semiconductor Corporation Switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop
JP4861566B2 (ja) * 2001-05-08 2012-01-25 富士通セミコンダクター株式会社 スイッチド・キャパシタ・フィルタ回路
US6433712B1 (en) * 2001-07-25 2002-08-13 Texas Instruments Incorporated Offset error compensation of input signals in analog-to-digital converter
US6628217B1 (en) * 2001-07-27 2003-09-30 Cypress Semiconductor Corp. Signal scaling scheme for a delta sigma modulator
US6617908B1 (en) * 2002-03-22 2003-09-09 Cirrus Logic, Inc. Switched-capacitor circuits with reduced distortion
JP3920123B2 (ja) 2002-03-25 2007-05-30 旭化成マイクロシステム株式会社 Ｄ／ａ変換器及びデルタシグマ型ｄ／ａ変換器
US6573850B1 (en) * 2002-05-24 2003-06-03 Wolfson Microelectronics Limited Digital-to-analogue converter circuits

Also Published As

Publication number Publication date
JP2006081165A (ja) 2006-03-23
EP1635468B1 (de) 2008-12-31
US7477079B2 (en) 2009-01-13
US20060055436A1 (en) 2006-03-16
EP1635468A1 (de) 2006-03-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee