JP4506990B2 - セラミック多層基板 - Google Patents
セラミック多層基板 Download PDFInfo
- Publication number
- JP4506990B2 JP4506990B2 JP2006529412A JP2006529412A JP4506990B2 JP 4506990 B2 JP4506990 B2 JP 4506990B2 JP 2006529412 A JP2006529412 A JP 2006529412A JP 2006529412 A JP2006529412 A JP 2006529412A JP 4506990 B2 JP4506990 B2 JP 4506990B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- ceramic
- multilayer substrate
- ceramic multilayer
- deformation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
10a 主面(第2の主面)
10b 主面(第1の主面)
11 本体
11a 底板部
11b キャビティ周囲部
12 キャビティ
13 面内導体(導体パターン)
14 ビアホール導体(導体パターン)
15 変形防止パターン
16 層間接続導体パターン
17 接続導体
18a,18b 端子電極(導体パターン)
20 セラミック多層基板
20b 主面(第1の主面)
22 キャビティ
26a,26b 表面パターン(変形防止パターン)
28 端子電極(導体パターン)
50,60,70 表面実装部品
100 底板部
114 変形防止パターン
116,116a,116b 層間接続導体パターン
124 変形防止パターン
126,126a,126b 層間接続導体パターン
134 変形防止パターン
136 接続導体
162 キャビティ
200 底板部
214,214a,214b,214c グランドパターン(変形防止パターン)
216,218 信号パターン(変形防止パターン)
226,226a,226b,226c 層間接続導体パターン
234,236 グランドパターン(変形防止パターン)
Claims (11)
- 積層された複数のセラミック層と、
少なくとも1つの前記セラミック層に配置された少なくとも一つの導体パターンとを備え、
少なくとも第1の主面にキャビティが形成されたセラミック多層基板であって、
前記キャビティを形成する開口を有する少なくとも2つの前記セラミック層に、それぞれ、前記開口の周りの一周の一部のみに沿って、前記第1の主面の法線方向から透視したときに異なる位置に配置された、前記導体パターンと同一材料からなる変形防止パターンを備え、
前記変形防止パターンは、全体として、前記第1の主面の法線方向から透視したときに前記開口の周りの一周を囲むように配置されていることを特徴とする、セラミック多層基板。 - 前記変形防止パターンは、前記開口を有する前記セラミック層に、前記開口の周りの一周の方向に間隔を設けて複数のパターン要素が配置された分割パターンを含むことを特徴とする、請求項1に記載のセラミック多層基板。
- 前記開口は矩形であり、
前記変形防止パターンは、前記開口を有する前記セラミック層に、前記開口の少なくとも1つの辺に沿って延在する帯状パターンを含むことを特徴とする、請求項1に記載のセラミック多層基板。 - 前記キャビティの開口の形状は正方形であり、
前記第1の主面は、長辺および短辺を有する長方形であり、
前記第1の主面には、前記キャビティの前記開口と前記第1の主面の前記短辺との間に、前記導体パターンである端子電極と、少なくとも一つの前記変形防止パターンとが配置され、
前記少なくとも一つの変形防止パターンは、前記端子電極よりも、面積が大きいことを特徴とする、請求項1〜3のいずれか一つに記載のセラミック多層基板。 - 前記開口を有する複数の前記セラミック層の主面にそれぞれ配置された複数の前記変形防止パターンと、
前記導体パターンと同一材料からなり、前記セラミック層を貫通し、前記複数の前記変形防止パターンを接続する、層間接続導体パターンとを備えたことを特徴とする、請求項1〜4のいずれか一つに記載のセラミック多層基板。 - 前記層間接続導体パターンを複数備え、
前記複数の層間接続導体パターンは、前記第1の主面の法線方向から透視したときに平行な少なくとも2列に交互にずらして配置されていることを特徴とする、請求項5に記載のセラミック多層基板。 - 前記変形防止パターンが、前記導体パターンのグランド電位になる部分に電気的に接続されたグランドパターンを含むことを特徴とする、請求項1〜6のいずれか一つに記載のセラミック多層基板。
- 前記第1の主面に、当該セラミック多層基板を回路基板に接続するための端子を有することを特徴とする、請求項1〜7のいずれか一つに記載のセラミック多層基板。
- 前記第1の主面に形成された前記キャビティ内に、第1の表面実装部品が実装され、
前記第1の主面とは反対側の第2の主面に、第2の表面実装部品が実装されることを特徴とする、請求項8に記載のセラミック多層基板。 - 前記第1の主面に、前記キャビティに沿って配置された、前記導体パターンと同一材料からなる表面パターンを備えたことを特徴とする、請求項1〜9に記載のセラミック多層基板。
- 前記セラミック層は、低温焼成セラミック材料によって構成され、
前記導体パターン及び前記変形防止パターンは、銀または銅を主成分とする材料によって構成されることを特徴とする、請求項1〜10のいずれか一つに記載のセラミック多層基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005140442 | 2005-05-12 | ||
JP2005140442 | 2005-05-12 | ||
PCT/JP2006/307590 WO2006120826A1 (ja) | 2005-05-12 | 2006-04-10 | セラミック多層基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2006120826A1 JPWO2006120826A1 (ja) | 2008-12-18 |
JP4506990B2 true JP4506990B2 (ja) | 2010-07-21 |
Family
ID=37396342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006529412A Expired - Fee Related JP4506990B2 (ja) | 2005-05-12 | 2006-04-10 | セラミック多層基板 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7745734B2 (ja) |
EP (1) | EP1881751B1 (ja) |
JP (1) | JP4506990B2 (ja) |
KR (1) | KR20070083505A (ja) |
CN (1) | CN100553413C (ja) |
WO (1) | WO2006120826A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2017082017A1 (ja) * | 2015-11-11 | 2018-08-02 | 株式会社村田製作所 | コイルアンテナ、コイル実装基板、記録媒体および電子機器 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4993739B2 (ja) | 2007-12-06 | 2012-08-08 | 新光電気工業株式会社 | 配線基板、その製造方法及び電子部品装置 |
TWI458400B (zh) * | 2008-10-31 | 2014-10-21 | Taiyo Yuden Kk | Printed circuit board and manufacturing method thereof |
JP5382225B2 (ja) * | 2010-07-29 | 2014-01-08 | 株式会社村田製作所 | セラミック多層基板およびその製造方法 |
US9414501B2 (en) | 2012-01-04 | 2016-08-09 | Board Of Regents, The University Of Texas System | Method for connecting inter-layer conductors and components in 3D structures |
US10518490B2 (en) | 2013-03-14 | 2019-12-31 | Board Of Regents, The University Of Texas System | Methods and systems for embedding filaments in 3D structures, structural components, and structural electronic, electromagnetic and electromechanical components/devices |
US10748867B2 (en) * | 2012-01-04 | 2020-08-18 | Board Of Regents, The University Of Texas System | Extrusion-based additive manufacturing system for 3D structural electronic, electromagnetic and electromechanical components/devices |
US9908037B2 (en) | 2013-07-11 | 2018-03-06 | Board Of Regents, The University Of Texas System | Electronic gaming die |
CN107079592B (zh) * | 2014-09-30 | 2019-06-18 | 株式会社村田制作所 | 多层基板 |
US9724897B2 (en) * | 2015-01-07 | 2017-08-08 | Emisense Technologies, Llc | Processing method for constraining lower melting point metals within ceramic laminates during sintering |
CN107615893B (zh) * | 2015-06-25 | 2019-11-05 | 京瓷株式会社 | 布线基板、电子装置以及电子模块 |
JP6573515B2 (ja) * | 2015-09-25 | 2019-09-11 | 日本特殊陶業株式会社 | セラミック基板 |
JP6737646B2 (ja) * | 2016-06-24 | 2020-08-12 | 京セラ株式会社 | 配線基板、電子装置および電子モジュール |
JP6490255B1 (ja) * | 2018-01-16 | 2019-03-27 | 三菱電機株式会社 | 車載電子装置 |
US10856411B2 (en) * | 2018-06-29 | 2020-12-01 | Dell Products, L.P. | System and method for design of high speed signaling and power delivery |
JP7044169B2 (ja) * | 2018-09-25 | 2022-03-30 | 株式会社村田製作所 | ワイヤレス受電回路モジュール |
KR20210101764A (ko) * | 2020-02-11 | 2021-08-19 | 삼성전자주식회사 | 인쇄회로기판 조립체 및 이를 포함하는 전자 장치 |
CN111599690A (zh) * | 2020-05-27 | 2020-08-28 | 上海芯波电子科技有限公司 | 一种基于wb芯片与fc芯片共存的双面挖腔陶瓷封装工艺 |
US20220216171A1 (en) * | 2021-01-06 | 2022-07-07 | Huawei Technologies Co., Ltd. | Chip package structure, preparation method, and electronic device |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288841A (en) | 1979-09-20 | 1981-09-08 | Bell Telephone Laboratories, Incorporated | Double cavity semiconductor chip carrier |
US4705917A (en) * | 1985-08-27 | 1987-11-10 | Hughes Aircraft Company | Microelectronic package |
JPH05243700A (ja) | 1992-03-03 | 1993-09-21 | Fujitsu Ltd | 多層セラミック回路基板の製造方法 |
JPH06252558A (ja) * | 1993-03-01 | 1994-09-09 | Oki Electric Ind Co Ltd | 多層ガラスセラミックキャビティ基板 |
EP0658937A1 (en) * | 1993-12-08 | 1995-06-21 | Hughes Aircraft Company | Vertical IC chip stack with discrete chip carriers formed from dielectric tape |
US5798909A (en) * | 1995-02-15 | 1998-08-25 | International Business Machines Corporation | Single-tiered organic chip carriers for wire bond-type chips |
JP3725949B2 (ja) | 1996-12-05 | 2005-12-14 | 日本特殊陶業株式会社 | 半導体素子収納用基体とその製造方法 |
JP3470852B2 (ja) * | 1996-12-25 | 2003-11-25 | 日本特殊陶業株式会社 | 配線基板とその製造方法 |
JP3508905B2 (ja) | 1997-04-15 | 2004-03-22 | 日本特殊陶業株式会社 | 配線基板とその製造方法 |
JP2001284808A (ja) * | 2000-03-31 | 2001-10-12 | Kyocera Corp | 積層回路基板 |
JP4524876B2 (ja) | 2000-07-12 | 2010-08-18 | 日立金属株式会社 | 導電性ペーストおよび多層セラミック基板 |
JP3757788B2 (ja) * | 2000-11-27 | 2006-03-22 | 株式会社村田製作所 | 多層セラミック基板およびその製造方法 |
JP2003060106A (ja) | 2001-08-21 | 2003-02-28 | Matsushita Electric Ind Co Ltd | 積層セラミックパッケージおよびこれを用いた電子部品 |
JP2003224222A (ja) * | 2001-11-26 | 2003-08-08 | Kyocera Corp | 半導体素子収納用パッケージ |
JP4099756B2 (ja) * | 2002-08-07 | 2008-06-11 | 日立金属株式会社 | 積層基板 |
JP2004095767A (ja) * | 2002-08-30 | 2004-03-25 | Murata Mfg Co Ltd | セラミック多層基板およびその製造方法 |
JP2004165247A (ja) | 2002-11-11 | 2004-06-10 | Matsushita Electric Ind Co Ltd | 多層セラミック基板、その製造方法、通信用デバイスおよびそれを用いた通信機器 |
JP4543374B2 (ja) * | 2004-07-05 | 2010-09-15 | 日立金属株式会社 | 積層基板およびその製造方法 |
JP4565381B2 (ja) * | 2004-07-29 | 2010-10-20 | 日立金属株式会社 | 積層基板 |
-
2006
- 2006-04-10 EP EP06731537.4A patent/EP1881751B1/en not_active Not-in-force
- 2006-04-10 CN CNB2006800007451A patent/CN100553413C/zh not_active Expired - Fee Related
- 2006-04-10 WO PCT/JP2006/307590 patent/WO2006120826A1/ja active Application Filing
- 2006-04-10 JP JP2006529412A patent/JP4506990B2/ja not_active Expired - Fee Related
- 2006-04-10 KR KR1020077004345A patent/KR20070083505A/ko not_active Application Discontinuation
-
2007
- 2007-04-23 US US11/738,637 patent/US7745734B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2017082017A1 (ja) * | 2015-11-11 | 2018-08-02 | 株式会社村田製作所 | コイルアンテナ、コイル実装基板、記録媒体および電子機器 |
Also Published As
Publication number | Publication date |
---|---|
US7745734B2 (en) | 2010-06-29 |
US20070187137A1 (en) | 2007-08-16 |
JPWO2006120826A1 (ja) | 2008-12-18 |
WO2006120826A1 (ja) | 2006-11-16 |
KR20070083505A (ko) | 2007-08-24 |
CN100553413C (zh) | 2009-10-21 |
EP1881751B1 (en) | 2014-06-04 |
CN101010996A (zh) | 2007-08-01 |
EP1881751A1 (en) | 2008-01-23 |
EP1881751A4 (en) | 2009-07-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4506990B2 (ja) | セラミック多層基板 | |
US7703198B2 (en) | Method of manufacturing capacitor-embedded low temperature co-fired ceramic substrate | |
US7573697B2 (en) | Method of manufacturing capacitor for incorporation in wiring board, capacitor for incorporation in wiring board, and wiring board | |
US7649252B2 (en) | Ceramic multilayer substrate | |
JP4965237B2 (ja) | 配線基板内蔵用コンデンサ及び配線基板 | |
JP5842859B2 (ja) | 多層配線基板およびこれを備えるモジュール | |
JP4746422B2 (ja) | コンデンサの製造方法及びコンデンサ | |
JPH10308584A (ja) | セラミック多層基板およびその製造方法 | |
JP5207854B2 (ja) | 部品内蔵セラミックス基板およびその製造方法 | |
JP4565381B2 (ja) | 積層基板 | |
JP4653033B2 (ja) | 配線基板 | |
JP3540941B2 (ja) | 積層体およびその製造方法 | |
JP5838978B2 (ja) | セラミック積層部品 | |
JP3909285B2 (ja) | 配線基板 | |
JP2005322744A (ja) | セラミック多層基板およびその製造方法 | |
JP2004165343A (ja) | 積層型セラミック電子部品およびその製造方法 | |
JP4254540B2 (ja) | 多層セラミック基板および複合電子部品 | |
JP3940659B2 (ja) | 多層回路基板の製造方法 | |
JP2007103908A (ja) | 配線基板内蔵用コンデンサの製造方法、配線基板内蔵用コンデンサ、及び配線基板 | |
JP2006032469A (ja) | 多層セラミック基板 | |
JP2005285993A (ja) | 表面実装型多連コンデンサ | |
JPH08186382A (ja) | 積層電子部品 | |
JP2007242859A (ja) | セラミック多層基板 | |
JP2010010164A (ja) | 容量内蔵基板 | |
KR20070098051A (ko) | 세라믹 다층기판 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090716 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090904 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20091104 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100202 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20100217 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100407 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100420 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4506990 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140514 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |