JP4398225B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4398225B2 JP4398225B2 JP2003376415A JP2003376415A JP4398225B2 JP 4398225 B2 JP4398225 B2 JP 4398225B2 JP 2003376415 A JP2003376415 A JP 2003376415A JP 2003376415 A JP2003376415 A JP 2003376415A JP 4398225 B2 JP4398225 B2 JP 4398225B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- main surface
- electrodes
- wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003376415A JP4398225B2 (ja) | 2003-11-06 | 2003-11-06 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003376415A JP4398225B2 (ja) | 2003-11-06 | 2003-11-06 | 半導体装置 |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009025463A Division JP4839384B2 (ja) | 2009-02-06 | 2009-02-06 | 半導体装置の製造方法 |
| JP2009111869A Division JP2009200519A (ja) | 2009-05-01 | 2009-05-01 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005142312A JP2005142312A (ja) | 2005-06-02 |
| JP2005142312A5 JP2005142312A5 (https=) | 2006-12-21 |
| JP4398225B2 true JP4398225B2 (ja) | 2010-01-13 |
Family
ID=34687463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003376415A Expired - Fee Related JP4398225B2 (ja) | 2003-11-06 | 2003-11-06 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4398225B2 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4571679B2 (ja) * | 2008-01-18 | 2010-10-27 | Okiセミコンダクタ株式会社 | 半導体装置 |
| WO2020211272A1 (en) * | 2019-04-15 | 2020-10-22 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
| CN114005760A (zh) * | 2021-11-05 | 2022-02-01 | 苏州群策科技有限公司 | 一种半导体封装基板的制备方法 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09199630A (ja) * | 1996-01-19 | 1997-07-31 | Toshiba Corp | 多層配線基板 |
| JP2000114412A (ja) * | 1998-10-06 | 2000-04-21 | Shinko Electric Ind Co Ltd | 回路基板の製造方法 |
| JP2001284783A (ja) * | 2000-03-30 | 2001-10-12 | Shinko Electric Ind Co Ltd | 表面実装用基板及び表面実装構造 |
| JP3871853B2 (ja) * | 2000-05-26 | 2007-01-24 | 株式会社ルネサステクノロジ | 半導体装置及びその動作方法 |
| JP2002026174A (ja) * | 2000-07-11 | 2002-01-25 | Shinko Electric Ind Co Ltd | 回路基板の製造方法 |
| JP4465884B2 (ja) * | 2001-01-22 | 2010-05-26 | ソニー株式会社 | 半導体装置およびその製造方法 |
| JP2002343818A (ja) * | 2001-05-14 | 2002-11-29 | Shinko Electric Ind Co Ltd | Bga型配線基板及びその製造方法並びに半導体装置の製造方法 |
| JP4012375B2 (ja) * | 2001-05-31 | 2007-11-21 | 株式会社ルネサステクノロジ | 配線基板およびその製造方法 |
| CN100407422C (zh) * | 2001-06-07 | 2008-07-30 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
| JP3500132B2 (ja) * | 2001-06-15 | 2004-02-23 | 日本アビオニクス株式会社 | フリップチップ実装方法 |
| JP2003007902A (ja) * | 2001-06-21 | 2003-01-10 | Shinko Electric Ind Co Ltd | 電子部品の実装基板及び実装構造 |
| JP2003086735A (ja) * | 2001-06-27 | 2003-03-20 | Shinko Electric Ind Co Ltd | 位置情報付配線基板及びその製造方法並びに半導体装置の製造方法 |
| JP2003234451A (ja) * | 2002-02-06 | 2003-08-22 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
-
2003
- 2003-11-06 JP JP2003376415A patent/JP4398225B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005142312A (ja) | 2005-06-02 |
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