JP4260617B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4260617B2
JP4260617B2 JP2003426943A JP2003426943A JP4260617B2 JP 4260617 B2 JP4260617 B2 JP 4260617B2 JP 2003426943 A JP2003426943 A JP 2003426943A JP 2003426943 A JP2003426943 A JP 2003426943A JP 4260617 B2 JP4260617 B2 JP 4260617B2
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Japan
Prior art keywords
semiconductor chip
semiconductor
back surface
chip
manufacturing
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Expired - Fee Related
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JP2003426943A
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English (en)
Japanese (ja)
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JP2005191053A5 (enExample
JP2005191053A (ja
Inventor
順弘 木下
順平 紺野
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2003426943A priority Critical patent/JP4260617B2/ja
Priority to TW093135102A priority patent/TWI381459B/zh
Priority to KR1020040106950A priority patent/KR20050065318A/ko
Priority to US11/017,077 priority patent/US20050140023A1/en
Priority to CNB2004101048860A priority patent/CN100477208C/zh
Publication of JP2005191053A publication Critical patent/JP2005191053A/ja
Priority to US11/648,646 priority patent/US7598121B2/en
Publication of JP2005191053A5 publication Critical patent/JP2005191053A5/ja
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Publication of JP4260617B2 publication Critical patent/JP4260617B2/ja
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    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
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    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
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    • H10W72/07231—Techniques
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    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
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    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/531—Shapes of wire connectors
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    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/00—Package configurations
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2003426943A 2003-12-24 2003-12-24 半導体装置の製造方法 Expired - Fee Related JP4260617B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2003426943A JP4260617B2 (ja) 2003-12-24 2003-12-24 半導体装置の製造方法
TW093135102A TWI381459B (zh) 2003-12-24 2004-11-16 Semiconductor device and manufacturing method thereof
KR1020040106950A KR20050065318A (ko) 2003-12-24 2004-12-16 반도체장치 및 그 제조 방법
US11/017,077 US20050140023A1 (en) 2003-12-24 2004-12-21 Method of manufacturing a semiconductor device
CNB2004101048860A CN100477208C (zh) 2003-12-24 2004-12-24 制造半导体器件的方法
US11/648,646 US7598121B2 (en) 2003-12-24 2007-01-03 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003426943A JP4260617B2 (ja) 2003-12-24 2003-12-24 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2005191053A JP2005191053A (ja) 2005-07-14
JP2005191053A5 JP2005191053A5 (enExample) 2007-01-25
JP4260617B2 true JP4260617B2 (ja) 2009-04-30

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JP2003426943A Expired - Fee Related JP4260617B2 (ja) 2003-12-24 2003-12-24 半導体装置の製造方法

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US (2) US20050140023A1 (enExample)
JP (1) JP4260617B2 (enExample)
KR (1) KR20050065318A (enExample)
CN (1) CN100477208C (enExample)
TW (1) TWI381459B (enExample)

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TW200522293A (en) * 2003-10-01 2005-07-01 Koninkl Philips Electronics Nv Electrical shielding in stacked dies by using conductive die attach adhesive
JP4538830B2 (ja) * 2004-03-30 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置
JP2006261485A (ja) * 2005-03-18 2006-09-28 Renesas Technology Corp 半導体装置およびその製造方法
KR20070095504A (ko) * 2005-10-14 2007-10-01 인티그런트 테크놀로지즈(주) 적층형 집적회로 칩 및 패키지.
US7750482B2 (en) * 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US7993971B2 (en) * 2007-12-28 2011-08-09 Freescale Semiconductor, Inc. Forming a 3-D semiconductor die structure with an intermetallic formation
US20090289101A1 (en) * 2008-05-23 2009-11-26 Yong Du Method for ball grid array (bga) solder attach for surface mount
KR20100109243A (ko) * 2009-03-31 2010-10-08 삼성전자주식회사 반도체 패키지
US8617926B2 (en) 2010-09-09 2013-12-31 Advanced Micro Devices, Inc. Semiconductor chip device with polymeric filler trench
JP2012221989A (ja) 2011-04-04 2012-11-12 Elpida Memory Inc 半導体装置製造装置、及び半導体装置の製造方法
JP6100489B2 (ja) 2012-08-31 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
EP2897166A4 (en) 2012-09-14 2016-06-29 Renesas Electronics Corp METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT
CN103107108B (zh) * 2012-12-12 2015-04-22 贵州振华风光半导体有限公司 改善厚膜混合集成电路同质键合系统质量一致性的方法
KR102066015B1 (ko) 2013-08-13 2020-01-14 삼성전자주식회사 반도체 패키지 및 이의 제조방법
JP2017059707A (ja) * 2015-09-17 2017-03-23 富士通株式会社 積層チップ、積層チップを搭載する基板、及び積層チップの製造方法
JP6639915B2 (ja) * 2016-01-08 2020-02-05 東レエンジニアリング株式会社 半導体実装装置および半導体実装方法
KR102592226B1 (ko) * 2018-07-17 2023-10-23 삼성전자주식회사 반도체 패키지 본딩헤드 및 본딩방법
JP2020136642A (ja) * 2019-02-26 2020-08-31 京セラ株式会社 半導体チップ、圧電デバイス及び電子機器
CN114496824B (zh) * 2020-10-23 2024-08-23 长鑫存储技术有限公司 裸片取出方法
US20240164008A1 (en) * 2022-11-11 2024-05-16 Industrial Technology Research Institute Molded electronic assembly
CN115763270B (zh) * 2022-11-28 2026-08-07 株洲中车时代半导体股份有限公司 Igbt模块贴装焊接方法
CN116298784B (zh) * 2023-02-20 2026-07-14 株洲中车时代半导体股份有限公司 一种转模塑封双面散热器件的芯片开封方法及夹具

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US7598121B2 (en) 2009-10-06
US20070111384A1 (en) 2007-05-17
TWI381459B (zh) 2013-01-01
KR20050065318A (ko) 2005-06-29
JP2005191053A (ja) 2005-07-14
CN1638122A (zh) 2005-07-13
CN100477208C (zh) 2009-04-08
US20050140023A1 (en) 2005-06-30

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