JP4105819B2 - 記憶装置およびメモリカード - Google Patents

記憶装置およびメモリカード Download PDF

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Publication number
JP4105819B2
JP4105819B2 JP11856799A JP11856799A JP4105819B2 JP 4105819 B2 JP4105819 B2 JP 4105819B2 JP 11856799 A JP11856799 A JP 11856799A JP 11856799 A JP11856799 A JP 11856799A JP 4105819 B2 JP4105819 B2 JP 4105819B2
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JP
Japan
Prior art keywords
data
error
output
circuit
error correction
Prior art date
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Expired - Fee Related
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JP11856799A
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English (en)
Japanese (ja)
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JP2000305861A (ja
JP2000305861A5 (https=
Inventor
敦史 野副
一男 中村
国弘 片山
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Renesas Technology Corp
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Renesas Technology Corp
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP11856799A priority Critical patent/JP4105819B2/ja
Priority to TW089106718A priority patent/TW479169B/zh
Priority to KR1020000021838A priority patent/KR20010029659A/ko
Priority to US09/558,036 priority patent/US6359806B1/en
Priority to US09/636,736 priority patent/US6351412B1/en
Publication of JP2000305861A publication Critical patent/JP2000305861A/ja
Priority to US10/012,525 priority patent/US6549460B2/en
Publication of JP2000305861A5 publication Critical patent/JP2000305861A5/ja
Application granted granted Critical
Publication of JP4105819B2 publication Critical patent/JP4105819B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
JP11856799A 1999-04-26 1999-04-26 記憶装置およびメモリカード Expired - Fee Related JP4105819B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP11856799A JP4105819B2 (ja) 1999-04-26 1999-04-26 記憶装置およびメモリカード
TW089106718A TW479169B (en) 1999-04-26 2000-04-11 Memory device and memory card
KR1020000021838A KR20010029659A (ko) 1999-04-26 2000-04-25 기억 장치 및 메모리 카드
US09/558,036 US6359806B1 (en) 1999-04-26 2000-04-26 Memory device
US09/636,736 US6351412B1 (en) 1999-04-26 2000-08-11 Memory card
US10/012,525 US6549460B2 (en) 1999-04-26 2001-12-12 Memory device and memory card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11856799A JP4105819B2 (ja) 1999-04-26 1999-04-26 記憶装置およびメモリカード

Publications (3)

Publication Number Publication Date
JP2000305861A JP2000305861A (ja) 2000-11-02
JP2000305861A5 JP2000305861A5 (https=) 2005-06-16
JP4105819B2 true JP4105819B2 (ja) 2008-06-25

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ID=14739802

Family Applications (1)

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JP11856799A Expired - Fee Related JP4105819B2 (ja) 1999-04-26 1999-04-26 記憶装置およびメモリカード

Country Status (4)

Country Link
US (3) US6359806B1 (https=)
JP (1) JP4105819B2 (https=)
KR (1) KR20010029659A (https=)
TW (1) TW479169B (https=)

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US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) * 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
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US7116602B2 (en) 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
JP4695385B2 (ja) * 2004-11-30 2011-06-08 株式会社東芝 メモリカードおよびカードコントローラ
US7424648B2 (en) * 2005-03-10 2008-09-09 Matsushita Electric Industrial Co., Ltd. Nonvolatile memory system, nonvolatile memory device, data read method, and data read program
KR100688549B1 (ko) * 2005-05-24 2007-03-02 삼성전자주식회사 비휘발성 메모리를 지원하는 온더플라이 ｂｃｃ 코덱시스템 및 방법
US8521970B2 (en) * 2006-04-19 2013-08-27 Lexmark International, Inc. Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts
US9245591B2 (en) * 2005-06-16 2016-01-26 Lexmark International, Inc. Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts
JP2007133986A (ja) * 2005-11-11 2007-05-31 Nec Electronics Corp 半導体記憶装置
US20070150798A1 (en) * 2005-12-12 2007-06-28 Jia-Horng Shieh Method for decoding an ecc block and related apparatus
JP4901334B2 (ja) * 2006-06-30 2012-03-21 株式会社東芝 メモリコントローラ
JP2008041123A (ja) * 2006-08-01 2008-02-21 Toshiba Corp 半導体記憶装置
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US7900120B2 (en) * 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
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KR100827662B1 (ko) 2006-11-03 2008-05-07 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 오류 검출 및정정 방법
US7861139B2 (en) * 2007-01-26 2010-12-28 Micron Technology, Inc. Programming management data for NAND memories
US20100100797A1 (en) * 2008-10-16 2010-04-22 Genesys Logic, Inc. Dual mode error correction code (ecc) apparatus for flash memory and method thereof
JP5422974B2 (ja) * 2008-11-18 2014-02-19 富士通株式会社 誤り判定回路及び共有メモリシステム
US8438453B2 (en) * 2009-05-06 2013-05-07 Apple Inc. Low latency read operation for managed non-volatile memory
US8470304B2 (en) * 2009-08-04 2013-06-25 Avidas Pharmaceuticals Llc Therapeutic vitamin D sun-protecting formulations and methods for their use
KR101139187B1 (ko) * 2009-12-28 2012-04-26 (주)인디링스 버퍼 없이 에러를 검출하고 정정하는 컨트롤러 및 그 컨트롤러의 동작 방법
JP5204186B2 (ja) * 2010-09-24 2013-06-05 株式会社東芝 メモリシステム
JP2012248258A (ja) * 2011-05-31 2012-12-13 Funai Electric Co Ltd 光ディスク装置
US8656251B2 (en) * 2011-09-02 2014-02-18 Apple Inc. Simultaneous data transfer and error control to reduce latency and improve throughput to a host
MY180992A (en) 2013-03-13 2020-12-15 Intel Corp Memory latency management
US10417091B2 (en) * 2013-03-25 2019-09-17 Hewlett Packard Enterprise Development Lp Memory device having error correction logic
JP2015053096A (ja) 2013-09-09 2015-03-19 マイクロン テクノロジー， インク． 半導体装置、及び誤り訂正方法
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US9734008B2 (en) * 2015-05-06 2017-08-15 International Business Machines Corporation Error vector readout from a memory device
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Also Published As

Publication number Publication date
JP2000305861A (ja) 2000-11-02
TW479169B (en) 2002-03-11
US20020054508A1 (en) 2002-05-09
US6549460B2 (en) 2003-04-15
US6351412B1 (en) 2002-02-26
KR20010029659A (ko) 2001-04-06
US6359806B1 (en) 2002-03-19

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