JP4063450B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP4063450B2
JP4063450B2 JP16632099A JP16632099A JP4063450B2 JP 4063450 B2 JP4063450 B2 JP 4063450B2 JP 16632099 A JP16632099 A JP 16632099A JP 16632099 A JP16632099 A JP 16632099A JP 4063450 B2 JP4063450 B2 JP 4063450B2
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JP
Japan
Prior art keywords
conductor layer
integrated circuit
bit line
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16632099A
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English (en)
Japanese (ja)
Other versions
JP2000353793A5 (enExample
JP2000353793A (ja
Inventor
秀行 松岡
悟 山田
勇 浅野
亮 永井
知紀 関口
理一郎 竹村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP16632099A priority Critical patent/JP4063450B2/ja
Priority to TW089110509A priority patent/TW473987B/zh
Priority to KR1020000032336A priority patent/KR100650468B1/ko
Priority to US09/592,648 priority patent/US6621110B1/en
Publication of JP2000353793A publication Critical patent/JP2000353793A/ja
Priority to US10/630,695 priority patent/US6809364B2/en
Publication of JP2000353793A5 publication Critical patent/JP2000353793A5/ja
Application granted granted Critical
Publication of JP4063450B2 publication Critical patent/JP4063450B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/908—Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP16632099A 1999-06-14 1999-06-14 半導体集積回路装置 Expired - Fee Related JP4063450B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP16632099A JP4063450B2 (ja) 1999-06-14 1999-06-14 半導体集積回路装置
TW089110509A TW473987B (en) 1999-06-14 2000-05-30 Semiconductor integrated circuit device and manufacture thereof
KR1020000032336A KR100650468B1 (ko) 1999-06-14 2000-06-13 반도체 집적 회로 장치 및 그 제조 방법
US09/592,648 US6621110B1 (en) 1999-06-14 2000-06-13 Semiconductor intergrated circuit device and a method of manufacture thereof
US10/630,695 US6809364B2 (en) 1999-06-14 2003-07-31 Semiconductor integrated circuit device and a method of manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16632099A JP4063450B2 (ja) 1999-06-14 1999-06-14 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2000353793A JP2000353793A (ja) 2000-12-19
JP2000353793A5 JP2000353793A5 (enExample) 2004-09-30
JP4063450B2 true JP4063450B2 (ja) 2008-03-19

Family

ID=15829179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16632099A Expired - Fee Related JP4063450B2 (ja) 1999-06-14 1999-06-14 半導体集積回路装置

Country Status (4)

Country Link
US (2) US6621110B1 (enExample)
JP (1) JP4063450B2 (enExample)
KR (1) KR100650468B1 (enExample)
TW (1) TW473987B (enExample)

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FR2839581B1 (fr) * 2002-05-07 2005-07-01 St Microelectronics Sa Circuit electronique comprenant un condensateur et au moins un composant semiconducteur, et procede de conception d'un tel circuit
KR100480601B1 (ko) * 2002-06-21 2005-04-06 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
KR100492899B1 (ko) * 2002-11-18 2005-06-02 주식회사 하이닉스반도체 반도체소자 및 그 제조 방법
DE10259634B4 (de) * 2002-12-18 2008-02-21 Qimonda Ag Verfahren zur Herstellung von Kontakten auf einem Wafer
KR100502669B1 (ko) * 2003-01-28 2005-07-21 주식회사 하이닉스반도체 반도체 메모리소자 및 그 제조 방법
JP2004311706A (ja) * 2003-04-07 2004-11-04 Toshiba Corp 半導体装置及びその製造方法
JP4342854B2 (ja) * 2003-07-09 2009-10-14 株式会社東芝 半導体装置及びその製造方法
JP4627977B2 (ja) 2003-10-14 2011-02-09 ルネサスエレクトロニクス株式会社 半導体装置
US7375033B2 (en) * 2003-11-14 2008-05-20 Micron Technology, Inc. Multi-layer interconnect with isolation layer
KR100630683B1 (ko) * 2004-06-02 2006-10-02 삼성전자주식회사 6ｆ2 레이아웃을 갖는 디램 소자
KR100706233B1 (ko) * 2004-10-08 2007-04-11 삼성전자주식회사 반도체 기억 소자 및 그 제조방법
KR100604911B1 (ko) 2004-10-20 2006-07-28 삼성전자주식회사 하부전극 콘택을 갖는 반도체 메모리 소자 및 그 제조방법
KR100593746B1 (ko) * 2004-12-24 2006-06-28 삼성전자주식회사 디램의 커패시터들 및 그 형성방법들
KR100752644B1 (ko) 2005-04-12 2007-08-29 삼성전자주식회사 반도체 소자의 셀영역 레이아웃 및 이를 이용한 콘택패드제조방법
KR100693879B1 (ko) * 2005-06-16 2007-03-12 삼성전자주식회사 비대칭 비트 라인들을 갖는 반도체 장치 및 이를 제조하는방법
KR100654353B1 (ko) * 2005-06-28 2006-12-08 삼성전자주식회사 커패시터를 구비하는 반도체 집적 회로 장치 및 이의 제조방법
US7687342B2 (en) * 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7557032B2 (en) 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US8716772B2 (en) * 2005-12-28 2014-05-06 Micron Technology, Inc. DRAM cell design with folded digitline sense amplifier
KR100876881B1 (ko) * 2006-02-24 2008-12-31 주식회사 하이닉스반도체 반도체 소자의 패드부
US7349232B2 (en) * 2006-03-15 2008-03-25 Micron Technology, Inc. 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier
JP2007294618A (ja) * 2006-04-24 2007-11-08 Elpida Memory Inc 半導体装置の製造方法及び半導体装置
US20080035956A1 (en) * 2006-08-14 2008-02-14 Micron Technology, Inc. Memory device with non-orthogonal word and bit lines
US7521763B2 (en) * 2007-01-03 2009-04-21 International Business Machines Corporation Dual stress STI
KR100898394B1 (ko) * 2007-04-27 2009-05-21 삼성전자주식회사 반도체 집적 회로 장치 및 그 제조 방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8294188B2 (en) * 2008-10-16 2012-10-23 Qimonda Ag 4 F2 memory cell array
JP2010219139A (ja) * 2009-03-13 2010-09-30 Elpida Memory Inc 半導体装置及びその製造方法
JP2010219326A (ja) * 2009-03-17 2010-09-30 Elpida Memory Inc 半導体記憶装置及びその製造方法
KR101076888B1 (ko) * 2009-06-29 2011-10-25 주식회사 하이닉스반도체 반도체 소자의 연결 배선체 및 형성 방법
JP2011023652A (ja) * 2009-07-17 2011-02-03 Elpida Memory Inc 半導体記憶装置
US8558320B2 (en) * 2009-12-15 2013-10-15 Qualcomm Incorporated Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior
US8686486B2 (en) 2011-03-31 2014-04-01 Semiconductor Energy Laboratory Co., Ltd. Memory device
JP5831687B2 (ja) * 2011-07-22 2015-12-09 ソニー株式会社 記憶装置およびその製造方法
CN105905231A (zh) * 2016-05-19 2016-08-31 国家海洋局第海洋研究所 便携双体船
CN109427787A (zh) * 2017-08-30 2019-03-05 联华电子股份有限公司 半导体存储装置
CN113903740B (zh) * 2020-07-06 2025-05-09 华邦电子股份有限公司 半导体存储器结构及其形成方法
US11637107B2 (en) 2021-06-17 2023-04-25 Applied Materials, Inc. Silicon-containing layer for bit line resistance reduction
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CN115996560B (zh) * 2021-10-15 2025-07-25 长鑫存储技术有限公司 一种存储器及其制造方法

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JP3368002B2 (ja) 1993-08-31 2003-01-20 三菱電機株式会社 半導体記憶装置
TW377495B (en) * 1996-10-04 1999-12-21 Hitachi Ltd Method of manufacturing semiconductor memory cells and the same apparatus
TW442923B (en) * 1998-03-20 2001-06-23 Nanya Technology Corp Manufacturing method of DRAM comprising redundancy circuit region
JP3137185B2 (ja) * 1998-04-09 2001-02-19 日本電気株式会社 半導体記憶装置
KR20010003628A (ko) * 1999-06-24 2001-01-15 김영환 반도체 메모리셀 구조 및 제조방법

Also Published As

Publication number Publication date
US6809364B2 (en) 2004-10-26
TW473987B (en) 2002-01-21
KR100650468B1 (ko) 2006-11-28
US20040021159A1 (en) 2004-02-05
US6621110B1 (en) 2003-09-16
JP2000353793A (ja) 2000-12-19
KR20010020983A (ko) 2001-03-15

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