JP3974284B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3974284B2 JP3974284B2 JP07348699A JP7348699A JP3974284B2 JP 3974284 B2 JP3974284 B2 JP 3974284B2 JP 07348699 A JP07348699 A JP 07348699A JP 7348699 A JP7348699 A JP 7348699A JP 3974284 B2 JP3974284 B2 JP 3974284B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide
- layer
- conductive layer
- forming
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07348699A JP3974284B2 (ja) | 1999-03-18 | 1999-03-18 | 半導体装置の製造方法 |
| US09/526,880 US6348402B1 (en) | 1999-03-18 | 2000-03-16 | Method of manufacturing a copper interconnect |
| TW089104982A TW452835B (en) | 1999-03-18 | 2000-03-17 | Manufacture of semiconductor device |
| KR1020000013549A KR100359968B1 (ko) | 1999-03-18 | 2000-03-17 | 반도체 장치의 제조 방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07348699A JP3974284B2 (ja) | 1999-03-18 | 1999-03-18 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2000269213A JP2000269213A (ja) | 2000-09-29 |
| JP2000269213A5 JP2000269213A5 (enExample) | 2005-08-25 |
| JP3974284B2 true JP3974284B2 (ja) | 2007-09-12 |
Family
ID=13519667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07348699A Expired - Fee Related JP3974284B2 (ja) | 1999-03-18 | 1999-03-18 | 半導体装置の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6348402B1 (enExample) |
| JP (1) | JP3974284B2 (enExample) |
| KR (1) | KR100359968B1 (enExample) |
| TW (1) | TW452835B (enExample) |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000079586A1 (en) * | 1999-06-24 | 2000-12-28 | Hitachi, Ltd. | Production method for semiconductor integrated circuit device and semiconductor integrated circuit device |
| JP4554011B2 (ja) | 1999-08-10 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
| US6433429B1 (en) * | 1999-09-01 | 2002-08-13 | International Business Machines Corporation | Copper conductive line with redundant liner and method of making |
| JP3439402B2 (ja) * | 1999-11-05 | 2003-08-25 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US6846711B2 (en) * | 2000-03-02 | 2005-01-25 | Tokyo Electron Limited | Method of making a metal oxide capacitor, including a barrier film |
| JP2001291720A (ja) * | 2000-04-05 | 2001-10-19 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
| JP2002110679A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| KR100365643B1 (ko) * | 2000-10-09 | 2002-12-26 | 삼성전자 주식회사 | 반도체 장치의 다마신 배선 형성 방법 및 그에 의해형성된 다마신 배선 구조체 |
| US6508919B1 (en) * | 2000-11-28 | 2003-01-21 | Tokyo Electron Limited | Optimized liners for dual damascene metal wiring |
| JP2002164428A (ja) | 2000-11-29 | 2002-06-07 | Hitachi Ltd | 半導体装置およびその製造方法 |
| KR100386034B1 (ko) | 2000-12-06 | 2003-06-02 | 에이에스엠 마이크로케미스트리 리미티드 | 확산 방지막의 결정립계를 금속산화물로 충진한 구리 배선구조의 반도체 소자 제조 방법 |
| JP2002217292A (ja) | 2001-01-23 | 2002-08-02 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
| JP2003051481A (ja) * | 2001-08-07 | 2003-02-21 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US6815818B2 (en) * | 2001-11-19 | 2004-11-09 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
| JP3648480B2 (ja) | 2001-12-26 | 2005-05-18 | 株式会社東芝 | 半導体装置およびその製造方法 |
| US20080070405A1 (en) * | 2002-05-30 | 2008-03-20 | Park Jae-Hwa | Methods of forming metal wiring layers for semiconductor devices |
| KR100564605B1 (ko) * | 2004-01-14 | 2006-03-28 | 삼성전자주식회사 | 반도체 소자의 금속 배선 형성 방법 |
| KR100446300B1 (ko) * | 2002-05-30 | 2004-08-30 | 삼성전자주식회사 | 반도체 소자의 금속 배선 형성 방법 |
| KR100475931B1 (ko) * | 2002-07-02 | 2005-03-10 | 매그나칩 반도체 유한회사 | 반도체 소자의 다층 배선 형성방법 |
| JP2004140198A (ja) * | 2002-10-18 | 2004-05-13 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| JP2006505127A (ja) * | 2002-10-29 | 2006-02-09 | エーエスエム インターナショナル エヌ.ヴェー. | 酸素架橋構造及び方法 |
| JP2005244178A (ja) * | 2004-01-26 | 2005-09-08 | Toshiba Corp | 半導体装置の製造方法 |
| US20090304914A1 (en) * | 2006-08-30 | 2009-12-10 | Lam Research Corporation | Self assembled monolayer for improving adhesion between copper and barrier layer |
| US7351656B2 (en) * | 2005-01-21 | 2008-04-01 | Kabushiki Kaihsa Toshiba | Semiconductor device having oxidized metal film and manufacture method of the same |
| JP4199206B2 (ja) * | 2005-03-18 | 2008-12-17 | シャープ株式会社 | 半導体装置の製造方法 |
| JP2007012996A (ja) * | 2005-07-01 | 2007-01-18 | Toshiba Corp | 半導体装置 |
| JP4282646B2 (ja) * | 2005-09-09 | 2009-06-24 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2007173511A (ja) * | 2005-12-22 | 2007-07-05 | Sony Corp | 半導体装置の製造方法 |
| JP2007266073A (ja) * | 2006-03-27 | 2007-10-11 | Toshiba Corp | 半導体装置及びその製造方法 |
| TW200814156A (en) | 2006-07-21 | 2008-03-16 | Toshiba Kk | Method for manufacturing semiconductor device and semiconductor device |
| JP2008258311A (ja) * | 2007-04-03 | 2008-10-23 | Denso Corp | 半導体装置及び半導体装置の配線または電極形成方法 |
| JP2010171398A (ja) * | 2008-12-26 | 2010-08-05 | Toshiba Corp | 半導体装置の製造方法 |
| US20110291147A1 (en) | 2010-05-25 | 2011-12-01 | Yongjun Jeff Hu | Ohmic contacts for semiconductor structures |
| US9343357B2 (en) | 2014-02-28 | 2016-05-17 | Qualcomm Incorporated | Selective conductive barrier layer formation |
| JP6259023B2 (ja) * | 2015-07-20 | 2018-01-10 | ウルトラテック インク | 電極系デバイス用のald処理のためのマスキング方法 |
| JP6595432B2 (ja) * | 2016-09-23 | 2019-10-23 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
| US9953927B1 (en) * | 2017-04-26 | 2018-04-24 | Globalfoundries Inc. | Liner replacements for interconnect openings |
| KR102370620B1 (ko) | 2017-07-10 | 2022-03-04 | 삼성전자주식회사 | 반도체 메모리 장치 및 도전체 구조물 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04259242A (ja) * | 1991-02-14 | 1992-09-14 | Fujitsu Ltd | 半導体装置の製造方法 |
| US5130274A (en) | 1991-04-05 | 1992-07-14 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
| US5679982A (en) * | 1993-02-24 | 1997-10-21 | Intel Corporation | Barrier against metal diffusion |
| US5989999A (en) * | 1994-11-14 | 1999-11-23 | Applied Materials, Inc. | Construction of a tantalum nitride film on a semiconductor wafer |
| US5918150A (en) | 1996-10-11 | 1999-06-29 | Sharp Microelectronics Technology, Inc. | Method for a chemical vapor deposition of copper on an ion prepared conductive surface |
| JPH10189730A (ja) * | 1996-11-11 | 1998-07-21 | Toshiba Corp | 半導体装置及びその製造方法 |
| US6139697A (en) * | 1997-01-31 | 2000-10-31 | Applied Materials, Inc. | Low temperature integrated via and trench fill process and apparatus |
-
1999
- 1999-03-18 JP JP07348699A patent/JP3974284B2/ja not_active Expired - Fee Related
-
2000
- 2000-03-16 US US09/526,880 patent/US6348402B1/en not_active Expired - Fee Related
- 2000-03-17 KR KR1020000013549A patent/KR100359968B1/ko not_active Expired - Fee Related
- 2000-03-17 TW TW089104982A patent/TW452835B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000269213A (ja) | 2000-09-29 |
| TW452835B (en) | 2001-09-01 |
| KR20000076888A (ko) | 2000-12-26 |
| US6348402B1 (en) | 2002-02-19 |
| KR100359968B1 (ko) | 2002-11-07 |
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