TWI531026B - 形成氧化物經封裝傳導形體之方法及具有該形體之裝置 - Google Patents

形成氧化物經封裝傳導形體之方法及具有該形體之裝置 Download PDF

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TWI531026B
TWI531026B TW100148253A TW100148253A TWI531026B TW I531026 B TWI531026 B TW I531026B TW 100148253 A TW100148253 A TW 100148253A TW 100148253 A TW100148253 A TW 100148253A TW I531026 B TWI531026 B TW I531026B
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劉晃
奇森 賽特
凱 宏 艾力克 史
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格羅方德半導體私人有限公司
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Description

形成氧化物經封裝傳導形體之方法及具有該形體之裝置
本發明係有關半導體裝置中之銅(Cu)及/或銅合金金屬化，以及有關一種製造具有可信賴，低電阻銅或銅合金互連之半導體裝置之方法。本發明特別可應用於形成具有次微米設計形體及高導電率互連結構之高速積體電路，包含以金屬-氧化物層，如MnOx或AlOx予以實質上均勻地封裝之銅或銅合金形體。
在半導體製造中，在金屬互連後段製程(BEOL)加工期間施加鑲嵌(damascene)。習知鑲嵌加工包含在介電中間層形成開口及以導電材料，例如，銅或銅合金填充開口，以形成接觸面、通孔、或線。習知BEOL加工包含在晶圓上利用配線之個別裝置(電晶體、電容、電阻等)的互連，以及晶片-對-封裝連接之接觸面、絕緣層(介電質)、金屬層級、及接合位置的形成。
如第1A-1F圖所示，使用習知鑲嵌製程形成半導體裝置中之金屬互連。第1A圖顯示形成在介電層103中之溝槽101。
由於銅經由介電中間層材料，如二氧化矽擴散，故銅或銅合金互連結構必須藉由擴散阻障層予以封裝。第1B圖顯示沉積在溝槽101之側表面107和底表面109上，以及介電層103之上表面111上之擴散阻障層105(例如，Ta/TaN)。
種晶層113沉積在阻障層105上，如第1C圖所示。種晶層113可為銅、或銅合金，如CuMn或CuAl。第1D圖顯示銅、或銅合金115，通常利用電鍍，填充溝槽101及種晶層113之上。
然後如藉由化學機械加工(CMP)實施平坦化以自介電層103移除銅或銅合金115、種晶層113、和阻障層105，而形成實質上平坦之上表面，如第1E圖所示。
然後沉積覆蓋層117，如氮化矽(SiN)或氮碳化矽(SiCxNy)，如第1F圖所示。
在第1F圖中，當使用銅合金種晶層如CuMn或CuAl時，錳或鋁在銅或銅合金115與覆蓋層117間之界面析出。析出量視種晶層113中之錳或鋁濃度及其他製程條件而定。析出程度可導致種晶層113僅包含銅，而大部份的錳或鋁因與氧(O2)反應而轉化成金屬氧化物層119，例如，MnO或Al2O3。
除了該種界面外，析出亦發生在任何受損或缺陷位置(如具有不足夠之阻障層的位置)。第2圖顯示襯有阻障層203之習知銅或銅合金互連201。習知實務導致合金原子，如錳或鋁原子205，向著O2擴散以在銅或銅合金互連201之上表面207上以及存在著O2之受損和缺陷位置形成氧化物層，例如，MnO或Al2O3。
銅或銅合金互連201中之合金原子，如錳或鋁原子205輕易地向著O2擴散以形成氧化物，例如，MnO或Al2O3，此乃由於其低活化能之故。另一方面，元素原子，如錳或鋁存在時，銅不會與O2反應形成CuO。所得之氧化物層，例如，MnO或Al2O3，作為阻障層以防止：(a)銅沿著Cu/SiCNH界面207擴散而形成CuO；(b) O2擴散至銅互連201中形成CuO；以及(c)錳或鋁繼續擴散至介電層213中。因此，提昇互連的電遷移(EM)性能。
受損和缺陷位置可為太薄之阻障層203之部份207、或節點201與介電層213間之缺陷界面211。阻障層203應完全地包圍整個銅互連201以防止銅擴散至周圍材料中並且穿過周圍材料。阻障層203應該要足夠厚以限制銅擴散，因此化學地隔離互連201與介電層213，而且還呈現足夠高的導電性以維持與導線215的良好電子接觸。然而，阻障層203在某些位置會太薄以致無法限制銅擴散。
習知實務僅導致氧化物層，例如，MnO或Al2O3，形成在存在著O2之互連201的上表面上或缺陷/破裂襯底區域207、211。然而，習知實務無法導致沿著沉積之導電材料，例如，銅或銅合金的側壁形成實質上均勻的氧化物阻障層，此乃由於該些位置缺乏O2之故。
在先進節點如20nm及以下，阻障層(例如，Ta/TaN，Ru)的厚度進一步薄化以促進間隙填充及降低導線電阻。然而，該種薄化的阻障層沒有強壯到足以禁得起EM、應力遷移(SM)、或時間相依介電崩潰(TDDB)加壓，且其中可能含有受損和缺陷區域。因此，BEOL可靠度性能降低。
因此需要存在一種能夠形成封裝金屬互連之實質上均勻之金屬氧化物阻障層的方法論，因此阻擋銅擴散且提昇可靠度性能沒有負面地衝擊間隙填充。
本發明之一方面係一種在BEOL加工期間，形成藉由實質上均勻之金屬-氧化物層，如MnO或Al2O3予以封裝之銅或銅合金互連。
本發明之另一方面係一種包含藉由實質上均勻之金屬-氧化物層，如MnO或Al2O3予以封裝之銅或銅合金互連之半導體裝置。
本發明之其他方面及其他特點將揭露於下述說明中，而且對熟知此項技藝人士而言在檢視下述說明時在某種程度上係顯而易見的或者可自本發明的實務學習之。
依據本發明，某些技術功效在某種程度上可藉由包含下述步驟之方法予以達成：在介電層中形成具有側表面及底表面之開口，在開口之側表面和底表面上及介電層之上表面上形成阻障層，以氧氣電漿處理阻障層以在阻障層上形成懸垂氧原子，在阻障層上形成種晶層，以及以銅或銅合金填充開口。
本發明之方面包含如藉由CMP平坦化以自介電層之上表面移除阻障層，種晶層，及銅或銅合金，使得鑲嵌之銅或銅合金的上表面與介電層的上表面實質上共平面。進一步方面包含在填充開口之銅或銅合金上提供覆蓋層，如SiN或SiCxNy。其他方面包含沉積銅合金種晶層，如CuMn或CuAl，導致形成金屬氧化物層，例如MnO或Al2O3。其他方面包含以5 至100 之厚度沉積阻障層。另一方面包含以100 至500 之厚度沉積種晶層。依據又一方面，以5 至20 之厚度形成金屬氧化物層。
本發明之另一方面係一種裝置，包含：半導體元件，半導體元件上之介電層，填充介電層中之開口之銅或銅合金，以及封裝填充開口之銅或銅合金之金屬氧化物層。
本發明之方面包含裝置，此裝置包含藉由具有5 至20 之實質上均勻厚度之氧化物層，例如MnO或Al2O3層予以封裝之鑲嵌銅或銅合金。本發明之方面包含在具有5 至100 厚度之阻障層之溝槽中具有銅或銅合金鑲嵌之裝置。
本發明之另一方面係一種方法，包含：在半導體元件上提供介電層；在介電層中形成具有側表面及底表面之溝槽；在溝槽之側表面及底表面上沉積阻障層；以氧氣電漿處理阻障層以形成鍵結在阻障層上之懸垂氧；在阻障層上沉積銅合金種晶層；以銅(Cu)或銅合金填充溝槽以形成銅或銅合金鑲嵌及在介電層之上表面上之過覆蓋；以及平坦化，使得銅或銅合金鑲嵌之上表面與介電層之上表面實質上共平面，導致封裝銅或銅合金鑲嵌之金屬氧化物層。
由下述之詳細說明，對熟知此項技藝人士而言，本發明之其他方面及技術功效係顯而易見的，其中本發明之實施例係藉由意欲實施本發明之最佳模式的說明予以簡單地陳述。如可瞭解般，本發明能夠以其他及不同實施例完成之，且其數種細節能夠在各種顯而易知方面予以修飾，皆無偏離本發明。因此，圖式及說明事實上係欲作為說明之用，而非作為限制之用。
在下述說明中，為了闡釋之目的，提出許多特定的細節以提供徹底瞭解示例之實施例。然而，應可清楚瞭解，沒有這些特定的細節或者利用均等的配置亦可實施這些示例的實施例。其他實例中，在方塊圖中顯示眾所皆知的結構及裝置以避免非必要地模糊示例之實施例。此外，除非另有說明，否則應瞭解說明書及申請專利範圍中所使用之成分、反應條件等之表示數量、比率、及數值性質之所有數值在所有實例中皆以"約"一詞予以修飾。
本發明關注並解決BEOL可靠度性能的問題，尤其當阻障襯底的厚度減小而調和間隙填充及低線電阻時。本發明藉由提供能夠形成實質上均勻之金屬-氧化物層，例如，MnO或Al2O3層、封裝金屬互連，例如，銅或銅合金接觸面、通孔、或線，因此防止銅擴散至介電層中並且穿過介電層，故而提昇可靠度性能沒有負面地衝擊間隙填充之方法論關注並解決該些問題。
依據本發明實施例的方法論係包含在介電層中形成具有側表面及底表面之開口，在開口之側表面和底表面上及介電層之上表面上形成阻障層，以氧氣電漿處理阻障層以在阻障層上形成懸垂氧原子，在阻障層上沉積種晶層，以及以銅或銅合金填充開口。
由下述之詳細說明，熟知此項技藝人士可淺顯易見地瞭解阻擋銅自銅或銅合金互連擴散沒有負面地衝擊間隙填充之又其他方面、特點、及技術功效，其中簡單地藉由意欲之最佳模式的說明，顯示及陳述較佳實施例。本發明能夠以其他及不同實施例完成之，且其數種細節能夠在各種顯而易知方面予以修飾。因此，圖式及說明事實上係欲作為說明之用，而非作為限制之用。
第3A-3G圖係說明依據本發明實施例之方法論。參照第3A圖，係藉由例如反應性離子蝕刻(RIE)在介電層303中形成開口，例如，溝槽301。
藉由，例如，物理氣相沉積(PVD)在溝槽301之側表面307及底表面309上、及介電層303之上表面311上形成擴散阻障層305，如第3B圖所示。阻障層305可以5Å至100Å之厚度形成之。典型之擴散阻障金屬包含鉭(Ta)，氮化鉭(TaN)，釕(Ru)，鈷(Co)，或Ta/TaN。
參照第3C圖，以氧氣電漿313，如30-180秒、於400-900W之RF電力、15-35m托之壓力、100-400℃、及60-120sccm之臭氧(O3)流動速率處理所得之結構。利用氧氣電漿之處理沿著溝槽301之側表面307及底表面309在阻障層305中形成懸垂氧原子。該些懸垂氧原子隨後反應以形成封裝氧化物阻障。
參照第3D圖，藉由，例如，物理氣相沉積(PVD)在阻障層305上沉積種晶層315。種晶層315可形成至100Å至500Å之厚度，且可包含銅合金，如CuMn或CuAl。與銅種晶層相較下，CuAl種晶層以十倍增加EM壽命，而與銅種晶層相較下，CuMn種晶層以一百倍增加EM壽命。
如藉由電化學電鍍、無電電鍍、或化學氣相沉積來沉積導電材料，如銅或銅合金317，以填充溝槽301並在介電層302上形成過覆蓋317，如第3E圖所示。然後如藉由CMP實施平坦化以自介電層301之上表面移除過覆蓋317，及阻障層305和種晶層315，形成實質上平坦之上表面，如第3F圖所示。
後續如藉由化學氣相沉積(CVD)沉積覆蓋層319，如第3G圖所示。覆蓋層319可包含SiN或SiCxNy。
種晶層315中之合金金屬原子，例如，錳或鋁析出至先前形成之懸垂氧原子以形成封裝之氧化物層，例如，MnO或Al2O3。析出量視銅合金種晶層中之錳或鋁濃度及各種製程條件而定。在某些實施例中，析出足以導致實質上之銅種晶層，使得實質上所有的錳或鋁皆析出以形成實質上均勻之封裝MnO或Al2O3氧化物層321。一般而言，該種保護性氧化物層係在銅或銅合金沉積之前形成之。EDX/EELS分析確認懸垂氧鍵結可完全地氧化來自5Å至20Å厚度之種晶層之錳或鋁原子以形成實質上均勻之MnO或Al2O3封裝層。
本發明之實施例可達成數種技術功效，包含阻擋銅自銅或銅合金互連擴散，因此提昇EM壽命沒有負面地衝擊間隙填充。本發明在各種高度集成之半導體裝置之任一種上具有產業應用性。
在前述說明中，本發明係參照其特定示例之實施例予以說明。然而，可證明可對其進行各種修飾及變更沒有偏 離本發明之較廣精神及範圍，如申請專利範圍所述。因此，說明及圖式欲視為係說明之用而非限制之用。可瞭解本發明能夠使用各種其他組合及實施例且在本文所示之本發明概念之範圍內能夠有任何變更或修飾。
101、301‧‧‧溝槽
103、213、303‧‧‧介電層
105、203、305‧‧‧阻障層
107、307‧‧‧側表面
109、309‧‧‧底表面
111、207、311‧‧‧上表面
113、315‧‧‧種晶層
115、317‧‧‧銅或銅合金
117、319‧‧‧覆蓋層
119、321‧‧‧金屬氧化物層
201．．．互連
205．．．錳或鋁原子
209．．．節點
211．．．缺陷界面
215．．．導線
313．．．氧氣電漿
在隨附的圖式中，本發明係藉由實施例予以說明，而非予以限制，且圖式中類似的參考數值係指類似的元件，其中：第1A至1F圖係圖解地說明形成半導體裝置中之金屬互連的習知鑲嵌製程；第2圖係圖解地說明襯有阻障層之習知互連；以及第3A至3G圖係圖解地說明依據本發明實施例之形成半導體裝置中之金屬互連的製程流程。
317．．．銅或銅合金

Claims (20)

  1. 一種製造半導體裝置之方法，包括：在介電層中形成具有側表面及底表面之開口；在該開口之該側表面及該底表面上和該介電層之上表面上形成阻障層，該阻障層係鉭、氮化鉭、釕、鈷或鉭/氮化鉭所形成；以氧氣電漿處理該阻障層，以在該阻障層上形成懸垂氧原子；在該阻障層上沉積種晶層；以及以銅(Cu)或銅合金填充該開口，導致在該銅或銅合金的上及底表面上和沿著填充該開口之該銅或銅合金之側表面形成金屬氧化物層，且提供直接地介於該金屬氧化物層與該介電層之間之部分該阻障層填充該開口。
  2. 如申請專利範圍第1項所述之方法，包括自該介電層之該上表面移除該阻障層、該種晶層、及該銅或銅合金。
  3. 如申請專利範圍第2項所述之方法，包括在填充該開口之該銅或銅合金上形成覆蓋層。
  4. 如申請專利範圍第3項所述之方法，其中該覆蓋層包括氮碳化矽(SiCxNy)。
  5. 如申請專利範圍第1項所述之方法，包括沉積作為該種晶層之銅合金。
  6. 如申請專利範圍第5項所述之方法，包括沉積作為該 種晶層之CuMn或CuAl合金，其中該金屬氧化物層包括MnO或Al2O3。
  7. 如申請專利範圍第1項所述之方法，包括以5Å至100Å之厚度沉積該阻障層。
  8. 如申請專利範圍第1項所述之方法，包括以100Å至500Å之厚度沉積該種晶層。
  9. 如申請專利範圍第1項所述之方法，包括以5Å至20Å之厚度形成該金屬氧化物層。
  10. 一種半導體裝置，包括：半導體元件；在該半導體元件上之介電層；形成在該介電層中之開口之側表面及底表面上之阻障層；形成在該阻障層上之封裝氧化物層；形成在該封裝氧化物層上之種晶層；填充該介電層中之該開口之銅或銅合金；以及封裝填充該開口之該銅或銅合金之金屬氧化物層。
  11. 如申請專利範圍第10項所述之半導體裝置，其中該金屬氧化物層包括MnO或Al2O3。
  12. 如申請專利範圍第10項所述之半導體裝置，進一步包括加襯該開口之阻障層。
  13. 如申請專利範圍第10項所述之半導體裝置，其中該金屬氧化物層具有5Å至20Å之實質上均勻之厚度。
  14. 如申請專利範圍第10項所述之半導體裝置，其中該阻障層具有5Å至100Å之厚度。
  15. 如申請專利範圍第10項所述之半導體裝置，其中：該開口為溝槽；以及填充該溝槽之該銅或銅合金為導線。
  16. 一種製造半導體裝置之方法，包括：在半導體元件上提供介電層；在該介電層中形成具有側表面及底表面之溝槽；在該溝槽之該側表面及該底表面上沉積阻障層，該阻障層係鉭、氮化鉭、釕、鈷或鉭/氮化鉭所形成；以氧氣電漿處理該阻障層，以在該阻障層上形成懸垂氧原子；在該阻障層上沉積銅合金種晶層；以銅(Cu)或銅合金填充該溝槽，以形成銅或銅合金鑲嵌及在該介電層之上表面上之過覆蓋；以及平坦化，使得該銅或銅合金鑲嵌之上表面與該介電層之該上表面實質上共平面，導致形成封裝該銅或銅合金鑲嵌之金屬氧化物層，且提供部分該阻障層直接地介於該金屬氧化物層與該介電層之間。
  17. 如申請專利範圍第16項所述之方法，包括沉積作為該種晶層之CuMn合金或CuAl合金。
  18. 如申請專利範圍第17項所述之方法，其中該金屬氧化物層包括MnO或Al2O3。
  19. 如申請專利範圍第16項所述之方法，包括以5Å至100Å之厚度沉積該阻障層。
  20. 如申請專利範圍第16項所述之方法，其中係以5Å至20Å之厚度形成該金屬氧化物層。
TW100148253A 2011-04-27 2011-12-23 形成氧化物經封裝傳導形體之方法及具有該形體之裝置 TWI531026B (zh)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012204501A (ja) * 2011-03-24 2012-10-22 Sony Corp 半導体装置、電子デバイス、及び、半導体装置の製造方法
US8765602B2 (en) 2012-08-30 2014-07-01 International Business Machines Corporation Doping of copper wiring structures in back end of line processing
US20140061915A1 (en) * 2012-08-30 2014-03-06 International Business Machines Corporation Prevention of thru-substrate via pistoning using highly doped copper alloy seed layer
TW201421637A (zh) * 2012-11-30 2014-06-01 Ind Tech Res Inst 利用自我成長阻障之阻障層結構及使用該結構之溝槽式半導體結構
CN105226050A (zh) * 2014-06-09 2016-01-06 旺宏电子股份有限公司 半导体结构及其制造方法
US9455182B2 (en) 2014-08-22 2016-09-27 International Business Machines Corporation Interconnect structure with capping layer and barrier layer
US11075179B2 (en) * 2018-08-30 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
CN111009644B (zh) * 2019-11-13 2023-09-22 天津工业大学 纳米多孔铜表面修饰MnO/石墨烯复合电极的制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
US6495449B1 (en) * 2000-03-07 2002-12-17 Simplus Systems Corporation Multilayered diffusion barrier structure for improving adhesion property
US20020117399A1 (en) * 2001-02-23 2002-08-29 Applied Materials, Inc. Atomically thin highly resistive barrier layer in a copper via
WO2004040642A1 (en) * 2002-10-29 2004-05-13 Asm America, Inc. Oxygen bridge structures and methods
JP4236201B2 (ja) * 2005-08-30 2009-03-11 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
KR100729126B1 (ko) * 2005-11-15 2007-06-14 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 및 그 형성 방법
JP2007180408A (ja) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20070259519A1 (en) * 2006-05-02 2007-11-08 International Business Machines Corporation Interconnect metallization process with 100% or greater step coverage
JP2008047719A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置の製造方法
US7884475B2 (en) * 2007-10-16 2011-02-08 International Business Machines Corporation Conductor structure including manganese oxide capping layer
KR101088813B1 (ko) * 2008-07-25 2011-12-01 주식회사 하이닉스반도체 반도체 소자의 금속배선 및 그 형성방법
JP4415100B1 (ja) * 2008-12-19 2010-02-17 国立大学法人東北大学 銅配線、半導体装置および銅配線形成方法
US8268722B2 (en) * 2009-06-03 2012-09-18 Novellus Systems, Inc. Interfacial capping layers for interconnects
JP5560696B2 (ja) * 2009-12-21 2014-07-30 富士通セミコンダクター株式会社 半導体装置の製造方法
US8299365B2 (en) * 2010-01-07 2012-10-30 International Business Machines Corporation Self-aligned composite M-MOx/dielectric cap for Cu interconnect structures

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