TWI611545B - 互連線結構與其製造方法 - Google Patents

互連線結構與其製造方法 Download PDF

Info

Publication number
TWI611545B
TWI611545B TW105127113A TW105127113A TWI611545B TW I611545 B TWI611545 B TW I611545B TW 105127113 A TW105127113 A TW 105127113A TW 105127113 A TW105127113 A TW 105127113A TW I611545 B TWI611545 B TW I611545B
Authority
TW
Taiwan
Prior art keywords
aluminum
layer
dielectric layer
etch stop
hole
Prior art date
Application number
TW105127113A
Other languages
English (en)
Other versions
TW201724436A (zh
Inventor
吳中文
Chung Wen Wu
張簡旭珂
Shiu Ko Jangjian
邱建文
Chien Wen Chiu
陳建全
Chien Chung Chen
Original Assignee
台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司, Taiwan Semiconductor Manufacturing Co., Ltd. filed Critical 台灣積體電路製造股份有限公司
Publication of TW201724436A publication Critical patent/TW201724436A/zh
Application granted granted Critical
Publication of TWI611545B publication Critical patent/TWI611545B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

互連線結構包括第一介電層、存在於第一介電層中之導電特徵、存在於第一介電層上之第二介電層、存在於第一介電層與第二介電層之間的含鋁蝕刻停止層、至少存在於第二介電層中及電連接至導電特徵的導電通孔，及至少存在於導電通孔底部轉角處的至少一個含鋁碎片。

Description

互連線結構與其製造方法
本揭露是關於一種互連線結構與其製造方法。
半導體積體電路(integrated circuit；IC)已經歷迅速增長。現代積體電路由幾乎數百萬有效裝置組成，如電晶體及電容器。IC材料及設計之技術進步已生產數代IC，其中每一代都具有比上一代更小及更複雜的電路。此等裝置最初是彼此隔絕的，但後來經由多個金屬層互連在一起以形成功能電路。隨著IC變得日益複雜，互連線結構亦變得更為複雜，導致增大數目之金屬層。
互連線結構可包括橫向互連，如金屬線(導線)，及垂直互連，如導電通孔及觸點。然而，複雜互連線限制現代積體電路之效能及密度。
根據本揭露之一些實施例，互連線結構包括第一介電層、存在於第一介電層中之導電特徵、存在於第一介電層上及其中具有孔洞的第二介電層、存在於孔洞中及電連接至導 電特徵的導體，及至少部分地存在於孔洞之至少一個側壁上之複數個含鋁碎片，其中孔洞側壁底部的含鋁碎片密度大於孔洞側壁中部的含鋁碎片密度。
根據本揭露之一些實施例，互連線結構包括第一介電層、存在於第一介電層中之導電特徵、存在於第一介電層上之第二介電層、存在於第一介電層與第二介電層之間的含鋁蝕刻停止層、至少存在於第二介電層中及電連接至導電特徵的導電通孔，及至少存在於導電通孔底部轉角處的至少一個含鋁碎片。
根據本揭露之一些實施例，製造互連線結構之一方法，此方法包括在第一介電層中形成導電特徵；在導電特徵及第一介電層上形成含鋁蝕刻停止層；在含鋁蝕刻停止層上形成第二介電層；及蝕刻第二介電層及含鋁蝕刻停止層以在第二介電層及含鋁蝕刻停止層中形成孔洞，其中導電特徵至少部分地由孔洞曝露，及蝕刻含鋁蝕刻停止層將至少一個含鋁碎片重新濺射至孔洞之至少一個側壁上。
110‧‧‧第一介電層
112‧‧‧開口
120‧‧‧導電特徵
122‧‧‧擴散阻障層
130‧‧‧下蝕刻停止層
132‧‧‧含鋁碎片
140‧‧‧上蝕刻停止層
150‧‧‧第二介電層
151‧‧‧上溝槽區段
152‧‧‧孔洞
153‧‧‧下通孔孔洞區段
160‧‧‧抗反射塗層
170‧‧‧封蓋層
180‧‧‧阻障層
190‧‧‧導電層/導體
A‧‧‧部分
本揭露之態樣最佳在閱讀附圖時根據下文之詳細說明來進行理解。應注意，依據工業中之標準實務，多個特徵並未按比例繪製。實際上，多個特徵之尺寸可任意增大或縮小，以便使論述明晰。
第1A圖至第1F圖是依據本揭露之一些實施例製造互連線結構之方法的不同階段。
第2圖是依據本揭露之一些實施例第1F圖中部分A之放大視圖。
以下揭示內容提供眾多不同的實施例或實例以用於實施本案提供之標的物的不同特徵。下文中描述組件及排列之特定實例以簡化本揭露。此些組件及排列當然僅為實例，及不意欲進行限制。例如，在下文之描述中，第一特徵在第二特徵上方或之上的形成可包括其中第一特徵與第二特徵以直接接觸方式形成的實施例，及亦可包括其中在第一特徵與第二特徵之間形成額外特徵以使得第一特徵與第二特徵無法直接接觸之實施例。此外，本揭露在多個實例中可重複元件符號及/或字母。此重複用於實現簡化與明晰之目的，及其自身並不規定所論述之多個實施例及/或配置之間的關係。
此外，本案中可使用諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等等之空間相對術語在以便於描述，以描述一個元件或特徵與另一或更多個元件或特徵之關係，如圖式中所圖示。空間相對術語意欲包含在使用或操作中之裝置除圖式中繪示之定向以外的不同定向。或者，設備可經定向(旋轉90度或其他定向)，及本案中使用之空間相對描述詞同樣可相應地進行解釋。
積體電路包含由互接線間隔分開的複數個圖案化金屬線。通常，垂直間隔敷金屬層之金屬圖案藉由通孔而電互 連。鑲嵌是一互連線製程，在此製程中，開口形成於絕緣層中及充填金屬以形成金屬線。形成於溝槽狀開口中之金屬線通常大體平行於半導體基板而延伸。此種類型之半導體裝置根據現代技術可包括八個或更多個水平的敷金屬層以滿足裝置幾何形狀及微小型化需求。隨著半導體裝置尺寸持續縮小，互連線結構面臨一些挑戰，因為此等金屬薄膜是具有高阻抗的薄膜，由此導致互連線結構中阻抗增大及RC延遲增長，尤其是在較小、狹窄的特徵中如此。
請參看第1A圖至第1F圖，此等圖式是依據本揭露之一些實施例製造互連線結構之方法的不同階段。請參看第1A圖，開口形成於第一介電層110中。第一介電層110形成於半導體基板(未圖示)上方。半導體基板可為半導體材料及可包括已知結構，此等結構例如包括分級層或埋置氧化物。在一些實施例中，基板包括體矽，此矽可為未經摻雜或經摻雜(例如p型、n型，或兩者之組合)。亦可使用適合於半導體裝置形成之其他材料。諸如鍺、石英、藍寶石及玻璃之其他材料可替代地用於基板。或者，矽基板可為絕緣體上半導體(semiconductor on insulator；SOI)基板之有效層或諸如形成於整塊矽層上的矽鍺層之多層結構。諸如P型金氧半導體及N型金氧半導體電晶體(未圖示)之積體電路可形成於基板頂表面上。
在一些實施例中，第一介電層110是具有低介電常數值(k值)的金屬間介電質(inter-metal dielectric； IMD)，此值例如低於約3.5。第一介電層110可包括介電材料，如氮化矽、氮化矽、氮氧化矽，或其他適合材料。
在一些實施例中，第一介電層110中形成有複數個開口112。開口112可藉由例如以下步驟而形成：在第一介電層110上方形成圖案化光阻劑層(未圖示)，及使用乾燥蝕刻處理步驟以移除第一介電層110之部分，以藉由使用圖案化光阻劑層(未圖示)作為遮蔽來界定開口112。可使用多種適合的乾燥蝕刻製程。在乾燥蝕刻處理步驟之後，藉由例如光微影移除製程而移除圖案化光阻劑層(未圖示)。
請參看第1B圖，導電特徵120形成於開口112中。形成導電特徵120之製程包括形成充填開口112及位於第一介電層110上之導電層，然後移除導電層之積聚在第一介電層110表面上方的多餘部分(未圖示)，以使得導電特徵120存在於開口112中。
導電層可為金屬層。導電層材料可包括銅或銅合金，或其他適合之導電材料，如銀、金、鎢、鋁，等等。導電層可由沉積製程而形成。移除製程可為任何適合的平面化製程，如化學機械拋光(chemical mechanical polishing；CMP)。化學機械製程經執行以整平導電特徵120及第一介電層110之表面。導電特徵120可為導電線，此線可為半導體裝置之第一或任何隨後的金屬互連線位準。
在一些實施例中，因為銅容易擴散至一些介電材料內，尤其是一些類型之低介電常數介電材料，因此在形成導電層之前，視情況在開口112之內表面上方及第一介電層110 表面上方沉積擴散阻障層122。擴散阻障層122可藉由使用諸如化學氣相沉積(chemical vapor deposition；CVD)或物理氣相沉積(physical vapor deposition；PVD)之方法而沉積至約50Å與300Å之間的厚度。擴散阻障層122之金屬阻障材料包括Ta、TaN或TiN。
請參看第1C圖，至少一個蝕刻停止層形成於第一介電層110之上及導電特徵120之上。在一些實施例中，下蝕刻停止層130形成於第一介電層110之上及導電特徵120之上，然後上蝕刻停止層140視情況形成於下蝕刻停止層130之上。下蝕刻停止層130及上蝕刻停止層140由不同材料製成。 下蝕刻停止層130及上蝕刻停止層140可藉由一系列沉積製程而形成。沉積製程可為如化學氣相沉積、物理氣相沉積、原子層沉積(atomic layer deposition；ALD)、遠端電漿增強化學氣相沉積(remote plasma enhanced chemical vapor deposition；RPECVD)、液態源霧狀化學沉積(liquid source misted chemical deposition；LSMCD)、塗覆、旋塗或經調適以在基板上方形成薄膜層的另一製程。
下蝕刻停止層130是低電容材料，用以改良RC延遲。在一些實施例中，下蝕刻停止層130是含鋁層。下蝕刻停止層130之材料可為例如氮化鋁、氮氧化鋁、碳化鋁，或上述各者之組合。如若沉積氮化鋁層以作為下蝕刻停止層130，則此層可由在氮大氣中利用鋁靶材進行反應性濺射(reactive sputtering；RS)而形成。下蝕刻停止層130形成於第一介電層110上及充當蝕刻停止物以用於持續的後段製程(back-end of line；BEOL)敷金屬。下蝕刻停止層130之厚度是薄膜層及處於自5Å至50Å的範圍中。然而，熟習此項技術者將認識到，此描述中整篇列舉的尺寸僅為實例，及將在使用不同的形成技術之情況下變更。
上蝕刻停止層140由不同於下蝕刻停止層130的材料製成。在一些實施例中，上蝕刻停止層140是無鋁層。上蝕刻停止層140可具有低於約4.0之介電常數，或甚至低於約3.5，及可包括選自摻雜氮之(矽)碳化物(SiC：N，亦稱為NDC)、摻雜氧的(矽)碳化物(SiC：O，亦稱為ODC)，及上述各者之組合。反應氣體(前驅物)依據蝕刻停止層之所需組成而定，及可包括矽(Si)、碳(C)、氫(H)、氮(N)、氧(O)、硼(B)，及/或類似物。諸如He、N2、Ar、Xe等等的無活性氣體可用作環境氣體。如若將形成ODC，則亦可添加CO2以提供氧。如若將形成NDC，則可添加NH3以提供氮。上蝕刻停止層140之厚度處於自30Å至1000Å的範圍中。然而，熟習此項技術者將認識到，此描述中整篇列舉的尺寸僅為實例，及將在使用不同的形成技術之情況下變更。
上蝕刻停止層140可利用下蝕刻停止層130之形成而現場形成，此意謂著下蝕刻停止層130及上蝕刻停止層140形成於同一處理腔室中。下蝕刻停止層130及上蝕刻停止層140之沉積可在高溫下執行，例如在約100℃與約500℃之間。
請參看第1D圖，額外的第二介電層150形成於上蝕刻停止層140上。第二介電層150可為金屬間介電質 (inter-metal dielectric；IMD)層。第二介電層150可為單層或多層結構。第二介電層150之厚度隨所應用技術而變化，例如約1000Å至約30000Å之厚度。然而，熟習此項技術者將認識到，此描述中整篇列舉的尺寸僅為實例，及將在使用不同的形成技術之情況下變更。
在一些實施例中，第二介電層150是含氧介電層。第二介電層150可由SiO2、摻雜碳的SiO2、相對低介電常數(k值)的介電材料(此介電材料具有小於約4.0之介電常數值)，或上述各者之組合而形成。第二介電層150可由低介電常數介電材料、極低介電常數介電材料、多孔低介電常數介電層，或上述各者之組合而形成。術語「低介電常數」意欲定義3.0或更小的介電材料介電常數。術語「極低介電常數(extreme low k；ELK)」意謂著2.5或更小介電常數。術語「多孔低介電常數」係指2.0或更小的介電材料介電常數。依據實施例可使用多種低介電常數材料，例如旋塗無機介電質、旋塗有機介電質、多孔介電材料、有機聚合物、有機氧化矽玻璃、FSG(SiOF物種材料)、HSQ(氫倍半氧矽烷)物種材料、MSQ(甲基倍半氧矽烷)物種材料，或多孔有機物種材料。第二介電層150經由多種技術中任何技術而沉積，此等技術如化學氣相沉積、物理氣相沉積、原子層沉積、RPECVD、LSMCD、塗覆、旋塗或經調適以在基板上方形成薄膜層之另一製程。
抗反射塗層(anti-reflective coating；ARC)160及封蓋層170可視情況沉積在第二介電層150上。抗反射塗層 160可為無氮抗反射膜層(nitrogen free anti-reflective coating layer；NFARL)及封蓋層170可為氮化鈦(TiN))層或氮化鉭(TaN)層。抗反射塗層160及封蓋層170可由任何適合的沉積製程而形成。在一些實施例中，抗反射塗層160及封蓋層170之合成物被視作障壁及抗反射膜(barrier and anti-reflective coating；BARC)層。在一些其他實施例中，封蓋層170可用作蝕刻停止物以用於隨後在形成半導體裝置時進行處理。
請參看第1E圖，孔洞152形成於上述結構中。孔洞152可為示例性雙鑲嵌開口，此開口包括上溝槽區段151及下通孔孔洞區段153，此等區段在結構中經圖案化以在基板中界定接觸區域。在包括圖案化方法之雙鑲嵌技術中，上溝槽區段151及下通孔孔洞區段153可藉由使用典型微影術而形成，此微影術具有遮蔽技術及各向異性蝕刻操作(例如電漿蝕刻或反應性離子蝕刻)。
例如，上溝槽區段151可藉由使用第一遮蔽層(未圖示)連同適合蝕刻製程而形成。遮蔽層可為硬質遮罩層，此層包括經由諸如CVD製程之製程而形成的氮化矽，但亦可替代性地使用諸如氧化物、氮氧化物、碳化矽、上述各者之組合或類似物之其他材料及諸如電漿增強化學氣相沉積、低壓化學氣相沉積，或甚至氧化矽形成後再進行氮化之其他製程。一旦形成，遮蔽層可由適合光微影製程經圖案化以曝露下層層中將被移除以形成上溝槽區段151之彼等部分。上溝槽區段151可由執行乾式蝕刻製程而形成，如電漿蝕刻或反應性離子蝕刻。 中間的蝕刻停止層可視情況中間沉積在第二介電層150中以提供明晰指示，指示何時結束特定之蝕刻製程。在形成上溝槽區段151之後移除遮蔽層。
上溝槽區段151下方之第二介電層150經圖案化以在上溝槽區段151下方形成下通孔孔洞區段153。例如，在上溝槽區段151之預定位置旁邊的部分再次受到另一遮蔽層保護。由此，第二介電層150中用於形成下通孔孔洞區段153之部分從遮蔽層中曝露。第二介電層150之曝露部分由執行乾式蝕刻製程而移除，如電漿蝕刻或反應性離子蝕刻。下通孔孔洞區段153比上溝槽區段151具有更高的深寬比，下通孔孔洞區段153之寬度小於上溝槽區段151之寬度。在形成下通孔孔洞區段153之後移除遮蔽層。
孔洞152穿透第二介電層150、抗反射塗層160、封蓋層170、上蝕刻停止層140，及下蝕刻停止層130而形成。因此，導電特徵120自孔洞152曝露。儘管實施例圖示第二介電層150中之雙鑲嵌開口，但使用在第二介電層150中之單鑲嵌開口亦提供價值。
因為孔洞152藉由執行一或更多個乾式蝕刻製程而形成，上述層曝露於離子轟擊(例如諸如氟碳化物、氧、氯之反應性氣體的電漿)。從曝露表面驅除層之材料，及層之材料重新濺射在孔洞152側壁上。例如，下蝕刻停止層130是含鋁蝕刻停止層，此含鋁蝕刻停止層是低電容材料，用以改良互連線結構之RC延遲。鋁較為輕質，及具有與介電材料的優良黏合能力。因此，來自驅除的下蝕刻停止層130材料之一些含 鋁碎片132存在於孔洞152之側壁之底部部分，如存在於下通孔孔洞區段153之底部部分。換言之，在乾式蝕刻製程期間，下蝕刻停止層130之一部分被離子轟擊離開而變為含鋁碎片132，及含鋁碎片132之一部分黏著在第二介電層150之側壁及孔洞152之底部轉角處。
含鋁碎片132在孔洞152之側壁及底部轉角上之分佈對應於與導電特徵120之距離。例如，含鋁碎片132在孔洞152之側壁底部部分具有更大密度，及含鋁碎片132之密度隨與導電特徵120之距離增長而減少。在一些實施例中，含鋁碎片132可在第二介電層150與導電特徵120之間的轉角處具有最大密度。
請參看第1F圖，阻障層180形成於孔洞152之側壁上。阻障層180沉積在孔洞152之內表面上方及第二介電層150表面上方。阻障層180可藉由使用諸如化學氣相沉積或物理氣相沉積之方法而沉積至約50Å與300Å之間的厚度。銅用作互連線介質，並日益獲得認可及越來越用於此目的。銅已知具有低成本及低電阻率；然而銅在諸如二氧化矽及矽之介電材料內具有相對大的擴散係數。阻障層180用於防止以下諸如銅或銅合金之沉積導電金屬擴散至第二介電層150內。阻障層180由實質上無鋁的材料製成。阻障層180之金屬阻障材料包括Ta、TaN或TiN。
在一些實施例中，較薄種晶層視情況形成於阻障層180上。種晶層具有一厚度，此厚度為約100Å至約1000Å。種晶層是包含至少一主金屬元素及第一添加金屬元素的金屬 合金層，此主金屬元素例如為銅(Cu)，及此添加金屬元素例如為錳(Mn)。在其他實施例中，Ti、Nb、Cr、V、Y、Tc、Re或類似物可用作另一添加金屬以用於形成種晶層。種晶層可藉由使用物理氣相沉積、化學氣相沉積、電漿增強化學氣相沉積、低壓化學氣相沉積，或其他的沉積技術而沉積。種晶層用於改良以下沉積製程的數量。
諸如雙鑲嵌開口之孔洞152充填導電材料。執行電化學銅沉積(electrochemical copper deposition；ECD)以在阻障層180上(或在種晶層上)形成導電層190及充填孔洞152。利用導電材料充填包括上溝槽區段151及下通孔孔洞區段153之孔洞152，使阻障層180至少部分位於導電層190與第二介電層150之間。導電層190可為金屬層。導電層190之材料可包括銅或銅合金，或其他適合之導電材料，如銀、金、鎢等等。在一些實施例中，導電層190由實質上無鋁的材料製成。阻障層180可充當保護裝置以保護導電層190不擴散至第二介電層150內。由於電化學銅沉積之更大粒徑(優良電遷移)及高沉積速率，電化學銅沉積已被採用用於銅敷金屬。然而，諸如電子化學電鍍之電化學銅沉積製程是濕式製程及在孔洞152中產生空隙之形成。此外，空隙中亦可能截留電解質，從而產生可靠性問題。
此外，在導電層190形成之後，對上述結構執行熱處理，例如退火製程。在一些實施例中，在導電層190形成之後立即提供熱處理步驟。在一些其他實施例中，在移除孔洞152外部的導電層190多餘部分之CMP步驟之後，立即提供熱 處理步驟。退火製程溫度之範圍可自約50℃至400℃。退火製程之歷時之範圍可自約5分鐘至60分鐘。
在形成充填孔洞152的導電層190之後，執行化學機械拋光製程以移除導電層190的多餘部分，及孔洞152外部的阻障層180，由此曝露封蓋層170之頂表面及獲得平面化表面。孔洞152中的殘餘導電層190被視作導體(在下文中被稱作導體190)。孔洞152及其中的導體190被視作用於互連線至導電特徵120的導電通孔。在一些實施例中，含鋁碎片132至少存在於導電通孔之底部轉角處。在一些實施例中，導電通孔之側壁具有底部部分及中間部分，此底部部分比中間部分更靠近下蝕刻停止層130，及導電通孔之側壁之底部部分上之含鋁碎片132之密度大於導電通孔之側壁之中間部分上的含鋁碎片132密度。請參看第2圖及第1F圖，其中第2圖是依據本揭露之一些實施例的第1F圖中部分A之放大視圖。在退火及平面化之後，例如化學機械拋光之後，導體190具有更低阻抗及更佳電遷移壽命。然而，不僅電化學銅沉積製程可在導體190中形成空隙，退火製程亦可導致空隙之形成。退火製程期間的應力使導體190變形及導致額外空隙形成於導體190與阻障層180之間的界面處。空隙之存在可減少孔洞152中導電材料之量，由此提高導體190阻抗，此亦可增長半導體裝置之RC延遲。
在本揭露之一些實施例中，用於BOEL之蝕刻停止層，如下蝕刻停止層130，是可改良RC延遲的低電容材料製成的。因為通孔由乾式蝕刻製程而形成，因此蝕刻停止層之一部分由離子轟擊及從曝露表面驅除，及可黏著在通孔側壁上及 通孔轉角處。在一些實施例中，用於蝕刻停止層之低電容材料為含鋁材料，如氮化鋁、氮氧化鋁、碳化鋁，或上述各者之組合。鋁較為輕質，及具有與介電材料的優良黏合能力。因此，來自驅除的下蝕刻停止層130材料之一些含鋁碎片132黏著於孔洞152之側壁之底部部分，及孔洞152之底部轉角處。含鋁碎片132可充當額外障壁以防止導體190逸散。
前述內容概括數個實施例之特徵，以便彼等熟習此項技術者可更佳地理解本揭露之態樣。彼等熟習此項技術者應瞭解，本揭露可易於用作設計或修正其他製程及結構之基礎，以實現與本案介紹之實施例相同的目的及/或達到與其相同的優勢。彼等熟習此項技術者亦應瞭解，此種同等構造不脫離本揭露之精神及範疇，及可在不脫離本揭露精神及範疇之情況下在本案中進行多種變更、取代及更動。
110‧‧‧介電層
120‧‧‧導電特徵
130‧‧‧下蝕刻停止層
140‧‧‧上蝕刻停止層
150‧‧‧額外介電層
151‧‧‧上溝槽區段
152‧‧‧孔洞
153‧‧‧下通孔孔洞區段
160‧‧‧抗反射塗層
170‧‧‧封蓋層
180‧‧‧阻障層
190‧‧‧導電層/導體
A‧‧‧部分

Claims (10)

  1. 一種互連線結構，包括：一第一介電層；一導電特徵，存在於該第一介電層中；一第二介電層，存在於該第一介電層上，且具有一孔洞；一導體，存在於該孔洞中及電連接至該導電特徵；以及複數個含鋁碎片，至少部分地存在於該孔洞之至少一個側壁上，其中該孔洞之該側壁之底部的該些含鋁碎片之密度大於該孔洞之該側壁之中部的該些含鋁碎片之密度。
  2. 如請求項1所述之互連線結構，更包括：一含鋁蝕刻停止層，存在於該第一介電層與該第二介電層之間。
  3. 如請求項2所述之互連線結構，其中該含鋁蝕刻停止層之材料為氮化鋁、氮氧化鋁、碳化鋁或其組合。
  4. 如請求項1所述之互連線結構，其中該孔洞具有至少一個底部轉角，該些含鋁碎片中之至少一者存在於該孔洞之該底部轉角。
  5. 如請求項1所述之互連線結構，更包含一阻障層，至少部分存在於該導體與該第二介電層之間。
  6. 如請求項1所述之互連線結構，其中該導體由一實質上無鋁的材料製成。
  7. 一種互連線結構，包括：一第一介電層；一導電特徵，存在於該第一介電層中；一第二介電層，存在於該第一介電層上；一含鋁蝕刻停止層，存在於該第一介電層與該第二介電層之間；一導電通孔，至少存在於該第二介電層中且電連接至該導電特徵；以及至少一個含鋁碎片，至少存在於該導電通孔之一底部轉角處。
  8. 如請求項7所述之互連線結構，其中複數個該含鋁碎片存在於該導電通孔之至少一個側壁上。
  9. 如請求項8所述之互連線結構，其中該導電通孔之該側壁具有一底部部分及一中間部分，該底部部分比該中間部分更靠近該含鋁蝕刻停止層，該導電通孔之該側壁之該底部部分上之該些含鋁碎片之密度大於該導電通孔之該側壁之該中間部分上的該些含鋁碎片之密度。
  10. 一種用於製造一互連線結構的方法，包括：在一第一介電層中形成一導電特徵； 在該導電特徵及該第一介電層上形成一含鋁蝕刻停止層；在該含鋁蝕刻停止層上形成一第二介電層；以及蝕刻該第二介電層及該含鋁蝕刻停止層以在該第二介電層及該含鋁蝕刻停止層中形成一孔洞，其中該導電特徵至少部分地由該孔洞曝露，該蝕刻該含鋁蝕刻停止層之步驟使得至少一個含鋁碎片重新濺射在該孔洞之至少一個側壁上。
TW105127113A 2015-12-21 2016-08-24 互連線結構與其製造方法 TWI611545B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562270468P 2015-12-21 2015-12-21
US62/270,468 2015-12-21
US15/145,369 US9837306B2 (en) 2015-12-21 2016-05-03 Interconnection structure and manufacturing method thereof
US15/145,369 2016-05-03

Publications (2)

Publication Number Publication Date
TW201724436A TW201724436A (zh) 2017-07-01
TWI611545B true TWI611545B (zh) 2018-01-11

Family

ID=59066379

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105127113A TWI611545B (zh) 2015-12-21 2016-08-24 互連線結構與其製造方法

Country Status (3)

Country Link
US (4) US9837306B2 (zh)
CN (1) CN106898595B (zh)
TW (1) TWI611545B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI721643B (zh) * 2018-11-30 2021-03-11 台灣積體電路製造股份有限公司 積體晶片的互連結構及其形成方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9837306B2 (en) * 2015-12-21 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and manufacturing method thereof
US10522468B2 (en) 2017-07-31 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US10790362B2 (en) * 2017-11-30 2020-09-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method of the same
CN110875320B (zh) * 2018-08-29 2022-02-11 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10978337B2 (en) * 2018-09-18 2021-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Aluminum-containing layers and methods of forming the same
US11322397B2 (en) * 2018-10-30 2022-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices including formation of adhesion enhancement layer
US11502001B2 (en) * 2018-10-31 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with self-aligned vias
US11037822B2 (en) 2019-05-08 2021-06-15 International Business Machines Corporation Svia using a single damascene interconnect
US11482454B2 (en) * 2021-02-17 2022-10-25 Tokyo Electron Limited Methods for forming self-aligned contacts using spin-on silicon carbide
KR20220153175A (ko) 2021-05-10 2022-11-18 삼성전자주식회사 반도체 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194739A (zh) * 2010-03-15 2011-09-21 台湾积体电路制造股份有限公司 内连线结构的形成方法
TWM489420U (en) * 2014-02-21 2014-11-01 Ya-Ling Zhang Power generation device capable of reducing occupation area
TW201532226A (zh) * 2013-12-30 2015-08-16 Taiwan Semiconductor Mfg Co Ltd 互連結構及其製造方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525542A (en) * 1995-02-24 1996-06-11 Motorola, Inc. Method for making a semiconductor device having anti-reflective coating
US5702981A (en) * 1995-09-29 1997-12-30 Maniar; Papu D. Method for forming a via in a semiconductor device
US7547669B2 (en) * 1998-07-06 2009-06-16 Ekc Technology, Inc. Remover compositions for dual damascene system
US6372653B1 (en) * 2000-07-07 2002-04-16 Taiwan Semiconductor Manufacturing Co., Ltd Method of forming dual damascene structure
US6492272B1 (en) * 2001-02-15 2002-12-10 Advanced Micro Devices, Inc. Carrier gas modification for use in plasma ashing of photoresist
US6586842B1 (en) * 2001-02-28 2003-07-01 Advanced Micro Devices, Inc. Dual damascene integration scheme for preventing copper contamination of dielectric layer
US7164206B2 (en) * 2001-03-28 2007-01-16 Intel Corporation Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
GB0117250D0 (en) * 2001-07-14 2001-09-05 Trikon Holdings Ltd Method of forming a conductive interconnect
US20050095869A1 (en) * 2003-11-05 2005-05-05 Hun-Jan Tao Low K dielectric surface damage control
KR100621548B1 (ko) * 2004-07-30 2006-09-14 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
EP1820214A2 (en) * 2004-12-01 2007-08-22 Koninklijke Philips Electronics N.V. A method of forming an interconnect structure on an integrated circuit die
US7445943B2 (en) * 2006-10-19 2008-11-04 Everspin Technologies, Inc. Magnetic tunnel junction memory and method with etch-stop layer
WO2009057660A1 (ja) 2007-11-01 2009-05-07 Ulvac Coating Corporation ハーフトーンマスク、ハーフトーンマスクブランクス、及びハーフトーンマスクの製造方法
US8282842B2 (en) * 2007-11-29 2012-10-09 United Microelectronics Corp. Cleaning method following opening etch
US20100252930A1 (en) 2009-04-01 2010-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Improving Performance of Etch Stop Layer
US9059250B2 (en) * 2012-02-17 2015-06-16 International Business Machines Corporation Lateral-dimension-reducing metallic hard mask etch
US9023219B2 (en) * 2012-04-26 2015-05-05 Everspin Technologies, Inc. Method of manufacturing a magnetoresistive device
US20140212993A1 (en) * 2013-01-31 2014-07-31 Everspin Technologies, Inc. Method of manufacturing a magnetoresistive device
CN104051256B (zh) * 2013-03-14 2018-04-17 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US9129965B2 (en) * 2013-03-14 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9269809B2 (en) * 2013-03-14 2016-02-23 Globalfoundries Inc. Methods for forming protection layers on sidewalls of contact etch stop layers
US9941214B2 (en) * 2013-08-15 2018-04-10 Taiwan Semiconductor Manufacturing Company Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures
US9437484B2 (en) * 2014-10-17 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Etch stop layer in integrated circuits
KR102399345B1 (ko) * 2014-11-12 2022-05-19 삼성전자주식회사 반도체 장치의 제조 방법
US9496169B2 (en) * 2015-02-12 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect structure having an air gap and structure thereof
US20160372413A1 (en) * 2015-06-17 2016-12-22 Globalfoundries Inc. Unique bi-layer etch stop to protect conductive structures during a metal hard mask removal process and methods of using same
US9515021B1 (en) * 2015-10-20 2016-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method of forming the same
US20170162430A1 (en) * 2015-12-03 2017-06-08 GlobalFoundries, Inc. Methods for producing integrated circuits with air gaps and integrated circuits produced from such methods
US9837306B2 (en) * 2015-12-21 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194739A (zh) * 2010-03-15 2011-09-21 台湾积体电路制造股份有限公司 内连线结构的形成方法
TW201532226A (zh) * 2013-12-30 2015-08-16 Taiwan Semiconductor Mfg Co Ltd 互連結構及其製造方法
TWM489420U (en) * 2014-02-21 2014-11-01 Ya-Ling Zhang Power generation device capable of reducing occupation area

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI721643B (zh) * 2018-11-30 2021-03-11 台灣積體電路製造股份有限公司 積體晶片的互連結構及其形成方法

Also Published As

Publication number Publication date
US9837306B2 (en) 2017-12-05
CN106898595A (zh) 2017-06-27
CN106898595B (zh) 2020-02-07
US20180102283A1 (en) 2018-04-12
US10510588B2 (en) 2019-12-17
US20200251383A1 (en) 2020-08-06
US20170178954A1 (en) 2017-06-22
US10854508B2 (en) 2020-12-01
US20200118869A1 (en) 2020-04-16
TW201724436A (zh) 2017-07-01

Similar Documents

Publication Publication Date Title
TWI611545B (zh) 互連線結構與其製造方法
US20220173042A1 (en) Interconnect Structure with Vias Extending Through Multiple Dielectric Layers
US9941199B2 (en) Two step metallization formation
US7998855B2 (en) Solving via-misalignment issues in interconnect structures having air-gaps
JP4956919B2 (ja) 半導体装置およびその製造方法
US9064934B2 (en) Barrier layer for copper interconnect
US20170018458A1 (en) Method for cleaning via of interconnect structure of semiconductor device structure
US11984355B2 (en) Method for manufacturing an interconnection structure having a bottom via spacer
US9824918B2 (en) Method for electromigration and adhesion using two selective deposition
US9966339B2 (en) Barrier structure for copper interconnect
TW201727709A (zh) 具有楔形鑲嵌孔洞之半導體結構及其製造方法
US10535560B2 (en) Interconnection structure of semiconductor device
US20240071815A1 (en) Method for forming interconnect structure
TW201820562A (zh) 半導體裝置的形成方法
US20120199980A1 (en) Integrated circuits having interconnect structures and methods for fabricating integrated circuits having interconnect structures
JP5326949B2 (ja) 半導体装置
US11929329B2 (en) Damascene process using cap layer
CN108573912B (zh) 半导体结构及其形成方法
US8742587B1 (en) Metal interconnection structure
CN112435958B (zh) 集成电路结构及其形成方法
KR20070033175A (ko) 반도체 장치의 금속 배선 형성 방법
KR20100073779A (ko) 반도체 소자의 금속배선 및 그 제조 방법