JP2018531506A5 - - Google Patents
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- JP2018531506A5 JP2018531506A5 JP2018515554A JP2018515554A JP2018531506A5 JP 2018531506 A5 JP2018531506 A5 JP 2018531506A5 JP 2018515554 A JP2018515554 A JP 2018515554A JP 2018515554 A JP2018515554 A JP 2018515554A JP 2018531506 A5 JP2018531506 A5 JP 2018531506A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- line
- different
- different materials
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims 70
- 238000000034 method Methods 0.000 claims 22
- 125000006850 spacer group Chemical group 0.000 claims 12
- 239000000758 substrate Substances 0.000 claims 9
- 239000002131 composite material Substances 0.000 claims 7
- 238000000059 patterning Methods 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 230000003287 optical effect Effects 0.000 claims 1
- 230000003252 repetitive effect Effects 0.000 claims 1
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562232005P | 2015-09-24 | 2015-09-24 | |
| US62/232,005 | 2015-09-24 | ||
| US201562258119P | 2015-11-20 | 2015-11-20 | |
| US62/258,119 | 2015-11-20 | ||
| PCT/US2016/052694 WO2017053316A1 (en) | 2015-09-24 | 2016-09-20 | Methods of forming etch masks for sub-resolution substrate patterning |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018531506A JP2018531506A (ja) | 2018-10-25 |
| JP2018531506A6 JP2018531506A6 (ja) | 2018-12-13 |
| JP2018531506A5 true JP2018531506A5 (enExample) | 2019-10-31 |
Family
ID=58386992
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018515554A Pending JP2018531506A (ja) | 2015-09-24 | 2016-09-20 | サブ解像度基板パターニングのためのエッチングマスクを形成する方法 |
| JP2018515551A Active JP6726834B2 (ja) | 2015-09-24 | 2016-09-20 | サブ解像度基板パターニングのためのエッチングマスクを形成する方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018515551A Active JP6726834B2 (ja) | 2015-09-24 | 2016-09-20 | サブ解像度基板パターニングのためのエッチングマスクを形成する方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US10020196B2 (enExample) |
| JP (2) | JP2018531506A (enExample) |
| KR (2) | KR102705674B1 (enExample) |
| CN (2) | CN108292591A (enExample) |
| TW (2) | TWI620995B (enExample) |
| WO (2) | WO2017053296A1 (enExample) |
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| US9991156B2 (en) | 2016-06-03 | 2018-06-05 | International Business Machines Corporation | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs |
| US10629435B2 (en) | 2016-07-29 | 2020-04-21 | Lam Research Corporation | Doped ALD films for semiconductor patterning applications |
| US10002762B2 (en) * | 2016-09-09 | 2018-06-19 | International Business Machines Corporation | Multi-angled deposition and masking for custom spacer trim and selected spacer removal |
| US9911619B1 (en) * | 2016-10-12 | 2018-03-06 | Globalfoundries Inc. | Fin cut with alternating two color fin hardmask |
| US10832908B2 (en) * | 2016-11-11 | 2020-11-10 | Lam Research Corporation | Self-aligned multi-patterning process flow with ALD gapfill spacer mask |
| US10454029B2 (en) | 2016-11-11 | 2019-10-22 | Lam Research Corporation | Method for reducing the wet etch rate of a sin film without damaging the underlying substrate |
| US9881794B1 (en) * | 2016-11-29 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor methods and devices |
| US10388644B2 (en) | 2016-11-29 | 2019-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing conductors and semiconductor device which includes conductors |
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| US20180323061A1 (en) * | 2017-05-03 | 2018-11-08 | Tokyo Electron Limited | Self-Aligned Triple Patterning Process Utilizing Organic Spacers |
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| US10269559B2 (en) | 2017-09-13 | 2019-04-23 | Lam Research Corporation | Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer |
| CN109545684B (zh) * | 2017-09-22 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| US10340364B2 (en) * | 2017-11-14 | 2019-07-02 | International Business Machines Corporation | H-shaped VFET with increased current drivability |
| US10566207B2 (en) * | 2017-12-27 | 2020-02-18 | Samsung Electronics Co., Ltd. | Semiconductor manufacturing methods for patterning line patterns to have reduced length variation |
| WO2019169335A1 (en) | 2018-03-02 | 2019-09-06 | Lam Research Corporation | Selective deposition using hydrolysis |
| US10395926B1 (en) * | 2018-04-17 | 2019-08-27 | Globalfoundries Inc. | Multiple patterning with mandrel cuts formed using a block mask |
| JP2019204815A (ja) * | 2018-05-21 | 2019-11-28 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
| US10643846B2 (en) | 2018-06-28 | 2020-05-05 | Lam Research Corporation | Selective growth of metal-containing hardmask thin films |
| US10763118B2 (en) * | 2018-07-11 | 2020-09-01 | International Business Machines Corporation | Cyclic selective deposition for tight pitch patterning |
| US10910381B2 (en) * | 2018-08-01 | 2021-02-02 | Applied Materials, Inc. | Multicolor approach to DRAM STI active cut patterning |
| CN110911272B (zh) * | 2018-09-17 | 2024-05-03 | 长鑫存储技术有限公司 | 在半导体器件中形成微图案的方法 |
| US11164772B2 (en) * | 2018-10-30 | 2021-11-02 | International Business Machines Corporation | Spacer-defined process for lithography-etch double patterning for interconnects |
| EP3660890B1 (en) | 2018-11-27 | 2021-08-11 | IMEC vzw | A method for forming an interconnection structure |
| CN111370309B (zh) * | 2018-12-26 | 2023-12-12 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| CN111640655B (zh) * | 2019-03-01 | 2023-04-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| US10943816B2 (en) | 2019-04-03 | 2021-03-09 | International Business Machines Corporation | Mask removal for tight-pitched nanostructures |
| US11315787B2 (en) * | 2019-04-17 | 2022-04-26 | Applied Materials, Inc. | Multiple spacer patterning schemes |
| CN111952165B (zh) * | 2019-05-17 | 2025-03-18 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| KR102837863B1 (ko) | 2019-06-04 | 2025-07-23 | 램 리써치 코포레이션 | 패터닝시 반응성 이온 에칭을 위한 중합 보호 라이너 |
| KR20220042442A (ko) | 2019-08-06 | 2022-04-05 | 램 리써치 코포레이션 | 실리콘-함유 막들의 열적 원자 층 증착 (thermal atomic layer deposition) |
| CN112017970B (zh) * | 2020-07-24 | 2022-09-20 | 中国科学院微电子研究所 | 自对准金属层的制造方法、半导体器件及电子设备 |
| TW202223133A (zh) | 2020-07-28 | 2022-06-16 | 美商蘭姆研究公司 | 含矽膜中的雜質減量 |
| CN114334801A (zh) * | 2020-09-30 | 2022-04-12 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
| US11990409B2 (en) | 2021-04-19 | 2024-05-21 | Samsung Electronics Co., Ltd. | Semiconductor device with fine metal lines for BEOL structure and method of manufacturing the same |
| KR20240032126A (ko) | 2021-07-09 | 2024-03-08 | 램 리써치 코포레이션 | 실리콘-함유 막들의 플라즈마 강화 원자 층 증착 |
| US12451354B2 (en) | 2022-09-09 | 2025-10-21 | Tokyo Electron Limited | Double patterning method of patterning a substrate |
| CN118039463B (zh) * | 2024-01-19 | 2024-10-29 | 深圳市鹏芯微集成电路制造有限公司 | 掩膜的制造方法和半导体器件的制造方法 |
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| US5223083A (en) * | 1992-01-23 | 1993-06-29 | Micron Technology, Inc. | Process for etching a semiconductor device using an improved protective etching mask |
| JP2827882B2 (ja) * | 1994-02-24 | 1998-11-25 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6632741B1 (en) | 2000-07-19 | 2003-10-14 | International Business Machines Corporation | Self-trimming method on looped patterns |
| US7190007B2 (en) * | 2004-08-05 | 2007-03-13 | International Business Machines Corporation | Isolated fully depleted silicon-on-insulator regions by selective etch |
| US7560390B2 (en) * | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
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| KR100718782B1 (ko) * | 2005-11-11 | 2007-05-16 | 매그나칩 반도체 유한회사 | 이미지 센서 제조방법 |
| KR101348280B1 (ko) * | 2007-07-06 | 2014-01-10 | 삼성전자주식회사 | 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법 |
| US8852851B2 (en) * | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
| US7611980B2 (en) * | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
| US7666578B2 (en) * | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
| KR20080034234A (ko) * | 2006-10-16 | 2008-04-21 | 삼성전자주식회사 | 반도체 장치의 미세 패턴 형성 방법 |
| WO2008115600A1 (en) * | 2007-03-21 | 2008-09-25 | Olambda, Inc. | Multi-material hard mask or prepatterned layer for use with multi-patterning photolithography |
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| JP2010080625A (ja) * | 2008-09-25 | 2010-04-08 | Toshiba Corp | マスクパターンの形成方法および半導体装置の製造方法 |
| JP4825891B2 (ja) * | 2009-03-31 | 2011-11-30 | 株式会社東芝 | 半導体装置の製造方法およびテンプレート |
| KR101732936B1 (ko) * | 2011-02-14 | 2017-05-08 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
| CN102693898B (zh) * | 2011-03-21 | 2016-02-24 | 华邦电子股份有限公司 | 缩小间距的方法 |
| JP2013161987A (ja) * | 2012-02-06 | 2013-08-19 | Toshiba Corp | パターン形成方法 |
| US9034197B2 (en) * | 2012-09-13 | 2015-05-19 | HGST Netherlands B.V. | Method for separately processing regions on a patterned medium |
| US9153477B2 (en) * | 2012-09-28 | 2015-10-06 | Intel Corporation | Directed self assembly of block copolymers to form vias aligned with interconnects |
| CN103715068A (zh) * | 2012-09-29 | 2014-04-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体精细图案的形成方法 |
| US8871651B1 (en) * | 2013-07-12 | 2014-10-28 | Globalfoundries Inc. | Mask formation processing |
| US9041217B1 (en) * | 2013-12-18 | 2015-05-26 | Intel Corporation | Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects |
| US9209077B2 (en) * | 2013-12-20 | 2015-12-08 | Intel Corporation | Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects |
| KR102176758B1 (ko) * | 2014-02-10 | 2020-11-10 | 에스케이하이닉스 주식회사 | 블록 코폴리머를 이용한 패턴 형성을 위한 구조 및 패턴 형성 방법 |
| US9240329B2 (en) * | 2014-02-23 | 2016-01-19 | Tokyo Electron Limited | Method for multiplying pattern density by crossing multiple patterned layers |
| CN103943468A (zh) * | 2014-05-08 | 2014-07-23 | 上海华力微电子有限公司 | 一种图形自对准形成方法 |
-
2016
- 2016-09-20 WO PCT/US2016/052668 patent/WO2017053296A1/en not_active Ceased
- 2016-09-20 KR KR1020187011023A patent/KR102705674B1/ko active Active
- 2016-09-20 JP JP2018515554A patent/JP2018531506A/ja active Pending
- 2016-09-20 CN CN201680067813.XA patent/CN108292591A/zh active Pending
- 2016-09-20 US US15/270,841 patent/US10020196B2/en active Active
- 2016-09-20 US US15/270,717 patent/US9818611B2/en active Active
- 2016-09-20 JP JP2018515551A patent/JP6726834B2/ja active Active
- 2016-09-20 WO PCT/US2016/052694 patent/WO2017053316A1/en not_active Ceased
- 2016-09-20 CN CN201680067753.1A patent/CN108352304B/zh active Active
- 2016-09-20 KR KR1020187010710A patent/KR102436100B1/ko active Active
- 2016-09-22 TW TW105130524A patent/TWI620995B/zh active
- 2016-09-22 TW TW105130522A patent/TWI622861B/zh active
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