JP2018531506A - サブ解像度基板パターニングのためのエッチングマスクを形成する方法 - Google Patents

サブ解像度基板パターニングのためのエッチングマスクを形成する方法 Download PDF

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JP2018531506A
JP2018531506A JP2018515554A JP2018515554A JP2018531506A JP 2018531506 A JP2018531506 A JP 2018531506A JP 2018515554 A JP2018515554 A JP 2018515554A JP 2018515554 A JP2018515554 A JP 2018515554A JP 2018531506 A JP2018531506 A JP 2018531506A
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layer
line
forming
pattern
different
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JP2018531506A5 (enExample
JP2018531506A6 (ja
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ジェイ． デヴィリアーズ，アントン
ジェイ． デヴィリアーズ，アントン
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2018515554A 2015-09-24 2016-09-20 サブ解像度基板パターニングのためのエッチングマスクを形成する方法 Pending JP2018531506A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562232005P 2015-09-24 2015-09-24
US62/232,005 2015-09-24
US201562258119P 2015-11-20 2015-11-20
US62/258,119 2015-11-20
PCT/US2016/052694 WO2017053316A1 (en) 2015-09-24 2016-09-20 Methods of forming etch masks for sub-resolution substrate patterning

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JP2018531506A true JP2018531506A (ja) 2018-10-25
JP2018531506A6 JP2018531506A6 (ja) 2018-12-13
JP2018531506A5 JP2018531506A5 (enExample) 2019-10-31

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JP2018515551A Active JP6726834B2 (ja) 2015-09-24 2016-09-20 サブ解像度基板パターニングのためのエッチングマスクを形成する方法

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US (2) US10020196B2 (enExample)
JP (2) JP2018531506A (enExample)
KR (2) KR102705674B1 (enExample)
CN (2) CN108292591A (enExample)
TW (2) TWI620995B (enExample)
WO (2) WO2017053296A1 (enExample)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
JP6715415B2 (ja) * 2016-01-29 2020-07-01 東京エレクトロン株式会社 メモリフィンパターンを形成するための方法及びシステム
US9991156B2 (en) 2016-06-03 2018-06-05 International Business Machines Corporation Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
US10629435B2 (en) 2016-07-29 2020-04-21 Lam Research Corporation Doped ALD films for semiconductor patterning applications
US10002762B2 (en) * 2016-09-09 2018-06-19 International Business Machines Corporation Multi-angled deposition and masking for custom spacer trim and selected spacer removal
US9911619B1 (en) * 2016-10-12 2018-03-06 Globalfoundries Inc. Fin cut with alternating two color fin hardmask
US10832908B2 (en) * 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10454029B2 (en) 2016-11-11 2019-10-22 Lam Research Corporation Method for reducing the wet etch rate of a sin film without damaging the underlying substrate
US9881794B1 (en) * 2016-11-29 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor methods and devices
US10388644B2 (en) 2016-11-29 2019-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing conductors and semiconductor device which includes conductors
CN110337715B (zh) * 2016-12-23 2023-08-25 英特尔公司 高级光刻和自组装装置
US9934970B1 (en) * 2017-01-11 2018-04-03 International Business Machines Corporation Self aligned pattern formation post spacer etchback in tight pitch configurations
US10217633B2 (en) * 2017-03-13 2019-02-26 Globalfoundries Inc. Substantially defect-free polysilicon gate arrays
CN108735585B (zh) * 2017-04-17 2019-06-28 联华电子股份有限公司 掩模图案的制作方法
US10304728B2 (en) * 2017-05-01 2019-05-28 Advanced Micro Devices, Inc. Double spacer immersion lithography triple patterning flow and method
US20180323061A1 (en) * 2017-05-03 2018-11-08 Tokyo Electron Limited Self-Aligned Triple Patterning Process Utilizing Organic Spacers
CN109216163A (zh) * 2017-06-29 2019-01-15 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
US10147611B1 (en) * 2017-08-28 2018-12-04 Nanya Technology Corporation Method for preparing semiconductor structures
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
CN109545684B (zh) * 2017-09-22 2020-11-27 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10340364B2 (en) * 2017-11-14 2019-07-02 International Business Machines Corporation H-shaped VFET with increased current drivability
US10566207B2 (en) * 2017-12-27 2020-02-18 Samsung Electronics Co., Ltd. Semiconductor manufacturing methods for patterning line patterns to have reduced length variation
WO2019169335A1 (en) 2018-03-02 2019-09-06 Lam Research Corporation Selective deposition using hydrolysis
US10395926B1 (en) * 2018-04-17 2019-08-27 Globalfoundries Inc. Multiple patterning with mandrel cuts formed using a block mask
JP2019204815A (ja) * 2018-05-21 2019-11-28 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US10643846B2 (en) 2018-06-28 2020-05-05 Lam Research Corporation Selective growth of metal-containing hardmask thin films
US10763118B2 (en) * 2018-07-11 2020-09-01 International Business Machines Corporation Cyclic selective deposition for tight pitch patterning
US10910381B2 (en) * 2018-08-01 2021-02-02 Applied Materials, Inc. Multicolor approach to DRAM STI active cut patterning
CN110911272B (zh) * 2018-09-17 2024-05-03 长鑫存储技术有限公司 在半导体器件中形成微图案的方法
US11164772B2 (en) * 2018-10-30 2021-11-02 International Business Machines Corporation Spacer-defined process for lithography-etch double patterning for interconnects
EP3660890B1 (en) 2018-11-27 2021-08-11 IMEC vzw A method for forming an interconnection structure
CN111370309B (zh) * 2018-12-26 2023-12-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN111640655B (zh) * 2019-03-01 2023-04-25 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10943816B2 (en) 2019-04-03 2021-03-09 International Business Machines Corporation Mask removal for tight-pitched nanostructures
US11315787B2 (en) * 2019-04-17 2022-04-26 Applied Materials, Inc. Multiple spacer patterning schemes
CN111952165B (zh) * 2019-05-17 2025-03-18 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
KR102837863B1 (ko) 2019-06-04 2025-07-23 램 리써치 코포레이션 패터닝시 반응성 이온 에칭을 위한 중합 보호 라이너
KR20220042442A (ko) 2019-08-06 2022-04-05 램 리써치 코포레이션 실리콘-함유 막들의 열적 원자 층 증착 (thermal atomic layer deposition)
CN112017970B (zh) * 2020-07-24 2022-09-20 中国科学院微电子研究所 自对准金属层的制造方法、半导体器件及电子设备
TW202223133A (zh) 2020-07-28 2022-06-16 美商蘭姆研究公司 含矽膜中的雜質減量
CN114334801A (zh) * 2020-09-30 2022-04-12 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US11990409B2 (en) 2021-04-19 2024-05-21 Samsung Electronics Co., Ltd. Semiconductor device with fine metal lines for BEOL structure and method of manufacturing the same
KR20240032126A (ko) 2021-07-09 2024-03-08 램 리써치 코포레이션 실리콘-함유 막들의 플라즈마 강화 원자 층 증착
US12451354B2 (en) 2022-09-09 2025-10-21 Tokyo Electron Limited Double patterning method of patterning a substrate
CN118039463B (zh) * 2024-01-19 2024-10-29 深圳市鹏芯微集成电路制造有限公司 掩膜的制造方法和半导体器件的制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099431A1 (en) * 2005-11-01 2007-05-03 Micron Technology, Inc. Process for increasing feature density during the manufacture of a semiconductor device
JP2010080625A (ja) * 2008-09-25 2010-04-08 Toshiba Corp マスクパターンの形成方法および半導体装置の製造方法
JP2010239009A (ja) * 2009-03-31 2010-10-21 Toshiba Corp 半導体装置の製造方法およびテンプレート、並びにパターン検査データの作成方法
US20120208361A1 (en) * 2011-02-14 2012-08-16 Samsung Electronics Co., Ltd. Method for forming fine patterns of a semiconductor device
JP2013161987A (ja) * 2012-02-06 2013-08-19 Toshiba Corp パターン形成方法
US20150179513A1 (en) * 2013-12-20 2015-06-25 Alan M. Myers Diagonal hardmasks for improved overlay in fabricating back end of line (beol) interconnects

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223083A (en) * 1992-01-23 1993-06-29 Micron Technology, Inc. Process for etching a semiconductor device using an improved protective etching mask
JP2827882B2 (ja) * 1994-02-24 1998-11-25 日本電気株式会社 半導体装置の製造方法
US6632741B1 (en) 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US7190007B2 (en) * 2004-08-05 2007-03-13 International Business Machines Corporation Isolated fully depleted silicon-on-insulator regions by selective etch
US7560390B2 (en) * 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
KR100718782B1 (ko) * 2005-11-11 2007-05-16 매그나칩 반도체 유한회사 이미지 센서 제조방법
KR101348280B1 (ko) * 2007-07-06 2014-01-10 삼성전자주식회사 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법
US8852851B2 (en) * 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7611980B2 (en) * 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7666578B2 (en) * 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
KR20080034234A (ko) * 2006-10-16 2008-04-21 삼성전자주식회사 반도체 장치의 미세 패턴 형성 방법
WO2008115600A1 (en) * 2007-03-21 2008-09-25 Olambda, Inc. Multi-material hard mask or prepatterned layer for use with multi-patterning photolithography
US7923373B2 (en) * 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7994495B2 (en) * 2008-01-16 2011-08-09 Xerox Corporation Organic thin film transistors
CN102693898B (zh) * 2011-03-21 2016-02-24 华邦电子股份有限公司 缩小间距的方法
US9034197B2 (en) * 2012-09-13 2015-05-19 HGST Netherlands B.V. Method for separately processing regions on a patterned medium
US9153477B2 (en) * 2012-09-28 2015-10-06 Intel Corporation Directed self assembly of block copolymers to form vias aligned with interconnects
CN103715068A (zh) * 2012-09-29 2014-04-09 中芯国际集成电路制造(上海)有限公司 半导体精细图案的形成方法
US8871651B1 (en) * 2013-07-12 2014-10-28 Globalfoundries Inc. Mask formation processing
US9041217B1 (en) * 2013-12-18 2015-05-26 Intel Corporation Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects
KR102176758B1 (ko) * 2014-02-10 2020-11-10 에스케이하이닉스 주식회사 블록 코폴리머를 이용한 패턴 형성을 위한 구조 및 패턴 형성 방법
US9240329B2 (en) * 2014-02-23 2016-01-19 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers
CN103943468A (zh) * 2014-05-08 2014-07-23 上海华力微电子有限公司 一种图形自对准形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099431A1 (en) * 2005-11-01 2007-05-03 Micron Technology, Inc. Process for increasing feature density during the manufacture of a semiconductor device
JP2010080625A (ja) * 2008-09-25 2010-04-08 Toshiba Corp マスクパターンの形成方法および半導体装置の製造方法
JP2010239009A (ja) * 2009-03-31 2010-10-21 Toshiba Corp 半導体装置の製造方法およびテンプレート、並びにパターン検査データの作成方法
US20120208361A1 (en) * 2011-02-14 2012-08-16 Samsung Electronics Co., Ltd. Method for forming fine patterns of a semiconductor device
JP2013161987A (ja) * 2012-02-06 2013-08-19 Toshiba Corp パターン形成方法
US20150179513A1 (en) * 2013-12-20 2015-06-25 Alan M. Myers Diagonal hardmasks for improved overlay in fabricating back end of line (beol) interconnects

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CN108292591A (zh) 2018-07-17
TW201721292A (zh) 2017-06-16
TWI620995B (zh) 2018-04-11
TWI622861B (zh) 2018-05-01
KR102436100B1 (ko) 2022-08-24
KR20180045892A (ko) 2018-05-04
CN108352304A (zh) 2018-07-31
WO2017053316A1 (en) 2017-03-30
JP2018530156A (ja) 2018-10-11
CN108352304B (zh) 2022-03-08
JP6726834B2 (ja) 2020-07-22
US10020196B2 (en) 2018-07-10
KR102705674B1 (ko) 2024-09-10
US20170092506A1 (en) 2017-03-30
WO2017053296A1 (en) 2017-03-30
US9818611B2 (en) 2017-11-14
US20170092496A1 (en) 2017-03-30
KR20180049101A (ko) 2018-05-10
TW201721293A (zh) 2017-06-16

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