KR102436100B1 - 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법 - Google Patents

분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법 Download PDF

Info

Publication number
KR102436100B1
KR102436100B1 KR1020187010710A KR20187010710A KR102436100B1 KR 102436100 B1 KR102436100 B1 KR 102436100B1 KR 1020187010710 A KR1020187010710 A KR 1020187010710A KR 20187010710 A KR20187010710 A KR 20187010710A KR 102436100 B1 KR102436100 B1 KR 102436100B1
Authority
KR
South Korea
Prior art keywords
layer
forming
pattern
different materials
multiline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020187010710A
Other languages
English (en)
Korean (ko)
Other versions
KR20180049101A (ko
Inventor
안톤 제이. 데빌리어스
Original Assignee
도쿄엘렉트론가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 도쿄엘렉트론가부시키가이샤 filed Critical 도쿄엘렉트론가부시키가이샤
Publication of KR20180049101A publication Critical patent/KR20180049101A/ko
Application granted granted Critical
Publication of KR102436100B1 publication Critical patent/KR102436100B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/7055—Exposure light control in all parts of the microlithographic apparatus, e.g. pulse length control or light interruption
    • G03F7/70575—Wavelength control, e.g. control of bandwidth, multiple wavelength, selection of wavelength or matching of optical components to wavelength
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020187010710A 2015-09-24 2016-09-20 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법 Active KR102436100B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562232005P 2015-09-24 2015-09-24
US62/232,005 2015-09-24
US201562258119P 2015-11-20 2015-11-20
US62/258,119 2015-11-20
PCT/US2016/052694 WO2017053316A1 (en) 2015-09-24 2016-09-20 Methods of forming etch masks for sub-resolution substrate patterning

Publications (2)

Publication Number Publication Date
KR20180049101A KR20180049101A (ko) 2018-05-10
KR102436100B1 true KR102436100B1 (ko) 2022-08-24

Family

ID=58386992

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020187011023A Active KR102705674B1 (ko) 2015-09-24 2016-09-20 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법
KR1020187010710A Active KR102436100B1 (ko) 2015-09-24 2016-09-20 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법

Family Applications Before (1)

Application Number Title Priority Date Filing Date
KR1020187011023A Active KR102705674B1 (ko) 2015-09-24 2016-09-20 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법

Country Status (6)

Country Link
US (2) US10020196B2 (enExample)
JP (2) JP6726834B2 (enExample)
KR (2) KR102705674B1 (enExample)
CN (2) CN108292591A (enExample)
TW (2) TWI622861B (enExample)
WO (2) WO2017053296A1 (enExample)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
SG11201806451VA (en) * 2016-01-29 2018-08-30 Tokyo Electron Ltd Method and system for forming memory fin patterns
US9991156B2 (en) * 2016-06-03 2018-06-05 International Business Machines Corporation Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
US10629435B2 (en) 2016-07-29 2020-04-21 Lam Research Corporation Doped ALD films for semiconductor patterning applications
US10002762B2 (en) * 2016-09-09 2018-06-19 International Business Machines Corporation Multi-angled deposition and masking for custom spacer trim and selected spacer removal
US9911619B1 (en) * 2016-10-12 2018-03-06 Globalfoundries Inc. Fin cut with alternating two color fin hardmask
US10832908B2 (en) * 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10454029B2 (en) 2016-11-11 2019-10-22 Lam Research Corporation Method for reducing the wet etch rate of a sin film without damaging the underlying substrate
US10388644B2 (en) 2016-11-29 2019-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing conductors and semiconductor device which includes conductors
US9881794B1 (en) 2016-11-29 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor methods and devices
KR20240146695A (ko) * 2016-12-23 2024-10-08 인텔 코포레이션 진보된 리소그래피 및 자기-조립 디바이스들
US9934970B1 (en) * 2017-01-11 2018-04-03 International Business Machines Corporation Self aligned pattern formation post spacer etchback in tight pitch configurations
US10217633B2 (en) * 2017-03-13 2019-02-26 Globalfoundries Inc. Substantially defect-free polysilicon gate arrays
CN108735585B (zh) * 2017-04-17 2019-06-28 联华电子股份有限公司 掩模图案的制作方法
US10304728B2 (en) * 2017-05-01 2019-05-28 Advanced Micro Devices, Inc. Double spacer immersion lithography triple patterning flow and method
US20180323061A1 (en) * 2017-05-03 2018-11-08 Tokyo Electron Limited Self-Aligned Triple Patterning Process Utilizing Organic Spacers
CN109216163A (zh) * 2017-06-29 2019-01-15 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
US10147611B1 (en) * 2017-08-28 2018-12-04 Nanya Technology Corporation Method for preparing semiconductor structures
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
CN109545684B (zh) * 2017-09-22 2020-11-27 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10340364B2 (en) 2017-11-14 2019-07-02 International Business Machines Corporation H-shaped VFET with increased current drivability
US10566207B2 (en) * 2017-12-27 2020-02-18 Samsung Electronics Co., Ltd. Semiconductor manufacturing methods for patterning line patterns to have reduced length variation
WO2019169335A1 (en) 2018-03-02 2019-09-06 Lam Research Corporation Selective deposition using hydrolysis
US10395926B1 (en) * 2018-04-17 2019-08-27 Globalfoundries Inc. Multiple patterning with mandrel cuts formed using a block mask
JP2019204815A (ja) * 2018-05-21 2019-11-28 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US10643846B2 (en) 2018-06-28 2020-05-05 Lam Research Corporation Selective growth of metal-containing hardmask thin films
US10763118B2 (en) * 2018-07-11 2020-09-01 International Business Machines Corporation Cyclic selective deposition for tight pitch patterning
US10910381B2 (en) * 2018-08-01 2021-02-02 Applied Materials, Inc. Multicolor approach to DRAM STI active cut patterning
CN110911272B (zh) * 2018-09-17 2024-05-03 长鑫存储技术有限公司 在半导体器件中形成微图案的方法
US11164772B2 (en) 2018-10-30 2021-11-02 International Business Machines Corporation Spacer-defined process for lithography-etch double patterning for interconnects
EP3660890B1 (en) 2018-11-27 2021-08-11 IMEC vzw A method for forming an interconnection structure
CN111370309B (zh) * 2018-12-26 2023-12-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN111640655B (zh) * 2019-03-01 2023-04-25 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10943816B2 (en) 2019-04-03 2021-03-09 International Business Machines Corporation Mask removal for tight-pitched nanostructures
US11315787B2 (en) * 2019-04-17 2022-04-26 Applied Materials, Inc. Multiple spacer patterning schemes
CN111952165B (zh) * 2019-05-17 2025-03-18 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
WO2020247977A1 (en) 2019-06-04 2020-12-10 Lam Research Corporation Polymerization protective liner for reactive ion etch in patterning
US12157945B2 (en) 2019-08-06 2024-12-03 Lam Research Corporation Thermal atomic layer deposition of silicon-containing films
CN112017970B (zh) * 2020-07-24 2022-09-20 中国科学院微电子研究所 自对准金属层的制造方法、半导体器件及电子设备
KR20230043795A (ko) 2020-07-28 2023-03-31 램 리써치 코포레이션 실리콘-함유 막들의 불순물 감소
CN114334801A (zh) * 2020-09-30 2022-04-12 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US11990409B2 (en) 2021-04-19 2024-05-21 Samsung Electronics Co., Ltd. Semiconductor device with fine metal lines for BEOL structure and method of manufacturing the same
JP2024524553A (ja) 2021-07-09 2024-07-05 ラム リサーチ コーポレーション ケイ素含有膜のプラズマ強化原子層堆積
US12451354B2 (en) 2022-09-09 2025-10-21 Tokyo Electron Limited Double patterning method of patterning a substrate
CN118039463B (zh) * 2024-01-19 2024-10-29 深圳市鹏芯微集成电路制造有限公司 掩膜的制造方法和半导体器件的制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090258492A1 (en) * 2005-06-02 2009-10-15 Micron Technology, Inc. Multiple spacer steps for pitch multiplication

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223083A (en) 1992-01-23 1993-06-29 Micron Technology, Inc. Process for etching a semiconductor device using an improved protective etching mask
JP2827882B2 (ja) * 1994-02-24 1998-11-25 日本電気株式会社 半導体装置の製造方法
US6632741B1 (en) * 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US7190007B2 (en) 2004-08-05 2007-03-13 International Business Machines Corporation Isolated fully depleted silicon-on-insulator regions by selective etch
US7696101B2 (en) * 2005-11-01 2010-04-13 Micron Technology, Inc. Process for increasing feature density during the manufacture of a semiconductor device
KR100718782B1 (ko) * 2005-11-11 2007-05-16 매그나칩 반도체 유한회사 이미지 센서 제조방법
KR101348280B1 (ko) * 2007-07-06 2014-01-10 삼성전자주식회사 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법
US8852851B2 (en) * 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7611980B2 (en) * 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7666578B2 (en) * 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
KR20080034234A (ko) * 2006-10-16 2008-04-21 삼성전자주식회사 반도체 장치의 미세 패턴 형성 방법
US8907456B2 (en) * 2007-03-21 2014-12-09 Olambda, Inc. Multi-material hard mask or prepatterned layer for use with multi-patterning photolithography
US7923373B2 (en) * 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7994495B2 (en) * 2008-01-16 2011-08-09 Xerox Corporation Organic thin film transistors
JP2010080625A (ja) * 2008-09-25 2010-04-08 Toshiba Corp マスクパターンの形成方法および半導体装置の製造方法
JP4825891B2 (ja) * 2009-03-31 2011-11-30 株式会社東芝 半導体装置の製造方法およびテンプレート
KR101732936B1 (ko) * 2011-02-14 2017-05-08 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
CN102693898B (zh) * 2011-03-21 2016-02-24 华邦电子股份有限公司 缩小间距的方法
JP2013161987A (ja) * 2012-02-06 2013-08-19 Toshiba Corp パターン形成方法
US9034197B2 (en) * 2012-09-13 2015-05-19 HGST Netherlands B.V. Method for separately processing regions on a patterned medium
US9153477B2 (en) * 2012-09-28 2015-10-06 Intel Corporation Directed self assembly of block copolymers to form vias aligned with interconnects
CN103715068A (zh) * 2012-09-29 2014-04-09 中芯国际集成电路制造(上海)有限公司 半导体精细图案的形成方法
US8871651B1 (en) * 2013-07-12 2014-10-28 Globalfoundries Inc. Mask formation processing
US9041217B1 (en) * 2013-12-18 2015-05-26 Intel Corporation Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects
US9209077B2 (en) * 2013-12-20 2015-12-08 Intel Corporation Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects
KR102176758B1 (ko) * 2014-02-10 2020-11-10 에스케이하이닉스 주식회사 블록 코폴리머를 이용한 패턴 형성을 위한 구조 및 패턴 형성 방법
US9240329B2 (en) * 2014-02-23 2016-01-19 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers
CN103943468A (zh) * 2014-05-08 2014-07-23 上海华力微电子有限公司 一种图形自对准形成方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090258492A1 (en) * 2005-06-02 2009-10-15 Micron Technology, Inc. Multiple spacer steps for pitch multiplication

Also Published As

Publication number Publication date
JP6726834B2 (ja) 2020-07-22
KR20180045892A (ko) 2018-05-04
CN108292591A (zh) 2018-07-17
JP2018530156A (ja) 2018-10-11
JP2018531506A (ja) 2018-10-25
CN108352304B (zh) 2022-03-08
WO2017053296A1 (en) 2017-03-30
KR20180049101A (ko) 2018-05-10
KR102705674B1 (ko) 2024-09-10
US9818611B2 (en) 2017-11-14
US20170092496A1 (en) 2017-03-30
CN108352304A (zh) 2018-07-31
US10020196B2 (en) 2018-07-10
TW201721293A (zh) 2017-06-16
TW201721292A (zh) 2017-06-16
TWI620995B (zh) 2018-04-11
WO2017053316A1 (en) 2017-03-30
TWI622861B (zh) 2018-05-01
US20170092506A1 (en) 2017-03-30

Similar Documents

Publication Publication Date Title
KR102436100B1 (ko) 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법
KR102603019B1 (ko) 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법
US11107682B2 (en) Method for patterning a substrate using a layer with multiple materials
JP2018531506A6 (ja) サブ解像度基板パターニングのためのエッチングマスクを形成する方法
US10366890B2 (en) Method for patterning a substrate using a layer with multiple materials
TWI633583B (zh) 形成記憶體fin圖案的方法與系統
JP6805414B2 (ja) サブ解像度基板パターニング方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 4