JP2019517154A5 - - Google Patents

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Publication number
JP2019517154A5
JP2019517154A5 JP2018561727A JP2018561727A JP2019517154A5 JP 2019517154 A5 JP2019517154 A5 JP 2019517154A5 JP 2018561727 A JP2018561727 A JP 2018561727A JP 2018561727 A JP2018561727 A JP 2018561727A JP 2019517154 A5 JP2019517154 A5 JP 2019517154A5
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JP
Japan
Prior art keywords
forming
mandrel
layer
substrate
etching
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JP2018561727A
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English (en)
Japanese (ja)
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JP2019517154A (ja
JP7008907B2 (ja
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Priority claimed from PCT/US2017/033051 external-priority patent/WO2017205136A1/en
Publication of JP2019517154A publication Critical patent/JP2019517154A/ja
Publication of JP2019517154A5 publication Critical patent/JP2019517154A5/ja
Application granted granted Critical
Publication of JP7008907B2 publication Critical patent/JP7008907B2/ja
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JP2018561727A 2016-05-23 2017-05-17 複数の材料を有する層を用いて基板をパターニングする方法 Active JP7008907B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662340279P 2016-05-23 2016-05-23
US62/340,279 2016-05-23
PCT/US2017/033051 WO2017205136A1 (en) 2016-05-23 2017-05-17 Method for patterning a substrate using a layer with multiple materials

Publications (3)

Publication Number Publication Date
JP2019517154A JP2019517154A (ja) 2019-06-20
JP2019517154A5 true JP2019517154A5 (enExample) 2020-06-25
JP7008907B2 JP7008907B2 (ja) 2022-01-25

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ID=60330321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018561727A Active JP7008907B2 (ja) 2016-05-23 2017-05-17 複数の材料を有する層を用いて基板をパターニングする方法

Country Status (7)

Country Link
US (1) US10366890B2 (enExample)
JP (1) JP7008907B2 (enExample)
KR (1) KR102296805B1 (enExample)
CN (1) CN109155238B (enExample)
SG (1) SG11201810373YA (enExample)
TW (1) TWI657484B (enExample)
WO (1) WO2017205136A1 (enExample)

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US11901190B2 (en) * 2017-11-30 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning
US11127594B2 (en) * 2017-12-19 2021-09-21 Tokyo Electron Limited Manufacturing methods for mandrel pull from spacers for multi-color patterning
US10366917B2 (en) 2018-01-04 2019-07-30 Globalfoundries Inc. Methods of patterning variable width metallization lines
KR102617139B1 (ko) * 2018-04-09 2023-12-26 삼성전자주식회사 반도체 소자 및 그 제조방법
US10573520B2 (en) 2018-06-12 2020-02-25 International Business Machines Corporation Multiple patterning scheme integration with planarized cut patterning
US11061315B2 (en) * 2018-11-15 2021-07-13 Globalfoundries U.S. Inc. Hybrid optical and EUV lithography
US10529570B1 (en) * 2018-11-20 2020-01-07 Nanya Technology Corporation Method for preparing a semiconductor structure
US11069564B2 (en) * 2019-04-09 2021-07-20 International Business Machines Corporation Double metal patterning
CN110289221B (zh) * 2019-06-25 2021-06-29 武汉新芯集成电路制造有限公司 一种半导体器件及其制造方法
US11335566B2 (en) * 2019-07-19 2022-05-17 Tokyo Electron Limited Method for planarization of spin-on and CVD-deposited organic films
EP3840034B1 (en) 2019-12-19 2022-06-15 Imec VZW Method for producing nanoscaled electrically conductive lines for semiconductor devices
CN111162447B (zh) * 2019-12-31 2021-06-15 苏州辰睿光电有限公司 一种电极窗口、具有电极窗口的半导体器件的制作方法
TWI831344B (zh) * 2021-08-25 2024-02-01 美商杰米納帝歐股份有限公司 窄線切割遮蔽方法
US12211696B2 (en) 2022-08-29 2025-01-28 Nanya Technology Corporation Method of manufacturing semiconductor structure with improved etching process
US12451354B2 (en) 2022-09-09 2025-10-21 Tokyo Electron Limited Double patterning method of patterning a substrate

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KR100691492B1 (ko) * 2005-09-29 2007-03-09 주식회사 하이닉스반도체 플래시 메모리 소자의 금속배선 형성방법
KR100744683B1 (ko) * 2006-02-27 2007-08-01 주식회사 하이닉스반도체 반도체 소자 제조 방법
KR100771891B1 (ko) * 2006-11-10 2007-11-01 삼성전자주식회사 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법
KR100825796B1 (ko) * 2006-12-14 2008-04-28 삼성전자주식회사 매몰 게이트를 구비한 반도체 소자의 제조 방법
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US20090130854A1 (en) * 2007-11-21 2009-05-21 Macronix International Co., Ltd. Patterning structure and method for semiconductor devices
US20110104901A1 (en) * 2008-06-13 2011-05-05 Tokyo Electron Limited Semiconductor device manufacturing method
US7915105B2 (en) * 2008-11-06 2011-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for patterning a metal gate
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
KR100995142B1 (ko) * 2008-12-22 2010-11-18 주식회사 하이닉스반도체 반도체소자의 컨택홀 형성방법
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US8828876B2 (en) 2013-01-09 2014-09-09 International Business Machines Corporation Dual mandrel sidewall image transfer processes
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WO2015126829A1 (en) * 2014-02-23 2015-08-27 Tokyo Electron Limited Method for patterning a substrate for planarization
US9508713B2 (en) 2014-03-05 2016-11-29 International Business Machines Corporation Densely spaced fins for semiconductor fin field effect transistors
US9123656B1 (en) 2014-05-13 2015-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Organosilicate polymer mandrel for self-aligned double patterning process
FR3025937B1 (fr) * 2014-09-16 2017-11-24 Commissariat Energie Atomique Procede de grapho-epitaxie pour realiser des motifs a la surface d'un substrat
US9780193B2 (en) * 2015-10-27 2017-10-03 United Microelectronics Corporation Device with reinforced metal gate spacer and method of fabricating

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