JP2012175109A5 - - Google Patents
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- Publication number
- JP2012175109A5 JP2012175109A5 JP2012033324A JP2012033324A JP2012175109A5 JP 2012175109 A5 JP2012175109 A5 JP 2012175109A5 JP 2012033324 A JP2012033324 A JP 2012033324A JP 2012033324 A JP2012033324 A JP 2012033324A JP 2012175109 A5 JP2012175109 A5 JP 2012175109A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric layer
- undercut
- forming
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 claims 26
- 238000000034 method Methods 0.000 claims 12
- 239000011231 conductive filler Substances 0.000 claims 9
- 239000004020 conductor Substances 0.000 claims 4
- 238000000926 separation method Methods 0.000 claims 3
- 238000002955 isolation Methods 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 1
- 238000002161 passivation Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/029,205 US8314026B2 (en) | 2011-02-17 | 2011-02-17 | Anchored conductive via and method for forming |
| US13/029,205 | 2011-02-17 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012175109A JP2012175109A (ja) | 2012-09-10 |
| JP2012175109A5 true JP2012175109A5 (enExample) | 2015-04-02 |
| JP5967801B2 JP5967801B2 (ja) | 2016-08-10 |
Family
ID=46652077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012033324A Expired - Fee Related JP5967801B2 (ja) | 2011-02-17 | 2012-02-17 | 固定された導電性ビアおよびその製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8314026B2 (enExample) |
| JP (1) | JP5967801B2 (enExample) |
| CN (1) | CN102646664B (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10217644B2 (en) * | 2012-07-24 | 2019-02-26 | Infineon Technologies Ag | Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures |
| US9832887B2 (en) * | 2013-08-07 | 2017-11-28 | Invensas Corporation | Micro mechanical anchor for 3D architecture |
| CN105990314B (zh) * | 2015-03-16 | 2018-10-26 | 台湾积体电路制造股份有限公司 | 半导体器件结构及其形成方法 |
| US9892957B2 (en) * | 2015-03-16 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5169680A (en) * | 1987-05-07 | 1992-12-08 | Intel Corporation | Electroless deposition for IC fabrication |
| JPS6480024A (en) * | 1987-09-22 | 1989-03-24 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH0226020A (ja) * | 1988-07-15 | 1990-01-29 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
| JPH02110934A (ja) * | 1988-10-19 | 1990-04-24 | Matsushita Electric Works Ltd | コンタクト電極用窓の形成方法 |
| JPH05308056A (ja) * | 1992-04-30 | 1993-11-19 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
| US5470790A (en) | 1994-10-17 | 1995-11-28 | Intel Corporation | Via hole profile and method of fabrication |
| KR19990000816A (ko) * | 1997-06-10 | 1999-01-15 | 윤종용 | 앵커드 텅스텐 플러그를 구비한 반도체장치의 금속배선구조 및 그 제조방법 |
| JP2001127151A (ja) * | 1999-10-26 | 2001-05-11 | Fujitsu Ltd | 半導体装置およびその製造方法 |
| KR100366635B1 (ko) * | 2000-11-01 | 2003-01-09 | 삼성전자 주식회사 | 반도체 소자의 금속 배선 및 그 제조방법 |
| JP2002319550A (ja) * | 2001-04-23 | 2002-10-31 | Sony Corp | 金属膜の形成方法および半導体装置の製造方法 |
| JP2002373937A (ja) * | 2001-06-15 | 2002-12-26 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| US6531384B1 (en) | 2001-09-14 | 2003-03-11 | Motorola, Inc. | Method of forming a bond pad and structure thereof |
| KR100413828B1 (ko) * | 2001-12-13 | 2004-01-03 | 삼성전자주식회사 | 반도체 장치 및 그 형성방법 |
| JP3973467B2 (ja) * | 2002-03-20 | 2007-09-12 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2004134498A (ja) * | 2002-10-09 | 2004-04-30 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
| US6864578B2 (en) | 2003-04-03 | 2005-03-08 | International Business Machines Corporation | Internally reinforced bond pads |
| US7190078B2 (en) | 2004-12-27 | 2007-03-13 | Khandekar Viren V | Interlocking via for package via integrity |
| JP5208936B2 (ja) * | 2006-08-01 | 2013-06-12 | フリースケール セミコンダクター インコーポレイテッド | チップ製造および設計における改良のための方法および装置 |
| TW200939509A (en) * | 2007-11-19 | 2009-09-16 | Applied Materials Inc | Crystalline solar cell metallization methods |
-
2011
- 2011-02-17 US US13/029,205 patent/US8314026B2/en active Active
-
2012
- 2012-02-17 JP JP2012033324A patent/JP5967801B2/ja not_active Expired - Fee Related
- 2012-02-17 CN CN201210037938.1A patent/CN102646664B/zh not_active Expired - Fee Related