JP5967801B2 - 固定された導電性ビアおよびその製造方法 - Google Patents

固定された導電性ビアおよびその製造方法 Download PDF

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Publication number
JP5967801B2
JP5967801B2 JP2012033324A JP2012033324A JP5967801B2 JP 5967801 B2 JP5967801 B2 JP 5967801B2 JP 2012033324 A JP2012033324 A JP 2012033324A JP 2012033324 A JP2012033324 A JP 2012033324A JP 5967801 B2 JP5967801 B2 JP 5967801B2
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Japan
Prior art keywords
layer
undercut
dielectric layer
forming
conductive
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Expired - Fee Related
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JP2012033324A
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English (en)
Japanese (ja)
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JP2012175109A5 (enExample
JP2012175109A (ja
Inventor
エス．ユーリン トレント
エス．ユーリン トレント
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2012033324A 2011-02-17 2012-02-17 固定された導電性ビアおよびその製造方法 Expired - Fee Related JP5967801B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/029,205 US8314026B2 (en) 2011-02-17 2011-02-17 Anchored conductive via and method for forming
US13/029,205 2011-02-17

Publications (3)

Publication Number Publication Date
JP2012175109A JP2012175109A (ja) 2012-09-10
JP2012175109A5 JP2012175109A5 (enExample) 2015-04-02
JP5967801B2 true JP5967801B2 (ja) 2016-08-10

Family

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Family Applications (1)

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JP2012033324A Expired - Fee Related JP5967801B2 (ja) 2011-02-17 2012-02-17 固定された導電性ビアおよびその製造方法

Country Status (3)

Country Link
US (1) US8314026B2 (enExample)
JP (1) JP5967801B2 (enExample)
CN (1) CN102646664B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10217644B2 (en) * 2012-07-24 2019-02-26 Infineon Technologies Ag Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures
US9832887B2 (en) * 2013-08-07 2017-11-28 Invensas Corporation Micro mechanical anchor for 3D architecture
US9892957B2 (en) * 2015-03-16 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
CN105990314B (zh) * 2015-03-16 2018-10-26 台湾积体电路制造股份有限公司 半导体器件结构及其形成方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5169680A (en) * 1987-05-07 1992-12-08 Intel Corporation Electroless deposition for IC fabrication
JPS6480024A (en) * 1987-09-22 1989-03-24 Toshiba Corp Semiconductor device and manufacture thereof
JPH0226020A (ja) * 1988-07-15 1990-01-29 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
JPH02110934A (ja) * 1988-10-19 1990-04-24 Matsushita Electric Works Ltd コンタクト電極用窓の形成方法
JPH05308056A (ja) * 1992-04-30 1993-11-19 Sanyo Electric Co Ltd 半導体装置の製造方法
US5470790A (en) 1994-10-17 1995-11-28 Intel Corporation Via hole profile and method of fabrication
KR19990000816A (ko) * 1997-06-10 1999-01-15 윤종용 앵커드 텅스텐 플러그를 구비한 반도체장치의 금속배선구조 및 그 제조방법
JP2001127151A (ja) * 1999-10-26 2001-05-11 Fujitsu Ltd 半導体装置およびその製造方法
KR100366635B1 (ko) * 2000-11-01 2003-01-09 삼성전자 주식회사 반도체 소자의 금속 배선 및 그 제조방법
JP2002319550A (ja) * 2001-04-23 2002-10-31 Sony Corp 金属膜の形成方法および半導体装置の製造方法
JP2002373937A (ja) * 2001-06-15 2002-12-26 Fujitsu Ltd 半導体装置及びその製造方法
US6531384B1 (en) 2001-09-14 2003-03-11 Motorola, Inc. Method of forming a bond pad and structure thereof
KR100413828B1 (ko) * 2001-12-13 2004-01-03 삼성전자주식회사 반도체 장치 및 그 형성방법
JP3973467B2 (ja) * 2002-03-20 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2004134498A (ja) * 2002-10-09 2004-04-30 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US6864578B2 (en) 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads
US7190078B2 (en) 2004-12-27 2007-03-13 Khandekar Viren V Interlocking via for package via integrity
JP5208936B2 (ja) * 2006-08-01 2013-06-12 フリースケール セミコンダクター インコーポレイテッド チップ製造および設計における改良のための方法および装置
US20090139568A1 (en) * 2007-11-19 2009-06-04 Applied Materials, Inc. Crystalline Solar Cell Metallization Methods

Also Published As

Publication number Publication date
US20120211883A1 (en) 2012-08-23
CN102646664A (zh) 2012-08-22
US8314026B2 (en) 2012-11-20
JP2012175109A (ja) 2012-09-10
CN102646664B (zh) 2017-06-20

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