JP2019514066A5 - - Google Patents

Download PDF

Info

Publication number
JP2019514066A5
JP2019514066A5 JP2018553884A JP2018553884A JP2019514066A5 JP 2019514066 A5 JP2019514066 A5 JP 2019514066A5 JP 2018553884 A JP2018553884 A JP 2018553884A JP 2018553884 A JP2018553884 A JP 2018553884A JP 2019514066 A5 JP2019514066 A5 JP 2019514066A5
Authority
JP
Japan
Prior art keywords
layer
mandrel
sidewall spacers
forming
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018553884A
Other languages
English (en)
Japanese (ja)
Other versions
JP7009681B2 (ja
JP2019514066A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2017/027693 external-priority patent/WO2017181057A1/en
Publication of JP2019514066A publication Critical patent/JP2019514066A/ja
Publication of JP2019514066A5 publication Critical patent/JP2019514066A5/ja
Application granted granted Critical
Publication of JP7009681B2 publication Critical patent/JP7009681B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2018553884A 2016-04-14 2017-04-14 複数の材料を有する層を用いて基板をパターン化する方法 Active JP7009681B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662322603P 2016-04-14 2016-04-14
US62/322,603 2016-04-14
PCT/US2017/027693 WO2017181057A1 (en) 2016-04-14 2017-04-14 Method for patterning a substrate using a layer with multiple materials

Publications (3)

Publication Number Publication Date
JP2019514066A JP2019514066A (ja) 2019-05-30
JP2019514066A5 true JP2019514066A5 (enExample) 2020-05-28
JP7009681B2 JP7009681B2 (ja) 2022-01-26

Family

ID=60039021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018553884A Active JP7009681B2 (ja) 2016-04-14 2017-04-14 複数の材料を有する層を用いて基板をパターン化する方法

Country Status (6)

Country Link
US (2) US10460938B2 (enExample)
JP (1) JP7009681B2 (enExample)
KR (1) KR102346568B1 (enExample)
CN (1) CN109075123B (enExample)
TW (1) TWI661466B (enExample)
WO (1) WO2017181057A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9824893B1 (en) 2016-06-28 2017-11-21 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US12051589B2 (en) 2016-06-28 2024-07-30 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US20180138078A1 (en) * 2016-11-16 2018-05-17 Tokyo Electron Limited Method for Regulating Hardmask Over-Etch for Multi-Patterning Processes
KR102722138B1 (ko) 2017-02-13 2024-10-24 램 리써치 코포레이션 에어 갭들을 생성하는 방법
US10546748B2 (en) 2017-02-17 2020-01-28 Lam Research Corporation Tin oxide films in semiconductor device manufacturing
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10366917B2 (en) * 2018-01-04 2019-07-30 Globalfoundries Inc. Methods of patterning variable width metallization lines
JP7334166B2 (ja) 2018-01-30 2023-08-28 ラム リサーチ コーポレーション パターニングにおける酸化スズマンドレル
US11987876B2 (en) 2018-03-19 2024-05-21 Lam Research Corporation Chamfer-less via integration scheme
US10573520B2 (en) 2018-06-12 2020-02-25 International Business Machines Corporation Multiple patterning scheme integration with planarized cut patterning
US10950442B2 (en) * 2018-07-06 2021-03-16 Tokyo Electron Limited Methods to reshape spacers for multi-patterning processes using thermal decomposition materials
EP3660890B1 (en) * 2018-11-27 2021-08-11 IMEC vzw A method for forming an interconnection structure
CN111415860A (zh) * 2019-01-07 2020-07-14 东京毅力科创株式会社 用于对基底进行多重图案化的方法
US11145509B2 (en) 2019-05-24 2021-10-12 Applied Materials, Inc. Method for forming and patterning a layer and/or substrate
CN115565867A (zh) 2019-06-27 2023-01-03 朗姆研究公司 交替蚀刻与钝化工艺
CN113363203B (zh) * 2020-03-05 2024-07-16 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US11854806B2 (en) * 2020-05-22 2023-12-26 Tokyo Electron Limited Method for pattern reduction using a staircase spacer
CN115735263A (zh) * 2020-07-23 2023-03-03 朗姆研究公司 使用锡氧化物的先进自对准多重图案化
US20240419074A1 (en) * 2023-06-14 2024-12-19 Tokyo Electron Limited Formation of sub-lithographic mandrel patterns using reversible overcoat

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
KR100640639B1 (ko) * 2005-04-19 2006-10-31 삼성전자주식회사 미세콘택을 포함하는 반도체소자 및 그 제조방법
KR100674970B1 (ko) * 2005-04-21 2007-01-26 삼성전자주식회사 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
WO2010096363A2 (en) * 2009-02-19 2010-08-26 Arkema Inc. Nanofabrication method
US8486611B2 (en) 2010-07-14 2013-07-16 Micron Technology, Inc. Semiconductor constructions and methods of forming patterns
US8575032B2 (en) * 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8629040B2 (en) * 2011-11-16 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for epitaxially growing active regions between STI regions
US8883621B2 (en) * 2012-12-27 2014-11-11 United Microelectronics Corp. Semiconductor structure and method of fabricating MOS device
TWI545618B (zh) * 2014-02-23 2016-08-11 東京威力科創股份有限公司 用於平坦化之基板圖案化方法
WO2015126829A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for patterning a substrate for planarization
US9240329B2 (en) * 2014-02-23 2016-01-19 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers
US9601378B2 (en) * 2015-06-15 2017-03-21 International Business Machines Corporation Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same
US10249501B2 (en) * 2016-03-28 2019-04-02 International Business Machines Corporation Single process for liner and metal fill
US10079180B1 (en) * 2017-03-14 2018-09-18 United Microelectronics Corp. Method of forming a semiconductor device

Similar Documents

Publication Publication Date Title
JP2019514066A5 (enExample)
US12488986B2 (en) Selective gas etching for self-aligned pattern transfer
US10014175B2 (en) Lithography using high selectivity spacers for pitch reduction
TWI661466B (zh) 使用具有多種材料之一層的基板圖案化方法
KR102296805B1 (ko) 다중 재료를 갖는 층을 사용하여 기판을 패터닝하는 방법
US9123776B2 (en) Self-aligned double spacer patterning process
JP2018530156A5 (enExample)
KR101576335B1 (ko) 집적 회로 패터닝 방법
CN112542377B (zh) 迭代自对准图案化
US10079145B2 (en) Method for pattern formation on a substrate, associated semiconductor devices, and uses of the method
KR20180072828A (ko) 분해능이하 기판 패터닝을 위한 에칭 마스크를 형성하는 방법
US20150093902A1 (en) Self-Aligned Patterning Process
KR102328551B1 (ko) 복수의 재료의 층을 이용하여 기판을 패터닝하는 방법
KR102105726B1 (ko) 디바이스 제조 방법
JP2019510366A5 (enExample)
KR20130005185A (ko) 미세 홀 배열 및 미세 전극 배열 형성 방법
US8828876B2 (en) Dual mandrel sidewall image transfer processes
CN108511338B (zh) 一种在介电层中限定用于导电路径的图案的方法
CN104167348B (zh) 形成间隔物图案掩模的方法
KR102462051B1 (ko) 진보된 콘택 홀 패터닝 방법
US9741567B2 (en) Method of forming multiple patterning spacer structures
CN107833889A (zh) 3d nand闪存的台阶接触孔的构建方法
US9348230B2 (en) Method of manufacturing semiconductor device
US8709946B2 (en) Method for forming contact hole
CN120358767B (zh) 半导体结构的加工方法和半导体工艺设备