JP7009681B2 - 複数の材料を有する層を用いて基板をパターン化する方法 - Google Patents

複数の材料を有する層を用いて基板をパターン化する方法 Download PDF

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JP7009681B2
JP7009681B2 JP2018553884A JP2018553884A JP7009681B2 JP 7009681 B2 JP7009681 B2 JP 7009681B2 JP 2018553884 A JP2018553884 A JP 2018553884A JP 2018553884 A JP2018553884 A JP 2018553884A JP 7009681 B2 JP7009681 B2 JP 7009681B2
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layer
mandrel
etching
side wall
substrate
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JP2019514066A5 (enExample
JP2019514066A (ja
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ジェイ． デヴィリアーズ，アントン
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2018553884A 2016-04-14 2017-04-14 複数の材料を有する層を用いて基板をパターン化する方法 Active JP7009681B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662322603P 2016-04-14 2016-04-14
US62/322,603 2016-04-14
PCT/US2017/027693 WO2017181057A1 (en) 2016-04-14 2017-04-14 Method for patterning a substrate using a layer with multiple materials

Publications (3)

Publication Number Publication Date
JP2019514066A JP2019514066A (ja) 2019-05-30
JP2019514066A5 JP2019514066A5 (enExample) 2020-05-28
JP7009681B2 true JP7009681B2 (ja) 2022-01-26

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JP2018553884A Active JP7009681B2 (ja) 2016-04-14 2017-04-14 複数の材料を有する層を用いて基板をパターン化する方法

Country Status (6)

Country Link
US (2) US10460938B2 (enExample)
JP (1) JP7009681B2 (enExample)
KR (1) KR102346568B1 (enExample)
CN (1) CN109075123B (enExample)
TW (1) TWI661466B (enExample)
WO (1) WO2017181057A1 (enExample)

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US9824893B1 (en) 2016-06-28 2017-11-21 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US12051589B2 (en) 2016-06-28 2024-07-30 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US20180138078A1 (en) * 2016-11-16 2018-05-17 Tokyo Electron Limited Method for Regulating Hardmask Over-Etch for Multi-Patterning Processes
KR102722138B1 (ko) 2017-02-13 2024-10-24 램 리써치 코포레이션 에어 갭들을 생성하는 방법
US10546748B2 (en) 2017-02-17 2020-01-28 Lam Research Corporation Tin oxide films in semiconductor device manufacturing
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10366917B2 (en) * 2018-01-04 2019-07-30 Globalfoundries Inc. Methods of patterning variable width metallization lines
JP7334166B2 (ja) 2018-01-30 2023-08-28 ラム リサーチ コーポレーション パターニングにおける酸化スズマンドレル
US11987876B2 (en) 2018-03-19 2024-05-21 Lam Research Corporation Chamfer-less via integration scheme
US10573520B2 (en) 2018-06-12 2020-02-25 International Business Machines Corporation Multiple patterning scheme integration with planarized cut patterning
US10950442B2 (en) * 2018-07-06 2021-03-16 Tokyo Electron Limited Methods to reshape spacers for multi-patterning processes using thermal decomposition materials
EP3660890B1 (en) * 2018-11-27 2021-08-11 IMEC vzw A method for forming an interconnection structure
CN111415860A (zh) * 2019-01-07 2020-07-14 东京毅力科创株式会社 用于对基底进行多重图案化的方法
US11145509B2 (en) 2019-05-24 2021-10-12 Applied Materials, Inc. Method for forming and patterning a layer and/or substrate
CN115565867A (zh) 2019-06-27 2023-01-03 朗姆研究公司 交替蚀刻与钝化工艺
CN113363203B (zh) * 2020-03-05 2024-07-16 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US11854806B2 (en) * 2020-05-22 2023-12-26 Tokyo Electron Limited Method for pattern reduction using a staircase spacer
CN115735263A (zh) * 2020-07-23 2023-03-03 朗姆研究公司 使用锡氧化物的先进自对准多重图案化
US20240419074A1 (en) * 2023-06-14 2024-12-19 Tokyo Electron Limited Formation of sub-lithographic mandrel patterns using reversible overcoat

Citations (3)

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JP2008512002A (ja) 2004-09-02 2008-04-17 マイクロン テクノロジー，インコーポレイテッド ピッチ増倍を使用する集積回路の製造方法
JP2009506576A (ja) 2005-08-31 2009-02-12 マイクロン テクノロジー， インク． ピッチ増倍コンタクトを形成する方法
US20150243518A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers

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KR100674970B1 (ko) * 2005-04-21 2007-01-26 삼성전자주식회사 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
WO2010096363A2 (en) * 2009-02-19 2010-08-26 Arkema Inc. Nanofabrication method
US8486611B2 (en) 2010-07-14 2013-07-16 Micron Technology, Inc. Semiconductor constructions and methods of forming patterns
US8575032B2 (en) * 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8629040B2 (en) * 2011-11-16 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for epitaxially growing active regions between STI regions
US8883621B2 (en) * 2012-12-27 2014-11-11 United Microelectronics Corp. Semiconductor structure and method of fabricating MOS device
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WO2015126829A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for patterning a substrate for planarization
US9601378B2 (en) * 2015-06-15 2017-03-21 International Business Machines Corporation Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same
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JP2008512002A (ja) 2004-09-02 2008-04-17 マイクロン テクノロジー，インコーポレイテッド ピッチ増倍を使用する集積回路の製造方法
JP2009506576A (ja) 2005-08-31 2009-02-12 マイクロン テクノロジー， インク． ピッチ増倍コンタクトを形成する方法
US20150243518A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers

Also Published As

Publication number Publication date
TWI661466B (zh) 2019-06-01
TW201742114A (zh) 2017-12-01
CN109075123A (zh) 2018-12-21
US10460938B2 (en) 2019-10-29
CN109075123B (zh) 2023-05-09
WO2017181057A1 (en) 2017-10-19
US20170301552A1 (en) 2017-10-19
KR102346568B1 (ko) 2021-12-31
US20200066522A1 (en) 2020-02-27
JP2019514066A (ja) 2019-05-30
US11107682B2 (en) 2021-08-31
KR20180125614A (ko) 2018-11-23

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