TWI620995B - 次解析度基板圖案化所用之蝕刻遮罩的形成方法 - Google Patents
次解析度基板圖案化所用之蝕刻遮罩的形成方法 Download PDFInfo
- Publication number
- TWI620995B TWI620995B TW105130524A TW105130524A TWI620995B TW I620995 B TWI620995 B TW I620995B TW 105130524 A TW105130524 A TW 105130524A TW 105130524 A TW105130524 A TW 105130524A TW I620995 B TWI620995 B TW I620995B
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- TW
- Taiwan
- Prior art keywords
- mandrel
- substrate
- spacer
- sidewall
- sidewall spacer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 239000000758 substrate Substances 0.000 title claims description 86
- 238000000059 patterning Methods 0.000 title claims description 39
- 239000000463 material Substances 0.000 claims abstract description 291
- 238000005530 etching Methods 0.000 claims abstract description 56
- 125000006850 spacer group Chemical group 0.000 claims description 110
- 238000000151 deposition Methods 0.000 claims description 15
- 238000001459 lithography Methods 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000036961 partial effect Effects 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 238000003486 chemical etching Methods 0.000 claims 2
- 238000012546 transfer Methods 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000005855 radiation Effects 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000004035 construction material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562232005P | 2015-09-24 | 2015-09-24 | |
| US62/232,005 | 2015-09-24 | ||
| US201562258119P | 2015-11-20 | 2015-11-20 | |
| US62/258,119 | 2015-11-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201721293A TW201721293A (zh) | 2017-06-16 |
| TWI620995B true TWI620995B (zh) | 2018-04-11 |
Family
ID=58386992
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105130524A TWI620995B (zh) | 2015-09-24 | 2016-09-22 | 次解析度基板圖案化所用之蝕刻遮罩的形成方法 |
| TW105130522A TWI622861B (zh) | 2015-09-24 | 2016-09-22 | 次解析度基板圖案化所用之蝕刻遮罩的形成方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105130522A TWI622861B (zh) | 2015-09-24 | 2016-09-22 | 次解析度基板圖案化所用之蝕刻遮罩的形成方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US10020196B2 (enExample) |
| JP (2) | JP2018531506A (enExample) |
| KR (2) | KR102705674B1 (enExample) |
| CN (2) | CN108292591A (enExample) |
| TW (2) | TWI620995B (enExample) |
| WO (2) | WO2017053296A1 (enExample) |
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| US9564312B2 (en) | 2014-11-24 | 2017-02-07 | Lam Research Corporation | Selective inhibition in atomic layer deposition of silicon-containing films |
| JP6715415B2 (ja) * | 2016-01-29 | 2020-07-01 | 東京エレクトロン株式会社 | メモリフィンパターンを形成するための方法及びシステム |
| US9991156B2 (en) | 2016-06-03 | 2018-06-05 | International Business Machines Corporation | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs |
| US10629435B2 (en) | 2016-07-29 | 2020-04-21 | Lam Research Corporation | Doped ALD films for semiconductor patterning applications |
| US10002762B2 (en) * | 2016-09-09 | 2018-06-19 | International Business Machines Corporation | Multi-angled deposition and masking for custom spacer trim and selected spacer removal |
| US9911619B1 (en) * | 2016-10-12 | 2018-03-06 | Globalfoundries Inc. | Fin cut with alternating two color fin hardmask |
| US10832908B2 (en) * | 2016-11-11 | 2020-11-10 | Lam Research Corporation | Self-aligned multi-patterning process flow with ALD gapfill spacer mask |
| US10454029B2 (en) | 2016-11-11 | 2019-10-22 | Lam Research Corporation | Method for reducing the wet etch rate of a sin film without damaging the underlying substrate |
| US9881794B1 (en) * | 2016-11-29 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor methods and devices |
| US10388644B2 (en) | 2016-11-29 | 2019-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing conductors and semiconductor device which includes conductors |
| CN110337715B (zh) * | 2016-12-23 | 2023-08-25 | 英特尔公司 | 高级光刻和自组装装置 |
| US9934970B1 (en) * | 2017-01-11 | 2018-04-03 | International Business Machines Corporation | Self aligned pattern formation post spacer etchback in tight pitch configurations |
| US10217633B2 (en) * | 2017-03-13 | 2019-02-26 | Globalfoundries Inc. | Substantially defect-free polysilicon gate arrays |
| CN108735585B (zh) * | 2017-04-17 | 2019-06-28 | 联华电子股份有限公司 | 掩模图案的制作方法 |
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| US10147611B1 (en) * | 2017-08-28 | 2018-12-04 | Nanya Technology Corporation | Method for preparing semiconductor structures |
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| CN109545684B (zh) * | 2017-09-22 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| US10340364B2 (en) * | 2017-11-14 | 2019-07-02 | International Business Machines Corporation | H-shaped VFET with increased current drivability |
| US10566207B2 (en) * | 2017-12-27 | 2020-02-18 | Samsung Electronics Co., Ltd. | Semiconductor manufacturing methods for patterning line patterns to have reduced length variation |
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| US10395926B1 (en) * | 2018-04-17 | 2019-08-27 | Globalfoundries Inc. | Multiple patterning with mandrel cuts formed using a block mask |
| JP2019204815A (ja) * | 2018-05-21 | 2019-11-28 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
| US10643846B2 (en) | 2018-06-28 | 2020-05-05 | Lam Research Corporation | Selective growth of metal-containing hardmask thin films |
| US10763118B2 (en) * | 2018-07-11 | 2020-09-01 | International Business Machines Corporation | Cyclic selective deposition for tight pitch patterning |
| US10910381B2 (en) * | 2018-08-01 | 2021-02-02 | Applied Materials, Inc. | Multicolor approach to DRAM STI active cut patterning |
| CN110911272B (zh) * | 2018-09-17 | 2024-05-03 | 长鑫存储技术有限公司 | 在半导体器件中形成微图案的方法 |
| US11164772B2 (en) * | 2018-10-30 | 2021-11-02 | International Business Machines Corporation | Spacer-defined process for lithography-etch double patterning for interconnects |
| EP3660890B1 (en) | 2018-11-27 | 2021-08-11 | IMEC vzw | A method for forming an interconnection structure |
| CN111370309B (zh) * | 2018-12-26 | 2023-12-12 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| CN111640655B (zh) * | 2019-03-01 | 2023-04-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| US10943816B2 (en) | 2019-04-03 | 2021-03-09 | International Business Machines Corporation | Mask removal for tight-pitched nanostructures |
| US11315787B2 (en) * | 2019-04-17 | 2022-04-26 | Applied Materials, Inc. | Multiple spacer patterning schemes |
| CN111952165B (zh) * | 2019-05-17 | 2025-03-18 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| KR102837863B1 (ko) | 2019-06-04 | 2025-07-23 | 램 리써치 코포레이션 | 패터닝시 반응성 이온 에칭을 위한 중합 보호 라이너 |
| KR20220042442A (ko) | 2019-08-06 | 2022-04-05 | 램 리써치 코포레이션 | 실리콘-함유 막들의 열적 원자 층 증착 (thermal atomic layer deposition) |
| CN112017970B (zh) * | 2020-07-24 | 2022-09-20 | 中国科学院微电子研究所 | 自对准金属层的制造方法、半导体器件及电子设备 |
| TW202223133A (zh) | 2020-07-28 | 2022-06-16 | 美商蘭姆研究公司 | 含矽膜中的雜質減量 |
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| CN118039463B (zh) * | 2024-01-19 | 2024-10-29 | 深圳市鹏芯微集成电路制造有限公司 | 掩膜的制造方法和半导体器件的制造方法 |
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- 2016-09-20 JP JP2018515554A patent/JP2018531506A/ja active Pending
- 2016-09-20 CN CN201680067813.XA patent/CN108292591A/zh active Pending
- 2016-09-20 US US15/270,841 patent/US10020196B2/en active Active
- 2016-09-20 US US15/270,717 patent/US9818611B2/en active Active
- 2016-09-20 JP JP2018515551A patent/JP6726834B2/ja active Active
- 2016-09-20 WO PCT/US2016/052694 patent/WO2017053316A1/en not_active Ceased
- 2016-09-20 CN CN201680067753.1A patent/CN108352304B/zh active Active
- 2016-09-20 KR KR1020187010710A patent/KR102436100B1/ko active Active
- 2016-09-22 TW TW105130524A patent/TWI620995B/zh active
- 2016-09-22 TW TW105130522A patent/TWI622861B/zh active
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108292591A (zh) | 2018-07-17 |
| TW201721292A (zh) | 2017-06-16 |
| TWI622861B (zh) | 2018-05-01 |
| KR102436100B1 (ko) | 2022-08-24 |
| KR20180045892A (ko) | 2018-05-04 |
| CN108352304A (zh) | 2018-07-31 |
| WO2017053316A1 (en) | 2017-03-30 |
| JP2018530156A (ja) | 2018-10-11 |
| CN108352304B (zh) | 2022-03-08 |
| JP2018531506A (ja) | 2018-10-25 |
| JP6726834B2 (ja) | 2020-07-22 |
| US10020196B2 (en) | 2018-07-10 |
| KR102705674B1 (ko) | 2024-09-10 |
| US20170092506A1 (en) | 2017-03-30 |
| WO2017053296A1 (en) | 2017-03-30 |
| US9818611B2 (en) | 2017-11-14 |
| US20170092496A1 (en) | 2017-03-30 |
| KR20180049101A (ko) | 2018-05-10 |
| TW201721293A (zh) | 2017-06-16 |
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