JP2018508991A5 - - Google Patents
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- Publication number
- JP2018508991A5 JP2018508991A5 JP2017541025A JP2017541025A JP2018508991A5 JP 2018508991 A5 JP2018508991 A5 JP 2018508991A5 JP 2017541025 A JP2017541025 A JP 2017541025A JP 2017541025 A JP2017541025 A JP 2017541025A JP 2018508991 A5 JP2018508991 A5 JP 2018508991A5
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- bit cell
- length
- word line
- patterning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims 39
- 238000000034 method Methods 0.000 claims 13
- 238000000059 patterning Methods 0.000 claims 5
- 238000004519 manufacturing process Methods 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 4
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/620,480 | 2015-02-12 | ||
| US14/620,480 US9524972B2 (en) | 2015-02-12 | 2015-02-12 | Metal layers for a three-port bit cell |
| PCT/US2015/062644 WO2016130194A1 (en) | 2015-02-12 | 2015-11-25 | Metal layers for a three-port bit cell |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018508991A JP2018508991A (ja) | 2018-03-29 |
| JP2018508991A5 true JP2018508991A5 (enExample) | 2018-12-13 |
| JP6884103B2 JP6884103B2 (ja) | 2021-06-09 |
Family
ID=54834961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017541025A Active JP6884103B2 (ja) | 2015-02-12 | 2015-11-25 | ３ポートのビットセルのための金属層 |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US9524972B2 (enExample) |
| EP (1) | EP3257080B1 (enExample) |
| JP (1) | JP6884103B2 (enExample) |
| KR (2) | KR20220076545A (enExample) |
| CN (1) | CN107210295B (enExample) |
| BR (1) | BR112017017345B1 (enExample) |
| SG (1) | SG11201705246UA (enExample) |
| WO (1) | WO2016130194A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9524972B2 (en) * | 2015-02-12 | 2016-12-20 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
| US9793211B2 (en) | 2015-10-20 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual power structure with connection pins |
| US10740531B2 (en) | 2016-11-29 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit, system for and method of forming an integrated circuit |
| US9887127B1 (en) | 2016-12-15 | 2018-02-06 | Globalfoundries Inc. | Interconnection lines having variable widths and partially self-aligned continuity cuts |
| US10043703B2 (en) * | 2016-12-15 | 2018-08-07 | Globalfoundries Inc. | Apparatus and method for forming interconnection lines having variable pitch and variable widths |
| US10002786B1 (en) | 2016-12-15 | 2018-06-19 | Globalfoundries Inc. | Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts |
| US9978682B1 (en) * | 2017-04-13 | 2018-05-22 | Qualcomm Incorporated | Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods |
| CN112216323B (zh) * | 2017-09-04 | 2024-06-14 | 华为技术有限公司 | 一种存储单元和静态随机存储器 |
| US10410714B2 (en) * | 2017-09-20 | 2019-09-10 | Qualcomm Incorporated | Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations |
| CN111554336A (zh) * | 2019-02-12 | 2020-08-18 | 联华电子股份有限公司 | 静态随机存取存储器单元 |
| US11302388B2 (en) | 2020-08-25 | 2022-04-12 | Qualcomm Incorporated | Decoding for pseudo-triple-port SRAM |
| US11398274B2 (en) | 2020-08-25 | 2022-07-26 | Qualcomm Incorporated | Pseudo-triple-port SRAM |
| US11361817B2 (en) | 2020-08-25 | 2022-06-14 | Qualcomm Incorporated | Pseudo-triple-port SRAM bitcell architecture |
| US11910587B2 (en) * | 2021-02-26 | 2024-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure |
| US11955169B2 (en) | 2021-03-23 | 2024-04-09 | Qualcomm Incorporated | High-speed multi-port memory supporting collision |
| US20240389292A1 (en) * | 2023-05-16 | 2024-11-21 | Qualcomm Incorporated | Fly bitline design for pseudo triple port memory |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3357382B2 (ja) * | 1991-05-28 | 2002-12-16 | 株式会社日立製作所 | 多ポートメモリ |
| JP4885365B2 (ja) | 2000-05-16 | 2012-02-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP4171201B2 (ja) | 2001-10-23 | 2008-10-22 | 松下電器産業株式会社 | 半導体記憶装置 |
| KR100526884B1 (ko) * | 2003-08-25 | 2005-11-09 | 삼성전자주식회사 | 듀얼 포트 에스램의 레이아웃 구조 및 그에 따른 형성방법 |
| JP2005175415A (ja) | 2003-12-05 | 2005-06-30 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路デバイスとその製造方法 |
| SG115742A1 (en) * | 2004-04-05 | 2005-10-28 | Taiwan Semiconductor Mfg | Sram device having high aspect ratio cell boundary |
| JP2006310467A (ja) * | 2005-04-27 | 2006-11-09 | Renesas Technology Corp | 半導体記憶装置 |
| US7324382B2 (en) * | 2006-05-31 | 2008-01-29 | Grace Semiconductor Manufacturing Corporation | Current-mode sensing structure used in high-density multiple-port register in logic processing and method for the same |
| US7525868B2 (en) * | 2006-11-29 | 2009-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-port SRAM device |
| JP5078338B2 (ja) | 2006-12-12 | 2012-11-21 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US20080291767A1 (en) * | 2007-05-21 | 2008-11-27 | International Business Machines Corporation | Multiple wafer level multiple port register file cell |
| JP2009043304A (ja) * | 2007-08-06 | 2009-02-26 | Renesas Technology Corp | 半導体装置 |
| JP2009238332A (ja) * | 2008-03-27 | 2009-10-15 | Renesas Technology Corp | 半導体記憶装置 |
| JP2009260083A (ja) * | 2008-04-17 | 2009-11-05 | Renesas Technology Corp | 半導体記憶装置 |
| JP5231924B2 (ja) * | 2008-10-03 | 2013-07-10 | 株式会社東芝 | 半導体記憶装置 |
| US8675397B2 (en) * | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
| JP5503480B2 (ja) * | 2010-09-29 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP5165040B2 (ja) | 2010-10-15 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
| CN102385908A (zh) | 2011-09-06 | 2012-03-21 | 复旦大学 | 一种多端口寄存器堆存储单元及其布局布线方法 |
| US20130083591A1 (en) | 2011-09-29 | 2013-04-04 | John J. Wuu | Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets |
| US8437166B1 (en) * | 2011-11-16 | 2013-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Word line driver cell layout for SRAM and other semiconductor devices |
| US9831345B2 (en) * | 2013-03-11 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with rounded source/drain profile |
| US9026973B2 (en) * | 2013-03-14 | 2015-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for arbitrary metal spacing for self-aligned double patterning |
| JPWO2015019411A1 (ja) * | 2013-08-06 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| US9281311B2 (en) * | 2013-09-19 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same |
| US9202557B2 (en) * | 2013-09-23 | 2015-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional two-port bit cell |
| US8929130B1 (en) * | 2013-11-12 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company Limited | Two-port SRAM cell structure |
| US9208854B2 (en) * | 2013-12-06 | 2015-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional dual-port bit cell and method of assembling same |
| US9312185B2 (en) * | 2014-05-06 | 2016-04-12 | International Business Machines Corporation | Formation of metal resistor and e-fuse |
| US9412742B2 (en) * | 2014-06-10 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout design for manufacturing a memory cell |
| US9536596B2 (en) * | 2014-08-26 | 2017-01-03 | Qualcomm Incorporated | Three-port bit cell having increased width |
| US9455026B2 (en) * | 2014-11-18 | 2016-09-27 | Qualcomm Incorporated | Shared global read and write word lines |
| US9876017B2 (en) * | 2014-12-03 | 2018-01-23 | Qualcomm Incorporated | Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells |
| US9368443B1 (en) * | 2015-01-20 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory metal scheme |
| US9524972B2 (en) | 2015-02-12 | 2016-12-20 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
-
2015
- 2015-02-12 US US14/620,480 patent/US9524972B2/en active Active
- 2015-11-25 WO PCT/US2015/062644 patent/WO2016130194A1/en not_active Ceased
- 2015-11-25 CN CN201580075694.8A patent/CN107210295B/zh active Active
- 2015-11-25 BR BR112017017345-0A patent/BR112017017345B1/pt active IP Right Grant
- 2015-11-25 JP JP2017541025A patent/JP6884103B2/ja active Active
- 2015-11-25 EP EP15805719.0A patent/EP3257080B1/en active Active
- 2015-11-25 KR KR1020227018296A patent/KR20220076545A/ko not_active Ceased
- 2015-11-25 KR KR1020177021683A patent/KR102504733B1/ko active Active
- 2015-11-25 SG SG11201705246UA patent/SG11201705246UA/en unknown
-
2016
- 2016-11-09 US US15/347,530 patent/US10141317B2/en not_active Expired - Fee Related
-
2018
- 2018-10-03 US US16/150,637 patent/US20190035796A1/en not_active Abandoned
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