CN107210295B - 用于三端口位单元的金属层 - Google Patents

用于三端口位单元的金属层 Download PDF

Info

Publication number
CN107210295B
CN107210295B CN201580075694.8A CN201580075694A CN107210295B CN 107210295 B CN107210295 B CN 107210295B CN 201580075694 A CN201580075694 A CN 201580075694A CN 107210295 B CN107210295 B CN 107210295B
Authority
CN
China
Prior art keywords
metal layer
bit cell
length
word line
polysilicon gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580075694.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN107210295A (zh
Inventor
N·N·莫朱梅德
R·查巴
刘平
S·S·宋
王忠泽
C·F·耶普
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN107210295A publication Critical patent/CN107210295A/zh
Application granted granted Critical
Publication of CN107210295B publication Critical patent/CN107210295B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H10P50/00—
    • H10W20/069—
    • H10W20/42—
    • H10W20/43—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Static Random-Access Memory (AREA)
CN201580075694.8A 2015-02-12 2015-11-25 用于三端口位单元的金属层 Active CN107210295B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/620,480 US9524972B2 (en) 2015-02-12 2015-02-12 Metal layers for a three-port bit cell
US14/620,480 2015-02-12
PCT/US2015/062644 WO2016130194A1 (en) 2015-02-12 2015-11-25 Metal layers for a three-port bit cell

Publications (2)

Publication Number Publication Date
CN107210295A CN107210295A (zh) 2017-09-26
CN107210295B true CN107210295B (zh) 2020-11-20

Family

ID=54834961

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580075694.8A Active CN107210295B (zh) 2015-02-12 2015-11-25 用于三端口位单元的金属层

Country Status (8)

Country Link
US (3) US9524972B2 (enExample)
EP (1) EP3257080B1 (enExample)
JP (1) JP6884103B2 (enExample)
KR (2) KR102504733B1 (enExample)
CN (1) CN107210295B (enExample)
BR (1) BR112017017345B1 (enExample)
SG (1) SG11201705246UA (enExample)
WO (1) WO2016130194A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524972B2 (en) 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell
US9793211B2 (en) 2015-10-20 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dual power structure with connection pins
US10740531B2 (en) 2016-11-29 2020-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit, system for and method of forming an integrated circuit
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US10043703B2 (en) * 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US9978682B1 (en) * 2017-04-13 2018-05-22 Qualcomm Incorporated Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods
CN109427388B (zh) 2017-09-04 2020-09-25 华为技术有限公司 一种存储单元和静态随机存储器
US10410714B2 (en) * 2017-09-20 2019-09-10 Qualcomm Incorporated Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations
CN111554336A (zh) * 2019-02-12 2020-08-18 联华电子股份有限公司 静态随机存取存储器单元
US11302388B2 (en) 2020-08-25 2022-04-12 Qualcomm Incorporated Decoding for pseudo-triple-port SRAM
US11398274B2 (en) 2020-08-25 2022-07-26 Qualcomm Incorporated Pseudo-triple-port SRAM
US11361817B2 (en) 2020-08-25 2022-06-14 Qualcomm Incorporated Pseudo-triple-port SRAM bitcell architecture
US11910587B2 (en) * 2021-02-26 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure
US11955169B2 (en) 2021-03-23 2024-04-09 Qualcomm Incorporated High-speed multi-port memory supporting collision
US20240389292A1 (en) * 2023-05-16 2024-11-21 Qualcomm Incorporated Fly bitline design for pseudo triple port memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317537A (en) * 1991-05-28 1994-05-31 Hitachi, Ltd. Multi-port memory device having precharged bit lines
CN1681126A (zh) * 2004-04-05 2005-10-12 台湾积体电路制造股份有限公司 静态随机存取存储器元件
CN101266981A (zh) * 2006-12-12 2008-09-17 株式会社瑞萨科技 半导体存储装置

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4885365B2 (ja) 2000-05-16 2012-02-29 ルネサスエレクトロニクス株式会社 半導体装置
JP4171201B2 (ja) 2001-10-23 2008-10-22 松下電器産業株式会社 半導体記憶装置
KR100526884B1 (ko) * 2003-08-25 2005-11-09 삼성전자주식회사 듀얼 포트 에스램의 레이아웃 구조 및 그에 따른 형성방법
JP2005175415A (ja) 2003-12-05 2005-06-30 Taiwan Semiconductor Manufacturing Co Ltd 集積回路デバイスとその製造方法
JP2006310467A (ja) * 2005-04-27 2006-11-09 Renesas Technology Corp 半導体記憶装置
US7324382B2 (en) * 2006-05-31 2008-01-29 Grace Semiconductor Manufacturing Corporation Current-mode sensing structure used in high-density multiple-port register in logic processing and method for the same
US7525868B2 (en) * 2006-11-29 2009-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-port SRAM device
US20080291767A1 (en) * 2007-05-21 2008-11-27 International Business Machines Corporation Multiple wafer level multiple port register file cell
JP2009043304A (ja) * 2007-08-06 2009-02-26 Renesas Technology Corp 半導体装置
JP2009238332A (ja) * 2008-03-27 2009-10-15 Renesas Technology Corp 半導体記憶装置
JP2009260083A (ja) * 2008-04-17 2009-11-05 Renesas Technology Corp 半導体記憶装置
JP5231924B2 (ja) * 2008-10-03 2013-07-10 株式会社東芝 半導体記憶装置
US8675397B2 (en) * 2010-06-25 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure for dual-port SRAM
JP5503480B2 (ja) * 2010-09-29 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置
JP5165040B2 (ja) 2010-10-15 2013-03-21 ルネサスエレクトロニクス株式会社 半導体集積回路
CN102385908A (zh) 2011-09-06 2012-03-21 复旦大学 一种多端口寄存器堆存储单元及其布局布线方法
US20130083591A1 (en) 2011-09-29 2013-04-04 John J. Wuu Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets
US8437166B1 (en) * 2011-11-16 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Word line driver cell layout for SRAM and other semiconductor devices
US9831345B2 (en) * 2013-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with rounded source/drain profile
US9026973B2 (en) * 2013-03-14 2015-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for arbitrary metal spacing for self-aligned double patterning
JPWO2015019411A1 (ja) * 2013-08-06 2017-03-02 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9281311B2 (en) * 2013-09-19 2016-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same
US9202557B2 (en) * 2013-09-23 2015-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional two-port bit cell
US8929130B1 (en) * 2013-11-12 2015-01-06 Taiwan Semiconductor Manufacturing Company Limited Two-port SRAM cell structure
US9208854B2 (en) * 2013-12-06 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional dual-port bit cell and method of assembling same
US9312185B2 (en) * 2014-05-06 2016-04-12 International Business Machines Corporation Formation of metal resistor and e-fuse
US9412742B2 (en) * 2014-06-10 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Layout design for manufacturing a memory cell
US9536596B2 (en) * 2014-08-26 2017-01-03 Qualcomm Incorporated Three-port bit cell having increased width
US9455026B2 (en) * 2014-11-18 2016-09-27 Qualcomm Incorporated Shared global read and write word lines
US9876017B2 (en) * 2014-12-03 2018-01-23 Qualcomm Incorporated Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
US9368443B1 (en) * 2015-01-20 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Memory metal scheme
US9524972B2 (en) 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317537A (en) * 1991-05-28 1994-05-31 Hitachi, Ltd. Multi-port memory device having precharged bit lines
CN1681126A (zh) * 2004-04-05 2005-10-12 台湾积体电路制造股份有限公司 静态随机存取存储器元件
CN101266981A (zh) * 2006-12-12 2008-09-17 株式会社瑞萨科技 半导体存储装置

Also Published As

Publication number Publication date
HK1244354A1 (zh) 2018-08-03
US10141317B2 (en) 2018-11-27
BR112017017345B1 (pt) 2022-12-06
EP3257080B1 (en) 2023-08-02
US20170062439A1 (en) 2017-03-02
JP2018508991A (ja) 2018-03-29
CN107210295A (zh) 2017-09-26
WO2016130194A1 (en) 2016-08-18
KR102504733B1 (ko) 2023-02-27
SG11201705246UA (en) 2017-09-28
KR20170116021A (ko) 2017-10-18
EP3257080C0 (en) 2023-08-02
KR20220076545A (ko) 2022-06-08
EP3257080A1 (en) 2017-12-20
US9524972B2 (en) 2016-12-20
BR112017017345A2 (pt) 2018-04-10
JP6884103B2 (ja) 2021-06-09
US20160240539A1 (en) 2016-08-18
US20190035796A1 (en) 2019-01-31

Similar Documents

Publication Publication Date Title
CN107210295B (zh) 用于三端口位单元的金属层
CN106796884B (zh) 具有增大的宽度的三端口位单元
US9455026B2 (en) Shared global read and write word lines
CN107810451B (zh) 包括鳍式场效应晶体管的可调谐存储器单元的结构和方法
US9859210B2 (en) Integrated circuits having reduced dimensions between components
CN107004680B (zh) 具有捆扎式触点的FinFET SRAM
US9653399B2 (en) Middle-of-line integration methods and semiconductor devices
CN107771348A (zh) 具有共享位线的位单元
US20160233159A1 (en) Integrated circuit device including multiple via connectors and a metal structure having a ladder shape
US20170338215A1 (en) Heterogeneous cell array
HK1244354B (zh) 用於三端口位单元的金属层
US9379014B1 (en) Static random-access memory (SRAM) array

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1244354

Country of ref document: HK

GR01 Patent grant
GR01 Patent grant