SG11201705246UA - Metal layers for a three-port bit cell - Google Patents

Metal layers for a three-port bit cell

Info

Publication number
SG11201705246UA
SG11201705246UA SG11201705246UA SG11201705246UA SG11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA
Authority
SG
Singapore
Prior art keywords
metal layers
bit cell
port bit
port
cell
Prior art date
Application number
SG11201705246UA
Inventor
Niladri Narayan Mojumder
Ritu Chaba
Ping Liu
Stanley Seungchul Song
Zhongze Wang
Choh Fei Yeap
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201705246UA publication Critical patent/SG11201705246UA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
SG11201705246UA 2015-02-12 2015-11-25 Metal layers for a three-port bit cell SG11201705246UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/620,480 US9524972B2 (en) 2015-02-12 2015-02-12 Metal layers for a three-port bit cell
PCT/US2015/062644 WO2016130194A1 (en) 2015-02-12 2015-11-25 Metal layers for a three-port bit cell

Publications (1)

Publication Number Publication Date
SG11201705246UA true SG11201705246UA (en) 2017-09-28

Family

ID=54834961

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201705246UA SG11201705246UA (en) 2015-02-12 2015-11-25 Metal layers for a three-port bit cell

Country Status (9)

Country Link
US (3) US9524972B2 (en)
EP (1) EP3257080B1 (en)
JP (1) JP6884103B2 (en)
KR (2) KR102504733B1 (en)
CN (1) CN107210295B (en)
BR (1) BR112017017345B1 (en)
HK (1) HK1244354A1 (en)
SG (1) SG11201705246UA (en)
WO (1) WO2016130194A1 (en)

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US9524972B2 (en) * 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell
US9793211B2 (en) * 2015-10-20 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dual power structure with connection pins
US10740531B2 (en) 2016-11-29 2020-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit, system for and method of forming an integrated circuit
US10043703B2 (en) * 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US9978682B1 (en) * 2017-04-13 2018-05-22 Qualcomm Incorporated Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods
CN112216323A (en) 2017-09-04 2021-01-12 华为技术有限公司 Memory cell and static random access memory
US10410714B2 (en) * 2017-09-20 2019-09-10 Qualcomm Incorporated Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations
CN111554336A (en) * 2019-02-12 2020-08-18 联华电子股份有限公司 Static random access memory unit
US11302388B2 (en) 2020-08-25 2022-04-12 Qualcomm Incorporated Decoding for pseudo-triple-port SRAM
US11398274B2 (en) 2020-08-25 2022-07-26 Qualcomm Incorporated Pseudo-triple-port SRAM
US11361817B2 (en) 2020-08-25 2022-06-14 Qualcomm Incorporated Pseudo-triple-port SRAM bitcell architecture
US11910587B2 (en) * 2021-02-26 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure
US11955169B2 (en) * 2021-03-23 2024-04-09 Qualcomm Incorporated High-speed multi-port memory supporting collision

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KR100526884B1 (en) * 2003-08-25 2005-11-09 삼성전자주식회사 Layout structure of dual port sram and method therefore
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Also Published As

Publication number Publication date
KR20220076545A (en) 2022-06-08
US10141317B2 (en) 2018-11-27
JP2018508991A (en) 2018-03-29
KR102504733B1 (en) 2023-02-27
US9524972B2 (en) 2016-12-20
JP6884103B2 (en) 2021-06-09
CN107210295B (en) 2020-11-20
KR20170116021A (en) 2017-10-18
EP3257080C0 (en) 2023-08-02
CN107210295A (en) 2017-09-26
WO2016130194A1 (en) 2016-08-18
BR112017017345B1 (en) 2022-12-06
US20160240539A1 (en) 2016-08-18
HK1244354A1 (en) 2018-08-03
US20170062439A1 (en) 2017-03-02
BR112017017345A2 (en) 2018-04-10
EP3257080A1 (en) 2017-12-20
EP3257080B1 (en) 2023-08-02
US20190035796A1 (en) 2019-01-31

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