JP2009260083A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an influence of an upper layer metal wiring pitch for pile driving to a pitch of gate wiring of a selection transistor included in a memory cell. <P>SOLUTION: Word line drive circuits (2R, 2L) are arranged face to face on both sides of a memory cell array (1) and word line drivers are alternately arranged to memory cell lines in each word line drive circuit. The gate wirings (PGo, PGe) of the selection transistors of the memory cells are arranged corresponding to each memory cell line. The upper layer metal wirings (MLo, MLe) for pile driving are extended from the word line drive circuits to be arranged face to face to a connection area (10) at the center part of the memory cell array, and mutually and electrically connected to the gate wirings in the connection area. Metal wirings are arranged face to face at a pitch of twice of the gate wiring. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a configuration for arranging memory cells at high density.

  In a semiconductor integrated circuit device, constituent transistors are miniaturized from the viewpoints of higher speed, lower power supply voltage, higher integration, and the like. Further, a multilayer wiring structure is employed in order to arrange transistors with high integration and to transmit signals / voltages / currents over a wide range with low resistance. In such a multilayer wiring structure, the upper layer wiring and the lower layer wiring are electrically connected by a via in which a conductive plug such as tungsten is embedded. This via requires a relatively wider width than the lower layer wiring in order to ensure the aspect ratio. For this reason, generally, the width of the upper layer wiring is made wider than the minimum wiring width defined by the design rule.

  Further, in the multilayer wiring structure, the design rule is relaxed as it goes to the upper layer in order to suppress voltage drop and signal propagation delay in the wiring. Accordingly, the cross-sectional area of the wiring is increased in the upper wiring layer. An example of such a semiconductor memory device having a multilayer wiring structure is disclosed in Japanese Patent Application Laid-Open No. 2004-6479.

  In the configuration disclosed in Patent Document 1, the memory cell array is divided into a plurality of blocks. A main word line extending in the X direction is formed by a third metal wiring, and a sub word line selection signal line is arranged in each memory block by the second metal wiring. The sub word line is formed of a first metal wiring. A column selection line of the second metal wiring layer is arranged in the Y direction. In this patent document 1, when a specific circuit is arranged in a cross region where a sense amplifier band and a sub word line driver band intersect, signal wiring for the specific circuit in the cross region is easily arranged. Further, by arranging the sub word line selection signal line below the third metal wiring constituting the main word line, the sub word line selection signal can be easily transmitted to the sub word line driver, and the wiring The degree of freedom of layout is improved to improve the degree of freedom of layout of mesh wiring such as power supply lines.

  A ferroelectric memory (FeRAM) having a multilayer wiring structure is disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 2006-186342). In the configuration disclosed in Patent Document 2, the word line backing wiring and the plate line backing wiring are each configured by the wiring of the first wiring layer, and the bit line backing of the second wiring layer is formed on the upper layer of the first wiring layer. Arrange the wiring. The occupied area of the wiring of the first wiring layer is made larger than the occupied area of the wiring of the second wiring layer.

  The memory cell shown in Patent Document 2 is an FeRAM cell, and has a hydrogen barrier effect that is arranged close to the capacitor by increasing the wiring density of the first wiring layer with respect to the capacitor formed of the ferroelectric film. The wiring density is increased to suppress the deterioration of characteristics due to hydrogen of the capacitor.

  Non-patent document 1 (T. Tsuji et al., “A 1.2V 1Mbit Embedded MRAM core with folded Bit-Line Array Architecture”, IEEE 2004 Symposium on VLSI Circuits, Digest of Technical Papers, June 2004, pp. 450-453). In the MRAM cell structure shown in Non-Patent Document 1, a four-layer metal wiring structure is used, a column selection line is formed by a fourth metal wiring, and a main word line is formed by a third metal wiring. A bit line is formed of the second metal wiring, and a write word line is formed of the first metal wiring. The source line is formed by a diffusion wiring lined with metal silicide. The read word line is composed of a polysilicon gate wiring.

In this non-patent document 1, a folded bit line structure is realized by arranging source lines and write word lines in parallel and alternately arranging MRAM cells for each row.
JP 2004-6479 A JP 2006-186342 A T. Tsuji et al., “A 1.2V 1Mbit Embedded MRAM core with folded Bit-Line Array Architecture”, IEEE 2004 Symposium on VLSI Circuits, Digest of Technical Papers, June 2004, pp. 450-453

  In the configuration disclosed in Patent Document 1, the main word line is formed of a third metal wiring, and the sub word line selection signal line is formed of a second metal wiring. The column selection signal line is formed of a second metal wiring. By arranging a wiring layer for forming the uppermost main word line MWL, the pitch of the main word lines is relaxed, and a space for arranging other mesh-like wirings such as other power supply lines is secured. In addition, by providing an island pattern only at the location where the main word line is connected to the transistor of the sub word line driver, and connecting the sub word line and the sub word line driver and connecting the sub word line selection signal line and the sub word line driver, The number of contacts in this portion is reduced, and accordingly, the number of island patterns (intermediate wirings) of the second metal wiring for connection is reduced to secure an area for arranging other wiring.

  However, in the arrangement shown in Patent Document 1, no consideration is given to a problem when the pitch condition of the gate electrode of the memory cell transistor, that is, the sub word line becomes severe. That is, when the pitch condition in the Y direction of the memory cell becomes severe with the miniaturization of the memory cell, there is no problem with the case where the sub word line of the first metal wiring is arranged corresponding to each memory cell column. Not considered. Only a layout is shown in which a set of sub-word line drivers is arranged in parallel with each sub-word line in the X direction to relax the pitch condition of the sub-word line drivers. In addition, the word line structure of the word line piled-up structure in which the gate electrode wiring of the memory cell transistor is piled with metal wiring is also considered in consideration of the difference in pitch between the gate electrode wiring and the metal wiring for pile driving. Not.

  Japanese Patent Laid-Open No. 2006-186342 discloses a memory cell array in which a first wiring layer constituting a word line backing wiring and a plate line backing wiring is used to improve the hydrogen barrier property of a ferroelectric capacitor in FeRAM. The area occupied above is larger than the area occupied by the second wiring layer constituting the bit line backing lower layer wiring. As a result, the wiring density of the wiring layer that is wired close to the ferroelectric capacitor and has the hydrogen barrier effect is increased, and deterioration of the ferroelectric capacitor characteristics due to hydrogen is suppressed. However, even in this Patent Document 2, although it is shown that word lines are arranged at high density, when the memory cell is miniaturized and the pitch in the Y direction of the memory cell is reduced, the word line is arranged. No consideration is given to the configuration in which the backing wiring is arranged at a high density.

  In Non-Patent Document 1, although the write word line is arranged in common for one row of memory cells, the data read selection transistor of this one row of memory cells is alternately selected by different read word lines, Thereby, a folded bit line configuration is substantially realized. Even in the configuration in which the folded bit line configuration is realized by the alternate arrangement of the read selection transistors, the source line is formed by a diffusion layer lined with metal silicide to suppress an increase in the number of metal wiring layers. However, no consideration is given to the configuration that lines the read word line for selecting the read selection transistor. That is, when the pitch of the gate electrode wiring of the selection transistor of the memory cell is reduced along with the miniaturization of the memory cell, no consideration is given to the problem of how to wire the read word line with a low resistance. Absent.

  Therefore, an object of the present invention is to realize a word line piling structure without adversely affecting the pitch condition of the memory cell when the word line has a piling structure in a memory cell configuration having a selection transistor. is there.

  Another object of the present invention is to provide a semiconductor memory device in which memory cells can be arranged at a high density without adversely affecting the operation speed.

  In summary, in the semiconductor memory device according to the present invention, word line drivers are arranged on both sides of the first wiring constituting the gate of the selection transistor of the memory cell so as to be wider than the pitch of the first wiring. A second wiring is arranged corresponding to each word line driver. The second wiring extends from the corresponding word line driver to the connection region, and is electrically connected to the first wiring alternately in the connection region. The wiring length of the second wiring is shorter than that of the first wiring.

  In one embodiment, a semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a matrix, a plurality of first wirings, and a plurality of word line drivers. Each memory cell includes an access transistor formed of an insulated gate field effect transistor used for reading at least stored data. The first wiring is arranged corresponding to each memory cell row, and the selection transistor of the memory cell in the corresponding row is connected to each, and the selection transistor in the corresponding row at the time of selection is made conductive. The plurality of word line drivers are arranged at a larger pitch than the first wiring so as to face both sides of the plurality of first wirings, and drive the memory cells in the addressed row to a selected state at least during data reading. A row selection signal is generated.

  In this embodiment, the semiconductor memory device according to the present invention further includes a plurality of second wirings arranged corresponding to the plurality of word line drivers. The plurality of second wirings correspond to each of the plurality of word line drivers and are arranged corresponding to the plurality of first wirings, and each transmits a row selection signal output from the corresponding one word line driver. To do. The plurality of second wirings are alternately electrically connected to the plurality of first wirings in the connection region, and the output signal from the corresponding word line driver is transmitted to the corresponding first wiring in the connection region. . Each second wiring is arranged to extend from the corresponding one word line driver to the connection region, and its wiring length is shorter than that of the first wiring.

  According to the present invention, the word line drivers are arranged on both sides of the memory cell row, and the second wiring extends from the corresponding word line driver to the connection region and is electrically connected to the first wiring alternately. Yes. Therefore, the pitch of the second wiring can be made larger than the pitch of the first wiring, the influence of the pitch of the second wiring on the pitch of the first wiring can be reduced, and the first wiring can be arranged at a high density. Accordingly, the memory cells can be arranged at high density.

[Embodiment 1]
FIG. 1 schematically shows an entire configuration of a semiconductor memory device according to the first embodiment of the present invention. 1, the semiconductor memory device according to the first embodiment of the present invention includes a memory cell array 1 in which memory cells MC are arranged in a matrix. Memory cell MC includes a selection transistor formed of an insulated gate field effect transistor.

  Corresponding to each row of the memory cells MC, a gate wiring PG made of, for example, polysilicon having a relatively high resistance constituting the gate of the selection transistor, and a relatively low resistance arranged corresponding to the gate wiring PG. For example, a pile driving wiring (hereinafter simply referred to as a metal wiring) ML made of a metal such as aluminum or copper is included. In FIG. 1, the gate wiring PGe and the metal wiring MLe arranged corresponding to the even-numbered memory cells MC, and the gate wiring PGo and the metal wiring MLo arranged corresponding to the odd-numbered memory cells MC are representative. Shown in The gate line PGe and the metal line MLe constitute an even word line WLe, and the gate line PGo and the metal line MLo constitute an odd word line WLo.

  The metal wiring MLe constituting the even-numbered word line WLe is electrically connected to the gate wiring PGe in the stakeout region (connection region) 10 provided in the central portion of the memory cell array 1 from the right word line drive circuit 2R. On the other hand, the metal wiring MLo constituting the odd word line WLo extends from the left word line drive circuit 2L to the piled area 10 and is electrically connected to the corresponding gate wiring PGo. The metal wirings MLe and MLo are arranged substantially opposite to each other and extend to the central region of the memory cell array 1, while the gate wirings PGe and PGo are arranged over the entire memory cell row of the memory cell array 1. Is done. Therefore, the metal wirings MLe and MLo are arranged at a pitch twice that of the gate wirings PGe and PGo.

  The right word line drive circuit 2R includes word line drivers provided corresponding to the metal wirings MLe constituting the even word lines WLe, and the left word line drive circuit 2L is connected to the metal wirings MLo constituting the odd word lines WLo. A corresponding word line driver is included.

  A right word line decode circuit 4R is provided corresponding to the right word line drive circuit 2R, and a left word line decode circuit 4L is provided corresponding to the left word line drive circuit 2L. These word line decode circuits 4R and 4L decode a word line address signal (not shown) and generate a word line selection signal for driving the addressed memory cell row to a selected state. Word line drive circuits 2R and 2L transmit word line selection signals onto corresponding word lines WLe and WLo, respectively, according to word line selection signals from corresponding word line decoding circuits 4R and 4L.

  Metal wirings MLe and MLo are electrically connected to corresponding gate wirings PGe and PGo, respectively, and select transistors of corresponding memory cells MC are turned on according to a word line selection signal transmitted onto gate wirings PGe and PGo. Then, data is accessed. When the memory cell is a DRAM (dynamic random access memory) cell, a phase change memory cell, a spin injection type MRAM (magnetic random access memory) cell, or an FeRAM cell, data is written or read. Is called. When the memory cell is an MRAM cell that performs data writing by a current-induced magnetic field, data is read. The memory cell may be any of the memory cells described above. It suffices if the memory cell has a selection transistor for data access.

  In order to read data from memory cell MC, column selection circuit 6 and read circuit 8 are provided. The column selection circuit 6 can take various forms depending on the configuration of the memory cell MC. A memory cell in the selected column is selected according to a column address signal (not shown), and the memory cell MC in the selected column is coupled to the read circuit 8. Read circuit 8 reads data from the memory cell selected by column select circuit 6.

  Although the structure for performing data writing is not shown in FIG. 1, various forms are used according to the structure of memory cell MC.

  As shown in FIG. 1, gate wirings PGe and PGo are arranged corresponding to each memory cell row, while metal wirings MLe and MLo are arranged from one end of memory cell array 1 to the central portion corresponding to two memory cell rows. And is electrically connected to the corresponding gate wirings PGe and PGo in the central pile driving region 10. The metal wirings MLe and MLo have a lower resistance than the gate wirings PGe and PGo, and equivalently reduce the resistance of the gate wirings PGe and PGo. Further, the metal wirings MLe and MLo only extend to the central pile driving region 10 so as to face each other in the memory cell array 1. Therefore, the wiring pitch of the metal wirings MLo and MLe can be made larger than the pitch of the gate wirings PGe and PGo (can be increased up to twice as much). Accordingly, even when the metal wirings MLo and MLe have a pitch condition larger than that of the lowermost gate wirings PGe and PGo, the pitches of the gate wirings PGe and PGo are increased in accordance with the upper metal wirings MLo and MLe. Therefore, even if the process is miniaturized, the memory cells can be arranged with high density.

  FIG. 2 schematically shows an arrangement of word lines in memory cell array 1 shown in FIG. FIG. 2 representatively shows memory cells MC arranged in two rows. Memory cell MC includes a select transistor 12 formed of an insulated gate field effect transistor. The gate electrodes of the select transistors 12 of the memory cells MC arranged in one row are formed by the gate wiring PGe or PGo, respectively. Metal wirings MLe and MLo are wired corresponding to gate wirings PGe and PGo, respectively. These metal wirings MLo and MLe are arranged to face each other, and extend from the opposing end of the memory cell array (1) to the pile driving region 10. In the stakeout region 10, no memory cell is arranged. Instead, the metal wiring MLe is electrically connected to the gate wiring PGe via the via 14e, and the metal wiring MLo is gated via the via 14o. It is electrically connected to the wiring PGo.

  Metal interconnection MLe is driven by word line driver WDR included in right word line drive circuit 2R, and metal interconnection MLo is driven by word line driver WDL included in left word line drive circuit 2L. Word line drivers WDR and WDL transmit selection / non-selection signals on metal interconnections MLe and MLo in accordance with decode signals from corresponding word line decode circuits 4R and 4L, respectively.

  FIG. 3 schematically shows a cross-sectional structure of metal wirings MLo and MLe and gate wirings PGe and PGo shown in FIG. Since the metal wiring and the gate wiring are similarly arranged with respect to the even-numbered word line and the odd-numbered word line, respectively, in FIG. 3, the metal wiring ML and the gate wiring PG are the metal wiring MLo and MLe and the gate wiring. PGe and PGo are shown.

  One metal wiring ML is disposed per two gate wirings PG in the upper layer of the gate wiring PG. The metal wiring ML is an upper layer wiring than the gate wiring PG, and the wiring width is wider than the gate wiring PG (the film thickness may be increased).

  The metal wiring ML is arranged at a symmetrical position with respect to the corresponding two gate wirings PG in order to make the field sufficiently large and equalize the influence of the parasitic capacitance on the corresponding gate wiring PG. The metal wiring ML is arranged with a pitch Mp. On the other hand, the gate lines PG are arranged with a pitch Gp. One metal wiring ML is arranged for two gate wirings PG. The pitch Mp of the metal wiring ML is twice the pitch Gp of the gate wiring PG (Mp = 2 · Gp).

  Therefore, even when the pitch of the metal wiring ML for reducing the resistance of the gate wiring PG is widened, the gate wiring PG can be arranged at a pitch sufficiently smaller than the pitch of the metal wiring ML.

  FIG. 4 is a diagram schematically showing wiring resistances of the gate wiring PG and the metal wiring ML. The metal wiring ML extends from one side of the memory cell row to the piled area 10 disposed in the center, and is electrically connected to the gate line PG through the via 14 in the piled area 10. The via 14 is disposed at substantially the center of the entire length of the gate wiring PG. Therefore, the wiring resistance R is distributed toward both ends of the gate wiring PG. On the other hand, the metal wiring ML has a resistance r.

  The metal wiring ML is, for example, an aluminum (Al) or copper (Cu) wiring, and its resistance value r is sufficiently smaller than the resistance R of the gate wiring. The gate line PG receives a word line selection signal at a high speed via the via 14 at substantially the center, and transmits the word line selection signal toward both ends thereof. The resistance value of the gate wiring PG can be reduced to a resistance value R and about 1/2 times the resistance value 2 · R of the entire gate wiring PG. In the case of the conventional pile driving structure, the upper metal wiring ML and the gate wiring are electrically connected at both ends and the center of the gate wiring PG. In this case, the gate wiring resistance is equivalently reduced to R / 4. Therefore, compared with the conventional pile driving structure, in the configuration of the first embodiment, although the resistance value of the gate wiring is slightly increased, the equivalent resistance value of the gate wiring can be maintained at a sufficiently small value. The advantage of the pile driving structure that the signal propagation delay is reduced can be sufficiently maintained.

  The gate wiring PG may be composed of a polysilicon single layer film, or may be a wiring having a multilayer gate wiring structure formed of a plurality of films such as polysilicon and a metal silicide film.

  FIG. 5 is a cross sectional view showing a specific structure of the memory cell of the semiconductor memory device according to the first embodiment of the present invention. FIG. 5 shows a cross-sectional structure of two memory cells MCa and MCb. Memory cell MCa is provided with impurity regions 21a and 22 formed on the surface of semiconductor substrate region 20 and a substrate region between impurity regions 21a and 22 via a gate insulating film (not shown). Gate electrode 23a. The gate electrode 23a is configured by the previous gate wiring PG. Impurity region 21a is electrically connected to local wiring 25a through plug 24a. A variable magnetoresistive element 26a for storing data is connected in contact with the local wiring 25a. The variable magnetoresistive element 26a is, for example, an MTJ element (magnet tunneling junction element) and is electrically and magnetically coupled to the wiring 27 constituting the bit line. The variable magnetoresistive element 26a is, for example, a spin injection type magnetoresistive element. The impurity region 22 is also electrically connected to the wiring 30 constituting the source line via the plug 29. The local wiring 25a and the wiring 30 constituting the source line are formed in different regions. In order to show that the arrangement positions are different, in FIG. 5, the wirings 30 constituting the plug 29 and the source line SL are indicated by broken lines.

  Similar to memory cell MCa, memory cell MCb includes impurity region 21b, gate electrode 23b, plug 24b, local interconnection 25b, and variable magnetoresistive element 26b. Impurity region 22 is shared by memory cells MCa and MCb, and is electrically connected to wiring 30 constituting the source line.

  On the wiring 27 constituting the bit line BL, an upper metal wiring 28 constituting the metal wiring ML is arranged in a direction intersecting with the wiring 27 constituting the bit line. The metal wiring 28 is electrically connected to the gate electrode 23a or 23b in a region not shown.

  The memory cell shown in FIG. 5 is a spin-injection MRAM cell, and switches the direction of current flowing through the variable magnetoresistive elements 26a and 26b in accordance with write data. Each of these variable magnetoresistive elements 26a and 26b has a free layer and a fixed layer, and the magnetization direction of the free layer is set according to the direction of the injected electron spin. When the magnetization directions of the free layer and the fixed layer are the same, the resistance values of the variable magnetoresistive elements 26a and 26b are small. On the other hand, when the magnetization directions of the free layer and the fixed layer are antiparallel, the resistance values are high. Become. Data is stored according to the resistance value.

  In FIG. 5, the configuration of the spin injection MRAM cell is shown as an example. This is because, in the case of a spin-injection MRAM cell, a current flows through a variable magnetoresistive element to set its magnetization direction, and therefore a current that sets a free layer by a magnetic field induced by a current flowing through a bit line and a write word line Compared with the induced magnetic field writing type MRAM cell, the layout area of the memory cell can be reduced, and the pitch of the gate wiring can be made finer. When the degree of miniaturization of such a memory cell is increased, the influence of the upper metal wiring pitch for gate wiring pile driving on the gate wiring is increased, and therefore the present invention can be applied more effectively. .

  FIG. 6 is a diagram showing an example of the arrangement in the memory cell array 1 of the MRAM cell shown in FIG. In FIG. 6, memory cells MC arranged in 6 rows and 4 columns are shown as an example. Memory cell MC includes a variable magnetoresistive element 32 and a select transistor 34. The variable magnetoresistive element 32 corresponds to the variable magnetoresistive element 26a (26b) and the local wiring 25a (25b) shown in FIG. The selection transistor 34 corresponds to the configuration of the gate electrode 23a and the impurity regions 21a and 22 or the configuration of the gate electrode 23b and the impurity regions 21b and 22 in FIG.

  Corresponding to each row of memory cells MC, word lines WLe0, WLo0, WLe1, WLo1, WLe2 and WLo2 are alternately arranged. These word lines WLe0, WLo0-WLe2, WLo2 are connected to the gates of the select transistors of the memory cells in the corresponding row, respectively.

  Bit lines BL0, BL1, BL2 and BL3 are arranged corresponding to each column of memory cells MC, and source lines SL0 and SL1 are arranged in common for the two columns of memory cells, respectively.

  In the memory cell column sharing the source line SL (SL0, SL1), the variable magnetoresistive element 32 is electrically connected to different bit lines alternately in units of two memory cells MC. The two memory cells in this unit share a source line contact and are connected to corresponding source lines (SL0, SL1). Therefore, in the memory cell column sharing the source line, the memory cell MC is arranged corresponding to the intersection of one of the two corresponding bit lines and the corresponding word line.

  The even word lines WLe0 to WLe2 are driven to a selected state by word line drivers WDR0 to WDR2 included in the right word line drive circuit 2R, and the odd word lines WLo0 to WLo2 are word lines included in the left word line drive circuit 2L. Driven to a selected state by drivers WDL0-WDL2.

  At the time of data writing, the word line arranged corresponding to the selected row is driven to the selected state, and the selection transistor 34 is driven to the conductive state. Between the bit line BL (any one of BL0 to BL3) of the selected column and the corresponding source line SL (any one of SL0 and SL1), a current flows in a direction corresponding to the stored data, and the magnetization of the variable magnetoresistive element 32 Set the state.

  At the time of data reading, similarly, the word line of the addressed row is driven to the selected state, and the selection transistor 34 is set to the conductive state. In this state, since the amount of current flowing between the bit line BL and the source line SL via the variable magnetoresistive element 32 differs according to the stored data (resistance value of the variable resistance element), the bit line BL or the source line SL is The amount of flowing current is detected by a sense amplifier circuit (not shown) (included in the readout circuit), and data is read out.

  The arrangement of the memory cells shown in FIG. 6 is a so-called folded bit line structure. A dummy cell is connected to one of a pair of bit lines arranged corresponding to a memory cell column sharing each source line. Data in the memory cell may be detected using the flowing current as a reference current. In addition, as shown in Non-Patent Document 1, a dummy cell in a high-resistance state that uses four bit lines as a unit, selects a 2-bit memory cell, and connects to the remaining two unselected column bit lines. In addition, the average current of the currents flowing through the dummy cells in the low resistance state may be generated as the reference current, and the parallel reading of the data of the 2-bit selected memory cell may be performed.

  FIG. 7 schematically shows a planar layout corresponding to the arrangement of the memory cells shown in FIG. In FIG. 7, active regions 40 in which rectangular portions and tapered portions are combined are arranged in a matrix. In the active region 40, two memory cells are formed. In the Y direction, the active regions 40 are alternately inverted in shape, and are arranged so that the tapered portions of the active regions face each other in adjacent active region rows.

  Two gate wirings PG are arranged for the active region 40 aligned in the X direction. FIG. 7 representatively shows gate wirings PG0 to PG7. Metal wirings MLR1-MLR4 and MLL1-MLL4 are arranged corresponding to each row of active region 40 for gate wirings PG0-PG7. Metal wirings MLR1-MLR4 are arranged for every two gate wirings, and metal wirings MLL1-MLL4 are arranged for every two gate wirings.

  The metal wirings MLR1 to MLR4 extend in the X direction so as to transmit the word line selection signals from the right word line drivers WDR1 to WDR4 to the pile driving region (connection region) 10, and the metal wirings MLL1 to MLL4. Are arranged extending in the X direction so as to transmit the word line selection signals from the left word line drivers WDL1 to WDL4 to the pile driving region 10. These metal interconnections MR1-MLR4 are arranged to face metal interconnections MLL1-MLL4.

  By selectively extending in the Y direction, bit lines BLLa-BLLn and BLRa-BLRn are arranged corresponding to each active region, and source lines SLLa-SLLk and SLRa-SLRk are arranged for every two bit lines. .

  Bit line lines BLLa-BLLn and BLRa-BLRn are electrically connected to active regions 40 of memory cells in the corresponding columns, respectively, and active regions 40 are variable magnetoresistive via vias (plugs) 44a and 44b. Connected to local wirings 42a and 42b in which elements are arranged. The gate wiring is arranged between vias 44a and 44b and metal wiring ML (MLL, MLR) in plan view. Source lines SLLa-SLLk and SLRa-SLRk are electrically connected to active regions 40 of memory cells in corresponding columns through vias 46, respectively. Two memory cells are formed in one active region 40, and the source lines are electrically connected in common to the active regions alternately connected to the paired bit lines.

  In the pile driving region 10, the metal wiring MLR (MLR1-MLR4) is electrically connected to the corresponding gate wirings PG0, PG2, PG4, and PG6 through the intermediate wiring 50a and the via 52a. On the other hand, metal wiring MLL (MLL1-MLL4) is electrically connected to odd-numbered gate wirings PG1, PG3, PG5 and PG7 through intermediate wiring 50b and via 52b in connection region 10.

  The distance L from the pile driving area 10 to the right word line driver WDR (WDR1-WDR4) and the distance L from the pile driving area 10 to the left word line driver WDL (WDL1-WDL4) are substantially equal to each other.

  With respect to the pitch Gp of the gate wirings PG0 to PG7 and the pitch Mp of the metal wiring ML (MLR, MLL), the relationship shown in FIG. 3 is substantially satisfied.

  Therefore, only one metal wiring is arranged for backing of two gate wirings, and the pitch of the gate wiring PG (PG0 to PG7) is sufficiently larger than the pitch Mp of the metal wiring ML (MLR, MLL). Gp can be made sufficiently small to arrange active region 40 that forms a memory cell.

  In the arrangement shown in FIG. 7, the metal wiring ML (MLR, MLL) is arranged between the gate wirings PG0 to PG7. However, the width of the metal wiring ML (MLR, MLL) in the Y direction may be widened so as to overlap the lower-layer gate wirings PG0 to PG7 in a plane.

  In the above description, a spin-injection MRAM cell having a folded bit line structure is described as the memory cell. However, as the memory cell, the present invention can be applied to other semiconductor memory elements such as a DRAM cell having a select transistor, an SRAM cell, and a change memory cell. Also, the MRAM cell may be a so-called “open bit line structure” MRAM cell instead of the folded bit line structure, and may be a current-induced magnetic field writing type MRAM cell other than the spin injection type MRAM cell. Also good.

  As described above, according to the first embodiment of the present invention, the gate wiring of the select transistor of the memory cell is piled from the both ends of the memory cell array to the substantially central portion corresponding to the set of two gate wirings. The upper-layer metal wiring is arranged up to the region, and the odd-numbered gate wiring and the even-numbered gate wiring are connected to different metal wirings in this pile driving region. Therefore, the pitch of the gate wiring may be at least 1/2 times the pitch of the upper metal wiring, and it is not necessary to increase the gate wiring pitch (or wiring interval) in accordance with the minimum pitch of the metal wiring. Memory cells can be arranged. In addition, the upper metal wiring is connected to the corresponding lower gate wiring almost to the center of the memory cell array, and the length of the gate wiring can be equivalently reduced to ½ times. , Signal propagation delay can be reduced.

[Embodiment 2]
FIG. 8 schematically shows a structure of a main portion of the semiconductor memory device according to the second embodiment of the present invention. FIG. 8 representatively shows the arrangement of one gate line PG and the corresponding metal line ML. The wiring arrangement shown in FIG. 8 is different from the wiring arrangement shown in FIG. 3 in the following points. That is, the end 60 of the gate wiring PG and the end 62 of the metal wiring ML are electrically connected in a portion close to the word line driver. The gate wiring PG is separated in the central region 66 between the end portion 60 and the via 14 of the pile driving region 10. The other configuration shown in FIG. 8 is the same as the wiring arrangement shown in FIG. 3, and the corresponding parts are denoted by the same reference numerals.

  In the wiring arrangement shown in FIG. 8, the portion between the end 60 of the gate wiring PG and the pile driving region 10 is divided into a resistance R / 2 portion. Therefore, it is possible to further reduce the wiring resistance in the portion near the word line driver of the gate wiring PG, and to further reduce the signal propagation delay in this portion.

  Also in this arrangement, the metal wiring ML is arranged at twice the pitch of the gate wiring PG, and the restriction on the minimum pitch condition of the metal wiring ML with respect to the gate wiring PG can be relaxed as in the first embodiment.

  The present invention can be generally applied to a semiconductor memory device having a memory cell having a selection transistor. The semiconductor memory device may be a single memory formed alone on a semiconductor chip, or may be a memory integrated with logic such as another processor on the semiconductor chip.

FIG. 11 schematically shows a structure of a portion related to data reading of the semiconductor memory device according to the first embodiment of the present invention. FIG. 2 is a diagram showing an example of the arrangement of word lines and memory cells in the memory cell array shown in FIG. 1. FIG. 3 is a diagram schematically showing a cross-sectional structure of a gate wiring and a metal wiring in the word line arrangement shown in FIG. 2. It is a figure which shows roughly the wiring resistance of one word line. It is a figure which shows an example of the cross-section of the memory cell of the semiconductor memory device according to Embodiment 1 of this invention. FIG. 4 schematically shows an arrangement of a memory cell array in the semiconductor memory device according to the first embodiment of the present invention. FIG. 7 schematically shows a planar layout of the memory cell arrangement shown in FIG. 6. FIG. 11 schematically shows a structure of a main portion of a semiconductor memory device according to the second embodiment of the present invention.

Explanation of symbols

  1 memory cell array, 2R right word line drive circuit, 2L left word line drive circuit, 4R right word line decode circuit, 4L left word line decode circuit, MC memory cell, PGe, PGo gate wiring, MLe, MLo metal wiring, WLe, WLo word line, 10 connection region, 14e, 14o via, 12 selection transistor, WD0-WDR4, WDL0-WDL4 word line driver, PG0-PG7 gate wiring, MLR1-MLR4, MLL1-MLL4 metal wiring, 40 active region, 60 gate Wiring end, 62 Metal wiring end.

Claims (3)

A plurality of memory cells arranged in a matrix, each of the memory cells including a selection transistor composed of at least an insulated gate field effect transistor used for reading stored data;
A plurality of first wirings arranged corresponding to each of the memory cell rows, each of which is connected to a selection transistor of a memory cell of the corresponding row, and which, when selected, makes the selection transistor of the corresponding row conductive;
A row selection signal is arranged to face both sides of the plurality of first wirings at a pitch larger than that of the first wirings, and drives a memory cell in the addressed row to a selected state at least during data reading. A plurality of word line drivers that are arranged corresponding to each of the plurality of word line drivers and corresponding to the plurality of first wirings, and each of which transmits an output signal of a corresponding one word line driver. Second wirings, and the plurality of second wirings are alternately electrically connected to the plurality of first wirings in a connection region to output an output signal from a corresponding word line driver. Each of the second wirings is arranged extending from the corresponding one word line driver to the connection region, and is shorter in length than each of the first wirings. .   The semiconductor memory device according to claim 1, wherein each of the first wirings has a resistivity higher than that of the second wiring.   The semiconductor memory device according to claim 1, wherein the connection region is a substantially central region of the first wiring.

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