JP2007213639A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of simultaneously writing data in different memory cells, and capable of preventing malfunction of data writing. <P>SOLUTION: The nonvolatile semiconductor memory comprises: a plurality of magnetic storage parts S arranged in a matrix form for storing data based on a current between a terminal T1 and a terminal T2; word lines WL arranged by n lines for one column of the respective magnetic storage parts S; bit lines BL arranged by n lines for one row; a source line arranged by corresponding to the row or column of the respective magnetic storage parts S and connected to the terminal T1 of the corresponding magnetic storage parts S; and transistors MB arranged by n pieces for every magnetic storage part S. In the n pieces of transistors MB, a control electrode is connected to the respective word lines WL corresponding to the column consisted of the corresponding magnetic storage part S, and a first conductive electrode is connected to the respective bit lines BL corresponding to the row, respectively, and a second conductive electrode is connected to the terminal T2 of the corresponding magnetic storage parts S. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device that performs data writing or data reading simultaneously on different memory cells.

  MRAM (Thin Film Magnetic Storage Device) is a general term for solid-state memories that store data using the magnetization direction of a ferromagnetic material. In the MRAM, “1” and “0” correspond to whether the magnetization direction of the ferromagnetic material constituting the memory cell is parallel or antiparallel to a certain reference direction. In addition, a GMR element using a giant magnetoresistive effect (GMR (Giant Magneto Resistive) effect) and a magnetic tunnel effect (Tunneling Magneto-Resistance effect: TMR (Tunneling Magneto) are used for reading data from a memory cell. Resistive effect) is used in the MRAM.

  The TMR element is composed of a three-layer film of ferromagnetic layer / insulating layer / ferromagnetic layer, and a tunnel current flows through the insulating layer. The resistance value to the tunnel current changes according to the relationship between the magnetization directions of the two ferromagnetic layers.

  Here, as a method of reversing the magnetization direction of the ferromagnetic layer, an external magnetic field is generated by passing a current through the bit line and digit line arranged in the vicinity of the memory cell to be written, and the magnetization direction of the ferromagnetic layer There is known an external magnetization reversal method for reversing (see, for example, Non-Patent Document 1).

  As a non-volatile magnetic memory employing this external magnetization reversal method, for example, Patent Document 1 discloses the following non-volatile magnetic memory. That is, the first and second word lines arranged in parallel to each other, the data lines intersecting the first and second word lines via the insulating layer, the first and second word lines and the data lines In the semiconductor memory device having a plurality of memory cells provided at the intersections, the data line extends between the first and second word lines, and the memory cell is formed of a magnetic conductor and an insulator. It has a laminated film.

As a method for reversing the magnetization direction of a ferromagnetic material, a spin injection magnetization reversal method is known (for example, see Non-Patent Document 2). This is a method in which a current is directly applied to a memory cell and magnetization is reversed by the action of spin (direction) of electrons. More specifically, this is a method of reversing the magnetization of the ferromagnetic layer by passing a current (hereinafter also referred to as a spin injection current) from one ferromagnetic layer of the TMR element to the other ferromagnetic layer. Since the spin injection current can have a smaller amount of current than the current for generating the external magnetic field, the spin injection magnetization reversal method can reduce the current consumption of the MRAM compared to the external magnetization reversal method.
JP 2002-208682 A “IEEE JOURNAL OF SOLID-STATE CIRCUITS”, VOL.40, NO.1, JANUARY 2005 “2005 Symposium on VLSI Technology Digest of Technical Papers”, 10B-1

  Incidentally, there is a demand for the realization of a dual port MRAM in which data is written to or read from different memory cells simultaneously. However, in the configuration employing the external magnetization reversal method in the dual port MRAM, for example, the dual port MRAM is arranged in the vicinity of the digit line corresponding to one of the two memory cells to be written, and the other memory cell There has been a problem that data writing is erroneously performed on memory cells that are not to be written and are arranged in the vicinity of the corresponding bit line.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of simultaneously writing data to different memory cells and preventing malfunction of data writing.

  In order to solve the above problems, a nonvolatile semiconductor memory device according to an aspect of the present invention is arranged in a matrix, includes a first terminal and a second terminal, and the first terminal and the second terminal A plurality of magnetic storage units for storing data based on a write current flowing between them, a first control line arranged with n (n is a natural number of 1 or more) for one column of each magnetic storage unit, N second control lines arranged for one row of each magnetic memory unit, and corresponding to the row or column of each magnetic memory unit, and connected to the first terminal of the corresponding magnetic memory unit. A third control line, a first control transistor having a control electrode, a first conduction electrode, and a second conduction electrode and arranged in n units for each magnetic storage unit. The n first control transistors arranged in the column are columns formed by corresponding magnetic storage units. A control electrode is connected to each corresponding first control line, and a first conduction electrode is connected to each second control line corresponding to a row formed by the corresponding magnetic storage unit, and the corresponding magnetic storage unit A second conductive electrode is connected to the second terminal of the second terminal.

  According to the present invention, data writing can be performed simultaneously on different memory cells, and malfunction of data writing can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
[Constitution]
FIG. 1 is a diagram schematically showing an overall configuration of a nonvolatile semiconductor memory device according to the first embodiment of the present invention. In the following description, the direction in which the word line WL extends is referred to as the column direction, and the direction in which the bit line BL extends is referred to as the row direction.

  Referring to FIG. 1, this nonvolatile semiconductor memory device includes a memory array 1 in which magnetic storage units S are arranged in a matrix, a word line driving circuit 2, a bit line driving circuit 4, and a source line driving circuit 5. A readout circuit 7, an output circuit 8, a control circuit 10, a power supply circuit 12, and a substrate bias circuit 13.

  A word line WL and a source line SL are arranged corresponding to each column of the magnetic memory unit S, and a bit line BL is arranged corresponding to each row of the magnetic memory unit S.

  The word line driving circuit 2 includes a word line driver that drives the word line WL. The bit line driving circuit 4 includes a bit line driver that drives the bit line BL. Source line drive circuit 5 includes a source line driver for driving source line SL.

  When writing data, the control circuit 10 generates an internal write control signal WRCONT based on the external write control signal WR and the external data D. In addition, the control circuit 10 generates an internal read control signal RDCONT based on a read control signal RE from the outside when reading data. The control circuit 10 generates an internal address control signal ADCONT representing the magnetic storage unit S to be written or read based on the address signal AD from the outside.

  In response to internal address control signal ADCONT and internal write control signal WRCONT or internal read control signal RDCONT, word line drive circuit 2 drives word line WL corresponding to the column indicated by internal address control signal ADCONT to a selected state. .

  Source line drive circuit 5 receives internal address control signal ADCONT and internal write control signal WRCONT or internal read control signal RDCONT, and supplies a voltage to source line SL corresponding to the column represented by internal address control signal ADCONT.

  Bit line drive circuit 4 receives internal address control signal ADCONT and internal write control signal WRCONT and selects bit line BL corresponding to the row represented by internal address control signal ADCONT when data is written. Then, the bit line driving circuit 4 drives the selected bit line BL to the selected state, and causes a spin injection current to flow.

  In addition, when reading data, bit line drive circuit 4 receives internal address control signal ADCONT and internal read control signal RDCONT, and selects bit line BL corresponding to the row indicated by internal address control signal ADCONT. The bit line drive circuit 4 supplies a read current to the selected bit line BL.

  The read circuit 7 detects the amount of read current flowing through the selected bit line BL and generates internal read data. The output circuit 8 generates external output data Q based on the internal read data output from the read circuit 7.

  The power supply circuit 12 supplies power supply voltages Vdd and Vss to each circuit. The substrate bias circuit 13 supplies bias voltages Vpw and Vnw to the substrate SUB.

  FIG. 2 is a circuit diagram showing a configuration of the memory array of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

  Referring to FIG. 1, memory array 1 includes a plurality of magnetic storage units S, a plurality of word lines (first control lines) WL, a plurality of bit lines (second control lines) BL, And a plurality of source lines (third control lines) SL and a plurality of bit line switching transistors (first control transistors) MB. In the figure, representatively magnetic storage units S1 to S15, word lines WL_EVEN0 to WL_EVEN2, word lines WL_ODD0 to WL_ODD2, bit lines BL_EVEN0 to BL_EVEN4, bit lines BL_ODD0 to BL_ODD4, source lines SL0 to SL2, and bit line switching Reference numerals are assigned to the transistors MB0_EVEN to MB15_EVEN and MB0_ODD to MB15_ODD. The bit line switching transistors MB0_EVEN to MB15_EVEN and MB0_ODD to MB15_ODD may be abbreviated as MB0_E to MB15_E and MB0_O to MB15_O in some cases.

  The magnetic storage units S1 to S15 are arranged in a matrix and include, for example, TMR elements. The magnetic storage unit S stores data based on a write current flowing between the terminal T1 (first terminal) and the terminal T2 (second terminal). For example, as described above, by applying a spin injection current from the terminal T1 connected to one ferromagnetic layer of the TMR element to the terminal T2 connected to the other ferromagnetic layer, the ferromagnetic layer of the TMR element The data is written by reversing the magnetization of.

  N (n is a natural number of 1 or more) word lines WL are arranged for one column of each magnetic storage unit S.

N bit lines BL are arranged for one row of each magnetic storage unit S.
The source line SL is arranged corresponding to the row or column of each magnetic memory unit S, and is connected to the terminal T1 of the corresponding magnetic memory unit S.

  The n bit line switching transistors MB are arranged for each magnetic memory unit S, the control electrodes, that is, the gates are respectively connected to the word lines WL corresponding to the columns formed by the corresponding magnetic memory unit S, and One conduction electrode, ie, source or drain, is connected to each bit line BL corresponding to the row that the magnetic memory unit S constitutes, and the other conduction electrode, ie, drain or source, is connected to the terminal T2 of the corresponding magnetic memory unit S. The

  The bit line switching transistor MB makes the terminal T2 of the magnetic memory unit S and the bit line BL conductive or non-conductive based on the voltage supplied to the word line WL.

  Hereinafter, the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described assuming that n = 2.

  The connection relationship of the magnetic storage unit S will be described in detail. In the magnetic memory unit S1, the terminal T1 is connected to the source line SL0, and the terminal T2 is connected to the sources of the bit line switching transistors MB1_EVEN and MB1_ODD. The drain of the bit line switching transistor MB1_EVEN is connected to the bit line BL_EVEN0, and the gate is connected to the word line WL_EVEN0. The drain of the bit line switching transistor MB1_ODD is connected to the bit line BL_ODD0, and the gate is connected to the word line WL_ODD0.

  In the magnetic memory unit S2, the terminal T1 is connected to the source line SL1, and the terminal T2 is connected to the sources of the bit line switching transistors MB2_EVEN and MB2_ODD. The drain of the bit line switching transistor MB2_EVEN is connected to the bit line BL_EVEN0, and the gate is connected to the word line WL_EVEN1. The drain of the bit line switching transistor MB2_ODD is connected to the bit line BL_ODD0, and the gate is connected to the word line WL_ODD1.

  In the magnetic memory unit S4, the terminal T1 is connected to the source line SL0, and the terminal T2 is connected to the sources of the bit line switching transistors MB4_EVEN and MB4_ODD. The drain of the bit line switching transistor MB4_EVEN is connected to the bit line BL_EVEN1, and the gate is connected to the word line WL_EVEN0. The drain of the bit line switching transistor MB4_ODD is connected to the bit line BL_ODD1, and the gate is connected to the word line WL_ODD0.

  Since the connection relationship around the magnetic storage units S3, S5 to S12 is the same as described above, detailed description will not be repeated here.

  FIG. 3 is a diagram showing a layout of the memory array of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 4 is a diagram schematically showing a cross-sectional structure of the memory array viewed from the direction A in FIG.

  Referring to FIG. 4, bit line BL_ODD4 is connected to the drain of bit line switching transistor MB13_ODD in substrate SUB. Although the bit line BL_EVEN4 is not shown in the figure because it is located on the back surface of the bit line BL_ODD4, it is connected to the drain of the bit line switching transistor MB_EVEN4 in the substrate SUB. The source line SL0 is connected to the terminal T1 of the magnetic memory unit S13. The source line SL1 is connected to the terminal T1 of the magnetic memory unit S14. The word line WL_EVEN0 is connected to the gate of the bit line switching transistor MB13_EVEN. The word line WL_ODD0 is connected to the gate of the bit line switching transistor MB13_ODD. The word line WL_EVEN1 is connected to the gate of the bit line switching transistor MB14_EVEN. The word line WL_ODD1 is connected to the gate of the bit line switching transistor MB14_ODD. The terminal T2 of the magnetic memory unit S13 is connected to the sources of the bit line switching transistors MB13_EVEN and MB13_ODD. The terminal T2 of the magnetic memory unit S14 is connected to the sources of the bit line switching transistors MB14_EVEN and MB14_ODD.

  Referring to FIG. 3, word line WL is arranged substantially in parallel with each magnetic storage unit S column. The bit line BL is arranged substantially in parallel with the row of each magnetic storage unit S. The source lines SL are arranged corresponding to the columns of the magnetic storage units S, and are arranged substantially parallel to the columns of the magnetic storage units S, that is, arranged substantially parallel to the word lines WL.

  Here, in the configuration in which the source line SL is arranged substantially parallel to the bit line BL, the source line SL is connected to the terminal T1 of the magnetic memory unit S while avoiding the connection line between the bit line BL and the substrate SUB shown in FIG. Extra space is required to do this. However, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, since the source line SL is arranged substantially perpendicular to the bit line BL, the source line SL is extended right above each magnetic memory unit S. The nonvolatile semiconductor memory device can be downsized.

  FIG. 5 shows the active region and the isolation region in FIG. FIG. 6 is a diagram showing the active region and the isolation region in FIG.

  Referring to FIG. 5, the shaded portion is the active region, and the region other than the shaded portion is the separation region. A portion surrounded by a thick line indicates a source region or a drain region in the second row of the magnetic memory portion S. Referring to FIG. 6, a portion surrounded by a thick line is an active region.

  Referring to FIG. 5, active regions ACT <b> 1 to ACT <b> 5 of bit line switching transistors MB are formed corresponding to the respective rows of magnetic storage units S <b> 1 to S <b> 15. A plurality of word lines WL cross the active regions ACT1 to ACT5.

  The source line SL0 is arranged to extend directly above the magnetic storage units S1, S4, S7, S10, and S13.

  The word line WL_EVEN0 and the word line WL_ODD0 are arranged substantially parallel to the source line SL0, and are arranged adjacent to the left and right of the source line SL0.

  The source line SL1 is arranged to extend directly above the magnetic storage units S2, S5, S8, S11, and S14.

  The word line WL_EVEN1 and the word line WL_ODD1 are arranged substantially parallel to the source line SL1, and are arranged adjacent to the left and right of the source line SL1.

  In addition, the region surrounded by the thick dotted line, that is, the active region divided by the adjacent word line WL and not having the magnetic storage unit S is connected to every other bit line BL.

  Referring to FIG. 6, bit line switching transistors MB13_ODD and MB14_ODD respectively corresponding to magnetic storage unit S13 and magnetic storage unit S14 adjacent in the row direction of magnetic storage unit S and connected to the same bit line BL_ODD4 are magnetic. Arranged adjacently between the storage unit S13 and the magnetic storage unit S14. The drain region is common between the bit line switching transistors MB13_ODD and MB14_ODD.

  That is, the active region divided by the word line WL_ODD0 and the word line WL_ODD1 is commonly used as the drain region of the bit line switching transistors MB13_ODD and MB14_ODD. The active region divided by the word line WL_EVEN1 and the word line WL_EVEN2 is commonly used as the drain region of the bit line switching transistors MB14_EVEN and MB_15EVEN.

  Therefore, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, by sharing the regions of the transistors adjacent in the row direction of the magnetic memory unit S, the drain regions of the transistors, There is no need to provide an isolation region between the transistors, and the nonvolatile semiconductor memory device can be downsized.

[Operation]
Next, the operation when the nonvolatile semiconductor memory device according to the first embodiment of the present invention simultaneously performs data writing or data reading with respect to a plurality of different memory cells will be described.

  First, a case will be described in which data is simultaneously written to a plurality of magnetic storage units corresponding to the same row of the magnetic storage unit S, for example, the magnetic storage unit S13 and the magnetic storage unit S14.

  FIG. 7 is a diagram showing the current supplied to the memory array in FIG. FIG. 8 is a diagram showing the current supplied to the memory array in FIG.

  Referring to FIGS. 7 and 8, the solid arrow indicates the current flowing between the source line SL1 and the bit line BL_EVEN4, and the dotted arrow indicates the current flowing between the source line SL0 and the bit line BL_ODD4. However, the current flowing through the back surface is indicated by a one-dot chain line. By flowing current in this manner, data writing or data reading is simultaneously performed on the magnetic storage unit S13 and the magnetic storage unit S14 corresponding to the same row of the magnetic storage unit S.

  More specifically, since the magnetic memory unit S13 and the magnetic memory unit S14 correspond to the same row, the control circuit 10 selects different bit lines BL for each magnetic memory unit, that is, for the magnetic memory unit S13. The bit line BL_EVEN4 is selected, and the bit line BL_ODD4 is selected for the magnetic memory unit S14.

  Further, the control circuit 10 selects the source line SL0 for the magnetic memory unit S13 and selects the source line SL1 for the magnetic memory unit S14.

  In addition, the control circuit 10 selects the word line WL_EVEN0 in order to turn on the bit line switching transistor MB13_EVEN corresponding to the magnetic memory unit S13 and corresponding to the bit line BL_EVEN4 selected by the bit line driving circuit 4. In addition, the control circuit 10 selects the word line WL_ODD1 to turn on the bit line switching transistor MB14_ODD corresponding to the magnetic memory unit S14 and corresponding to the bit line BL_ODD4 selected by the bit line driving circuit 4.

  Then, control circuit 10 outputs internal address control signal ADCONT representing the selection result to word line drive circuit 2, bit line drive circuit 4 and source line drive circuit 5. Further, the control circuit 10 outputs an internal write control signal WRCONT representing write data for the magnetic storage unit S13 and the magnetic storage unit S14 to the bit line drive circuit 4 and the source line drive circuit 5.

  Bit line drive circuit 4 supplies a voltage to bit line BL_EVEN4 and bit line BL_ODD4 based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  Source line drive circuit 5 supplies a voltage to source line SL0 and source line SL1 based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  Word line drive circuit 2 drives word line WL_EVEN0 and word line WL_ODD1 to a selected state based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  That is, the control circuit 10 controls the word line driving circuit 2, the bit line driving circuit 4, and the source line driving circuit 5, and according to the logic level of the write data to the magnetic storage unit S13 between the bit line BL_EVEN4 and the source line SL0. By supplying a write current in the opposite direction, data is written to the magnetic storage unit S13. In parallel with this, the control circuit 10 supplies a write current having a direction corresponding to the logic level of the write data to the magnetic storage unit S14 between the bit line BL_ODD4 and the source line SL1, thereby providing the magnetic storage unit S14 with the write current. Data is written to the data.

  Next, a case where data is read simultaneously from the magnetic storage unit S13 and the magnetic storage unit S14 will be described. The operation of the control unit 10 selecting the bit line BL, the source line SL, and the bit line switching transistor MB corresponding to the magnetic storage unit S13 and the magnetic storage unit S14 is the same as that at the time of data writing. Do not repeat.

  The bit line driving circuit 4 supplies a bias voltage for reading data to the bit line BL_ODD4 and the bit line BL_EVEN4 based on the internal address control signal ADCONT and the internal read control signal RDCONT received from the control circuit 10.

  Source line drive circuit 5 supplies, for example, a ground voltage to source line SL0 and source line SL1 based on internal address control signal ADCONT and internal read control signal RDCONT received from control circuit 10.

  Word line drive circuit 2 drives word line WL_ODD0 and word line WL_EVEN1 to a selected state based on internal address control signal ADCONT and internal read control signal RDCONT received from control circuit 10.

  The read circuit 7 detects the amount of read current flowing through the bit line BL_ODD4 and the bit line BL_EVEN4 based on the internal address control signal ADCONT and the internal read control signal RDCONT received from the control circuit 10, respectively. Data stored in the magnetic storage unit S14 is detected.

  Therefore, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, when n = 2, data writing or data reading is simultaneously performed on two magnetic storage units S corresponding to the same row. Can be performed. Furthermore, by configuring the nonvolatile semiconductor memory device to satisfy 3 ≦ n, it is possible to simultaneously write or read data to n magnetic storage units S corresponding to the same row.

  Next, a case will be described in which data writing or data reading is simultaneously performed on a plurality of magnetic storage units S corresponding to different rows and different columns of the magnetic storage unit S, for example, the magnetic storage unit S13 and the magnetic storage unit S11.

  In this case, the control circuit 10 selects the bit line BL_EVEN4 and the bit line switching transistor MB13_EVEN, or the bit line BL_ODD4 and the bit line switching transistor MB13_ODD for the magnetic memory unit S13. Further, the control circuit 10 selects the source line SL0.

  Further, the control circuit 10 selects the bit line BL_EVEN3 and the bit line switching transistor MB11_EVEN or the bit line BL_ODD3 and the bit line switching transistor MB11_ODD for the magnetic memory unit S11. In addition, the control circuit 10 selects the source line SL1.

  Then, the control circuit 10 performs data writing or data reading with respect to the magnetic memory unit S13 by passing a write current or a read current between the bit line BL_EVEN4 and the source line SL0. In addition, the control circuit 10 performs data writing or data reading with respect to the magnetic memory unit S14 by passing a write current or a read current between the bit line BL_EVEN3 and the source line SL1.

  Next, data is simultaneously written to a plurality of magnetic storage units S corresponding to the same column, for example, magnetic storage units S1, S4, S7, S10 and S13, and H level is applied to the magnetic storage units S1 and S4. A case where data is written and L level data is written to the magnetic storage units S7, S10, and S13 will be described.

  Here, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, for example, a write current is passed in the direction from the terminal T1 to the terminal T2 of the magnetic memory unit S, that is, from the source line SL to the bit line BL. Thus, L data is written in the magnetic memory unit S, and H data is written in the magnetic memory unit S by passing a write current in the direction from the bit line BL to the source line SL.

  FIG. 9 shows voltage waveforms and current waveforms when the nonvolatile semiconductor memory device according to the first embodiment of the present invention simultaneously writes or reads data to a plurality of magnetic storage units S corresponding to the same column. FIG.

  Referring to the figure, here, the current flowing from source line SL to bit line BL is a positive current, and the current flowing from bit line BL to source line SL is a negative current.

  The control circuit 10 selects, for example, the bit lines BL_ODD0 to BL_ODD4 because the magnetic storage units S1, S4, S7, S10, and S13 correspond to the same column.

  In addition, the control circuit 10 selects the source line SL0 corresponding to the magnetic storage units S1, S4, S7, S10, and S13.

  The control circuit 10 also turns on the bit line switching transistors MB1_ODD, MB4_ODD, MB7_ODD, MB10_ODD, and MB13_ODD corresponding to the magnetic storage units S1, S4, S7, S10, and S13 and corresponding to the selected bit lines BL_ODD0 to BL_ODD4. Therefore, the word line WL_ODD0 is selected.

  Then, control circuit 10 outputs internal address control signal ADCONT representing the selection result to word line drive circuit 2, bit line drive circuit 4 and source line drive circuit 5. Further, the control circuit 10 outputs an internal write control signal WRCONT representing write data for the magnetic storage units S 1, S 4, S 7, S 10 and S 13 to the bit line drive circuit 4 and the source line drive circuit 5.

  The bit line driving circuit 4 supplies a ground voltage to the bit lines BL_ODD0 to BL_ODD4 based on the internal address control signal ADCONT and the internal write control signal WRCONT received from the control circuit 10.

  Source line drive circuit 5 supplies a positive voltage to source line SL 0 based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  Word line drive circuit 2 drives word line WL_ODD0 to a selected state based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  That is, the control circuit 10 controls the word line driving circuit 2, the bit line driving circuit 4, and the source line driving circuit 5, and first causes a positive write current to flow through the magnetic storage units S1, S4, S7, S10, and S13. As a result, the same L data is written to the magnetic storage units S1, S4, S7, S10 and S13.

  Next, the control circuit 10 controls the bit line drive circuit 4 to supply a positive voltage to the bit lines BL_ODD0 and BL_ODD1 corresponding to the magnetic storage units S1 and S4 whose write data has a logic level of H level. In addition, the control circuit 10 controls the bit line driving circuit 4 to supply the ground voltage to the bit lines BL_ODD2 to BL_ODD4 corresponding to the magnetic storage units S7, S10, and S13 in which the logic level of the write data is L level.

  Further, the control circuit 10 controls the source line driving circuit 5 to supply the ground voltage to the source line SL0. Note that the word line driving circuit 2 drives the word line WL_ODD0 to a selected state.

  That is, the control circuit 10 controls the word line driving circuit 2, the bit line driving circuit 4, and the source line driving circuit 5 to write the same L data in the magnetic storage units S1, S4, S7, S10, and S13. By supplying a negative write current in the opposite direction only to the magnetic storage units S1 and S4, H data is written only to the magnetic storage units S1 and S4.

  Therefore, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, data of different logic levels can be written to the plurality of magnetic memory units S corresponding to the same column of the magnetic memory unit S. .

  For data reading, the read current can be made constant between the source line SL and the bit line BL, and the bit lines BL corresponding to the magnetic storage units S in the same column are different from each other. It is possible to simultaneously read data from a plurality of magnetic storage sections S corresponding to the same column of S.

  By the way, in the configuration employing the external magnetization reversal method in the dual port MRAM, there is a problem that data writing is erroneously performed on a memory cell that is not a write target. However, in the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the magnetic memory unit S stores data based on a write current flowing between the terminal T1 and the terminal T2, for example, a spin injection current. Further, the bit line switching transistor MB makes the connection between the terminal T2 of the magnetic storage unit S and the bit line BL conductive or non-conductive based on the voltage supplied to the word line WL. With such a configuration, a spin injection current can be supplied only to the magnetic storage unit S to be written, and even if data is written to different magnetic storage units S at the same time, It is possible to prevent erroneous data writing.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a nonvolatile semiconductor memory device in which a source line SL can be selected for data writing and data reading with respect to one magnetic memory unit S, compared to the first embodiment. Configurations and operations other than those described below are the same as those of the nonvolatile semiconductor memory device according to the first embodiment.

[Constitution]
FIG. 10 is a circuit diagram showing a configuration of a memory array of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

  Referring to FIG. 1, memory array 1 includes a plurality of magnetic storage units S, a plurality of word lines (first control lines) WL, a plurality of bit lines (second control lines) BL, A plurality of source lines (third control lines) SL, a plurality of bit line switching transistors (first control transistors) MB, and a plurality of source line switching transistors (second control transistors) MS Prepare.

  In the figure, typically, the magnetic storage units S1 to S12, the word lines WL_EVEN0 to WL_EVEN5, the word lines WL_ODD0 to WL_ODD5, the bit lines BL_EVEN0 to BL_EVEN1 and the bit lines BL_ODD0 to BL_ODD1, the source lines SL_EVEN0 to SL_EVEN1 and SL_ODDD0 to ODD1 Bit line switching transistors MB0_EVEN to MB12_EVEN and MB0_ODD to MB12_ODD, and source line switching transistors MS0_EVEN to MS12_EVEN and MS0_ODD to MS12_ODD are denoted by reference numerals. The bit line switching transistors MB0_EVEN to MB12_EVEN and MB0_ODD to MB12_ODD may be abbreviated as MB0_E to MB12_E and MB0_O to MB12_O in some cases. The source line switching transistors MS0_EVEN to MS12_EVEN and MS0_ODD to MS12_ODD may be abbreviated as MS0_E to MS12_E and MS0_O to MS12_O in some cases.

  A word line WL is arranged corresponding to each column of the magnetic memory unit S, and a bit line BL and a source line SL are arranged corresponding to each row of the magnetic memory unit S.

  N (n is a natural number of 1 or more) word lines WL are arranged for one column of each magnetic storage unit S.

N bit lines BL are arranged for one row of each magnetic storage unit S.
N source lines SL are arranged for one row of each magnetic storage unit S.

  The n bit line switching transistors MB are arranged for each magnetic memory unit S, the control electrodes, that is, the gates are respectively connected to the word lines WL corresponding to the columns formed by the corresponding magnetic memory unit S, and One conduction electrode, ie, source or drain, is connected to each bit line BL corresponding to the row that the magnetic memory unit S constitutes, and the other conduction electrode, ie, drain or source, is connected to the terminal T2 of the corresponding magnetic memory unit S. The

  The bit line switching transistor MB makes the terminal T2 of the magnetic memory unit S and the bit line BL conductive or non-conductive based on the voltage supplied to the word line WL.

  The n source line switching transistors MS are arranged for each magnetic storage unit S, connected to each word line WL corresponding to the column formed by the corresponding magnetic storage unit S, and the corresponding magnetic storage unit S is The source lines SL are connected to the corresponding rows.

  The source line switching transistor MS makes the connection between the terminal T1 of the magnetic storage unit S and the source line SL conductive or non-conductive based on the voltage supplied to the word line WL.

  Hereinafter, the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described assuming that n = 2.

  The connection relationship of the magnetic storage unit S will be described in detail. The magnetic storage unit S1 has a terminal T1 connected to the sources of the source line switching transistors MS1_EVEN and MS1_ODD, and a terminal T2 connected to the sources of the bit line switching transistors MB1_EVEN and MB1_ODD. The drain of the bit line switching transistor MB1_EVEN is connected to the bit line BL_EVEN0, and the gate is connected to the word line WL_EVEN0. The drain of the bit line switching transistor MB1_ODD is connected to the bit line BL_ODD0, and the gate is connected to the word line WL_ODD0. The drain of the source line switching transistor MS1_EVEN is connected to the source line SL_EVEN0, and the gate is connected to the word line WL_EVEN0. The drain of the source line switching transistor MS1_ODD is connected to the source line SL_ODD0, and the gate is connected to the word line WL_ODD0.

  The magnetic storage unit S2 has a terminal T1 connected to the sources of the source line switching transistors MS2_EVEN and MS2_ODD, and a terminal T2 connected to the sources of the bit line switching transistors MB2_EVEN and MB2_ODD. The drain of the bit line switching transistor MB2_EVEN is connected to the bit line BL_EVEN0, and the gate is connected to the word line WL_EVEN1. The drain of the bit line switching transistor MB2_ODD is connected to the bit line BL_ODD0, and the gate is connected to the word line WL_ODD1. The drain of the source line switching transistor MS2_EVEN is connected to the source line SL_EVEN0, and the gate is connected to the word line WL_EVEN1. The drain of the source line switching transistor MS2_ODD is connected to the source line SL_ODD0, and the gate is connected to the word line WL_ODD1.

  The magnetic memory unit S7 has a terminal T1 connected to the sources of the source line switching transistors MS7_EVEN and MS7_ODD, and a terminal T2 connected to the sources of the bit line switching transistors MB7_EVEN and MB7_ODD. The drain of the bit line switching transistor MB7_EVEN is connected to the bit line BL_EVEN1, and the gate is connected to the word line WL_EVEN0. The drain of the bit line switching transistor MB7_ODD is connected to the bit line BL_ODD1, and the gate is connected to the word line WL_ODD0. The drain of the source line switching transistor MS7_EVEN is connected to the source line SL_EVEN1, and the gate is connected to the word line WL_EVEN0. The drain of the source line switching transistor MS7_ODD is connected to the source line SL_ODD1, and the gate is connected to the word line WL_ODD0.

  Since the connection relation around the magnetic storage units S3 to S6 and S8 to S12 is the same as described above, detailed description will not be repeated here.

  FIG. 11 is a diagram showing a layout of the memory array of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 12 is a diagram schematically showing a cross-sectional structure of the memory array viewed from the direction A in FIG. 13 is a cross-sectional view of the memory array taken along the line B-C in FIG.

  Referring to FIGS. 12 and 13, bit line BL_ODD1 is connected to the drain of bit line switching transistor MB9_ODD in substrate SUB. The bit line BL_EVEN1 is not shown in the drawing because it is located on the back surface of the bit line BL_ODD1, but is connected to the drain of the bit line switching transistor MB9_EVEN in the substrate SUB. The source line SL_ODD1 is not shown in the drawing because it is located on the back surface of the bit line BL_ODD1, but is connected to the drain of the source line switching transistor MS9_ODD in the substrate SUB. The source line SL_EVEN1 is not shown in the drawing because it is located on the back surface of the bit line BL_ODD1, but is connected to the drain of the source line switching transistor MS9_EVEN in the substrate SUB. The terminal T1 of the magnetic memory unit S9 is connected to the sources of the source line switching transistors MS9_EVEN and MS9_ODD. The word line WL_EVEN2 is connected to the gates of the bit line switching transistor MB9_EVEN and the source line switching transistor MS9_EVEN. The word line WL_ODD2 is connected to the gates of the bit line switching transistor MB9_ODD and the source line switching transistor MS9_ODD. The terminal T2 of the magnetic memory unit S9 is connected to the sources of the bit line switching transistors MB9_EVEN and MB9_ODD.

  Referring to FIG. 11, word line WL is arranged substantially parallel to each magnetic storage unit S column. The bit line BL and the source line SL are arranged substantially in parallel with the row of each magnetic storage unit S.

  Here, in the configuration in which the source line SL is arranged substantially perpendicular to the bit line BL as in the nonvolatile semiconductor memory device according to the first embodiment, different end portions of the memory array 1, for example, as shown in FIG. Further, since it is necessary to supply voltages to the right end and the lower end of the memory array 1, the circuit configuration becomes complicated. However, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, since the source line SL is arranged substantially parallel to the bit line BL, for example, only at the right end of the memory array 1 as shown in FIG. A voltage may be supplied, and the circuit configuration of the nonvolatile semiconductor memory device can be simplified.

  FIG. 14 is a diagram showing the active region and the isolation region in FIG. FIG. 15 shows the active region and the isolation region in FIG. FIG. 16 shows the active region and the isolation region in FIG.

  Referring to FIG. 14, the shaded portion is the active region, and the region other than the shaded portion is the separation region. A portion surrounded by a thick line indicates a source region or a drain region in the second row of the magnetic memory portion S. Referring to FIG. 15, a portion surrounded by a thick line is an active region.

  Referring to FIG. 14, active regions ACT <b> 1 to ACT <b> 4 of bit line switching transistors MB are formed corresponding to the respective rows of magnetic storage units S <b> 1 to S <b> 12. A plurality of word lines WL cross the active regions ACT1 to ACT4.

  The word line WL_EVEN2 and the word line WL_ODD2 are arranged substantially parallel to the columns of the magnetic storage units S3 and S9, and are arranged adjacent to the left and right of the magnetic storage units S3 and S9.

  The word line WL_EVEN3 and the word line WL_ODD3 are arranged substantially parallel to the columns of the magnetic storage units S4 and S10, and are arranged adjacent to the left and right of the magnetic storage units S4 and S10.

  In addition, the region surrounded by the thick dotted line, that is, the active region divided by the adjacent word line WL and not having the magnetic storage unit S is connected to every other bit line BL.

  Referring to FIGS. 14 to 16, bit line switching transistors MB9_ODD corresponding to the magnetic storage units S9 and S10 adjacent in the row direction of the magnetic storage unit S and connected to the same bit line BL_ODD1, and MB10_ODD is arranged adjacently between the magnetic storage unit S9 and the magnetic storage unit S10. The drain region is common between the bit line switching transistors MB9_ODD and MB10_ODD.

  That is, the active region divided by the word line WL_ODD2 and the word line WL_ODD3 is commonly used as the drain region of the bit line switching transistors MB9_ODD and MB10_ODD. The active region divided by the word line WL_EVEN1 and the word line WL_EVEN2 is commonly used as the drain region of the bit line switching transistors MB8_EVEN and MB_9EVEN.

  Therefore, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, the transistor regions adjacent in the row direction of the magnetic memory unit S can be shared to reduce the size.

[Operation]
Next, an operation when the nonvolatile semiconductor memory device according to the second embodiment of the present invention simultaneously performs data writing or data reading with respect to a plurality of different memory cells will be described.

  First, a case where data is simultaneously written to a plurality of magnetic storage units corresponding to the same row of the magnetic storage unit S, for example, the magnetic storage unit S9 and the magnetic storage unit S11 will be described.

  FIG. 17 is a diagram showing the current supplied to the memory array in FIG. FIG. 18 schematically shows a cross-sectional structure of the memory array as seen from the direction A in FIG. FIG. 19 is a cross-sectional view of the memory array taken along the line B-C in FIG. FIG. 20 is a diagram schematically showing a cross-sectional structure of the memory array as seen from the direction D of FIG. FIG. 21 is a cross-sectional view showing the EF cross section of FIG. 17 of the memory array.

  Referring to FIGS. 17 to 21, a solid arrow indicates a current flowing between source line SL_EVEN1 and bit line BL_EVEN1, and a dotted arrow indicates a current flowing between source line SL_ODD1 and bit line BL_ODD1. By flowing current in this manner, data writing or data reading is simultaneously performed on the magnetic storage unit S9 and the magnetic storage unit S11 corresponding to the same row of the magnetic storage unit S.

  More specifically, since the magnetic storage unit S9 and the magnetic storage unit S11 correspond to the same row, the control circuit 10 selects different bit lines BL for each magnetic storage unit, that is, for the magnetic storage unit S9. The bit line BL_EVEN1 is selected, and the bit line BL_ODD1 is selected for the magnetic memory unit S11. Further, the control circuit 10 selects the source line SL_EVEN1 for the magnetic memory unit S9 and selects the source line SL_ODD1 for the magnetic memory unit S11.

  Further, the control circuit 10 turns on the word line WL_EVEN2 to turn on the bit line switching transistor MB9_EVEN and the source line switching transistor MS9_EVEN corresponding to the magnetic storage unit S9 and corresponding to the selected bit line BL_EVEN1 and source line SL_EVEN1. select. In addition, the control circuit 10 turns on the bit line switching transistor MB11_ODD and the source line switching transistor MS11_ODD corresponding to the magnetic storage unit S11 and corresponding to the selected bit line BL_ODD1 and source line SL_ODD1, so that the word line WL_ODD4 is turned on. select.

  Then, control circuit 10 outputs internal address control signal ADCONT representing the selection result to word line drive circuit 2, bit line drive circuit 4 and source line drive circuit 5. Further, the control circuit 10 outputs an internal write control signal WRCONT representing write data for the magnetic storage unit S9 and the magnetic storage unit S11 to the bit line drive circuit 4 and the source line drive circuit 5.

  Bit line drive circuit 4 supplies a voltage to bit line BL_EVEN1 and bit line BL_ODD1 based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  Source line drive circuit 5 supplies a voltage to source line SL_EVEN1 and source line SL_ODD1 based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  Word line drive circuit 2 drives word line WL_EVEN2 and word line WL_ODD4 to a selected state based on internal address control signal ADCONT and internal write control signal WRCONT received from control circuit 10.

  In other words, the control circuit 10 controls the word line driving circuit 2, the bit line driving circuit 4, and the source line driving circuit 5, and according to the logic level of the write data for the magnetic storage unit S9 between the bit line BL_EVEN1 and the source line SL_EVEN1. By supplying a write current in the opposite direction, data is written to the magnetic storage unit S9. In parallel with this, the control circuit 10 supplies a write current having a direction according to the logic level of the write data to the magnetic storage unit S11 between the bit line BL_ODD1 and the source line SL_ODD1, thereby providing the magnetic storage unit S11 with the write current. Data is written to the data.

  Next, a case where data is read simultaneously from the magnetic storage unit S9 and the magnetic storage unit S11 will be described. The operation of the control unit 10 selecting the bit line BL, the source line SL, and the bit line switching transistor MB corresponding to the magnetic storage unit S9 and the magnetic storage unit S11 is the same as that at the time of data writing. Do not repeat.

  The bit line driving circuit 4 supplies a bias voltage for reading data to the bit line BL_EVEN1 and the bit line BL_ODD1 based on the internal address control signal ADCONT and the internal read control signal RDCONT received from the control circuit 10.

  Based on the internal address control signal ADCONT and the internal read control signal RDCONT received from the control circuit 10, the source line drive circuit 5 supplies, for example, a ground voltage to the source line SL_EVEN1 and the source line SL_ODD1.

  Word line drive circuit 2 drives word line WL_EVEN2 and word line WL_ODD4 to a selected state based on internal address control signal ADCONT and internal read control signal RDCONT received from control circuit 10.

  Based on the internal address control signal ADCONT and the internal read control signal RDCONT received from the control circuit 10, the read circuit 7 detects the current amounts of the read currents flowing through the bit line BL_EVEN1 and the bit line BL_ODD1, respectively, and the magnetic storage unit S9 and Data stored in the magnetic storage unit S11 is detected.

  Therefore, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, when n = 2, data writing or data reading is simultaneously performed on two magnetic storage units S corresponding to the same row. Can be performed. Furthermore, by configuring the nonvolatile semiconductor memory device to satisfy 3 ≦ n, it is possible to simultaneously write or read data to n magnetic storage units S corresponding to the same row.

  Next, a case where data writing or data reading is simultaneously performed on a plurality of magnetic storage units S corresponding to different rows and different columns of the magnetic storage unit S, for example, the magnetic storage unit S9 and the magnetic storage unit S4 will be described.

  In this case, the control circuit 10 uses the bit line BL_EVEN1, the source line SL_EVEN1, the word line WL_EVEN2, the bit line switching transistor MB9_EVEN and the source line switching transistor MS9_EVEN, or the bit line BL_ODD1, the source line SL_ODD1, the word line for the magnetic storage unit S9. WL_ODD2, bit line switching transistor MB9_ODD, and source line switching transistor MS9_ODD are selected.

  The control circuit 10 also controls the bit line BL_EVEN0, the source line SL_EVEN0, the word line WL_EVEN3, the bit line switching transistor MB4_EVEN and the source line switching transistor MS4_EVEN, or the bit line BL_ODD0, the source line SL_ODD0, and the word line WL_ODD3 with respect to the magnetic storage unit S4. The bit line switching transistor MB4_ODD and the source line switching transistor MS4_ODD are selected.

  Then, the control circuit 10 performs data writing or data reading with respect to the magnetic memory unit S9 by passing a write current or a read current between the bit line BL_EVEN1 and the source line SL_EVEN1. In addition, the control circuit 10 performs data writing or data reading with respect to the magnetic memory unit S4 by passing a write current or a read current between the bit line BL_EVEN0 and the source line SL_EVEN0.

  Next, a case where data is simultaneously written to a plurality of magnetic storage units S corresponding to the same column, for example, magnetic storage units S3 and S9 will be described.

  In this case, the control circuit 10 uses the bit line BL_EVEN0, the source line SL_EVEN0, the word line WL_EVEN2, the bit line switching transistor MB3_EVEN and the source line switching transistor MS3_EVEN, or the bit line BL_ODD0, the source line SL_ODD0, the word line for the magnetic storage unit S3. WL_ODD2, bit line switching transistor MB3_ODD, and source line switching transistor MS3_ODD are selected.

  Further, the control circuit 10 controls the bit line BL_EVEN1, the source line SL_EVEN1, the word line WL_EVEN2, the bit line switching transistor MB9_EVEN and the source line switching transistor MS9_EVEN, or the bit line BL_ODD1, the source line SL_ODD1, and the word line WL_ODD2 with respect to the magnetic storage unit S9. The bit line switching transistor MB9_ODD and the source line switching transistor MS9_ODD are selected.

  Therefore, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, data writing or data reading can be simultaneously performed on a plurality of magnetic memory units S corresponding to the same column of the magnetic memory unit S. it can.

  Further, in the nonvolatile semiconductor memory device according to the second embodiment of the present invention, similarly to the nonvolatile semiconductor memory device according to the first embodiment, the spin injection current is applied only to the magnetic storage unit S to be written. Even if data is written to different magnetic storage units S at the same time, it is possible to prevent data from being erroneously written to the magnetic storage units S that are not to be written.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a diagram schematically showing an overall configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 1 is a circuit diagram showing a configuration of a memory array of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. 1 is a diagram showing a layout of a memory array of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 4 is a diagram schematically showing a cross-sectional structure of a memory array viewed from the direction A in FIG. 3. It is the figure which showed the active region and the isolation region in FIG. FIG. 5 is a diagram showing an active region and a separation region in FIG. 4. FIG. 4 is a diagram showing a current supplied to the memory array in FIG. 3. FIG. 5 is a diagram showing a current supplied to the memory array in FIG. 4. FIG. 6 is a diagram illustrating voltage waveforms and current waveforms when the nonvolatile semiconductor memory device according to the first embodiment of the present invention simultaneously performs data writing or data reading with respect to a plurality of magnetic storage units S corresponding to the same column. is there. FIG. 6 is a circuit diagram showing a configuration of a memory array of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. It is a figure which shows the layout of the memory array of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention. FIG. 12 is a diagram schematically showing a cross-sectional structure of the memory array viewed from the direction A in FIG. 11. It is sectional drawing which shows the BC cross section in FIG. 11 of a memory array. It is the figure which showed the active region and isolation region in FIG. It is the figure which showed the active region and the isolation region in FIG. It is the figure which showed the active region and the isolation region in FIG. It is the figure which showed the electric current supplied to a memory array in FIG. FIG. 12 is a diagram schematically showing a cross-sectional structure of the memory array viewed from the direction A in FIG. 11. FIG. 18 is a cross-sectional view of the memory array taken along the line B-C in FIG. 17. FIG. 12 is a diagram schematically showing a cross-sectional structure of the memory array as viewed from a direction D in FIG. 11. It is sectional drawing which shows the EF cross section in FIG. 17 of a memory array.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Memory array, 2 Word line drive circuit, 4 Bit line drive circuit, 5 Source line drive circuit, 7 Read circuit, 8 Output circuit, 10 Control circuit, 12 Power supply circuit, 13 Substrate bias circuit, S, S1-S15 Magnetic memory , WL, WL_EVEN0 to WL_EVEN5, WL_ODD0 to WL_ODD5 Word line (first control line), BL, BL_EVEN0 to BL_EVEN4, BL_ODD0 to BL_ODD4 Bit line (second control line), SL, SL0 to SL2, SL_EVEN0 to SL_EVEN1, SL_ODD0 to ODD1 Source line (third control line), MB, MB0_EVEN to MB15_EVEN, MB0_ODD to MB15_ODD, MB0_E to MB15_E, MB0_O to MB15_O Bit line switching transistors (first Control transistor), T1 terminal (first terminal), T2 terminal (second terminal), MS, MS0_EVEN to MS12_EVEN, MS0_ODD to MS12_ODD, MS0_E to MS12_E, MS0_O to MS12_O Source line switching transistor (second control transistor) ), ACT1-ACT5 active region.

Claims (7)

A plurality of magnetic storage units arranged in a matrix, having a first terminal and a second terminal, and storing data based on a write current flowing between the first terminal and the second terminal;
A first control line arranged with n (n is a natural number of 1 or more) for one column of each of the magnetic storage units;
N second control lines arranged for one row of each magnetic storage unit;
A third control line arranged corresponding to the row or column of each magnetic storage unit and connected to the first terminal of the corresponding magnetic storage unit;
A first control transistor having a control electrode, a first conduction electrode, and a second conduction electrode, and being arranged for each n of the magnetic storage units,
The n first control transistors arranged for each magnetic memory unit are connected to the first control lines corresponding to the columns formed by the corresponding magnetic memory units, respectively. The first conduction electrode is connected to each of the second control lines corresponding to the rows formed by the magnetic memory unit, and the second conduction electrode is connected to the second terminal of the corresponding magnetic memory unit. A nonvolatile semiconductor memory device to be connected. The first control line is disposed substantially parallel to the row of each magnetic storage unit,
The second control line is disposed substantially parallel to the row of each magnetic storage unit,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the third control line is arranged corresponding to a column of each of the magnetic memory units, and is arranged substantially parallel to the column of each of the magnetic memory units. The nonvolatile semiconductor memory device further includes:
A control circuit for performing control to supply current to the first to third control lines;
The control circuit supplies the write current in a predetermined direction to all the magnetic storage units connected to the third control line corresponding to a predetermined row or column of each magnetic storage unit when writing data, 2. The nonvolatile memory according to claim 1, wherein the write current in a direction opposite to the predetermined direction is supplied to a part or all of the magnetic storage units connected to the third control line corresponding to the predetermined row or column. Semiconductor memory device.   The two first control transistors respectively corresponding to the two magnetic storage units adjacent in the row direction of the magnetic storage units and connected to the same second control line are the two The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is disposed adjacent to each other between the magnetic memory portions, and a source region or a drain region of each of the first control transistors disposed adjacent to each other is common. N third control lines are arranged for one row of each magnetic storage unit;
The nonvolatile semiconductor memory device further includes:
A second control transistor having a control electrode, a first conduction electrode, and a second conduction electrode, wherein n pieces are arranged for each of the magnetic memory units;
The n second control transistors arranged for each of the magnetic memory units are connected to the first control lines corresponding to the columns formed by the corresponding magnetic memory units, respectively. The first conductive electrode is connected to each of the third control lines corresponding to the row formed by the magnetic memory unit, and the second conductive electrode is connected to the first terminal of the corresponding magnetic memory unit. The nonvolatile semiconductor memory device according to claim 1, which is connected.   The nonvolatile semiconductor memory device according to claim 1, wherein n is a natural number of 2 or more. The first control line is disposed substantially parallel to the row of each magnetic storage unit,
The second control line is disposed substantially parallel to the row of each magnetic storage unit,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the third control line is arranged corresponding to a row of each magnetic storage unit, and is arranged substantially parallel to the row of each magnetic storage unit.

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