JP2012195038A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device with a smaller space area on a surface of a semiconductor substrate.SOLUTION: Each memory cell MC of this MRAM includes a magnetic resistor 18 and two access transistors 19a and 19b. Drains of the transistors 19a and 19b are connected to a corresponding bit line BL via the magnetic resistor 18, gates thereof are connected to a corresponding word line WL, and sources thereof are connected to a source line SL and an auxiliary line AL, respectively. Thus, the source of the access transistors 19b and the source of a driver transistor 23 included in a DL driver 14 can be used in common, thereby reducing a space area on a surface of a silicon substrate 31.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device including a memory cell that magnetically stores a data signal.

  In recent years, MRAM (Magnetic Random Access Memory) has attracted attention as a semiconductor memory device capable of storing nonvolatile data with low power consumption (see, for example, Non-Patent Document 1).

  The MRAM includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, a plurality of digit lines provided corresponding to the plurality of rows, respectively. And a plurality of bit lines provided corresponding to a plurality of columns. Each memory cell is connected in series with a magnetoresistive element that stores a data signal according to a resistance level change, and between the corresponding bit line and the reference voltage line, and its gate is connected to the corresponding word line. A connected access transistor.

  During a write operation, a magnetizing current is passed through the selected digit line to place the magnetoresistive element of each memory cell corresponding to the digit line in a half-selected state, and the selected bit line is set to the logic of the data signal. A data current is written in the magnetoresistive element of the memory cell arranged at the intersection of the selected digit line and the bit line by supplying a write current in a corresponding direction.

  During the read operation, the selected word line is set to the selection level, the access transistor of each memory cell corresponding to the word line is made conductive, and a voltage sufficiently lower than that during the write operation is applied to the selected bit line. Then, the current flowing through the magnetoresistive element of the selected memory cell via the bit line is detected, and the stored data of the magnetoresistive element is read based on the detection result.

  Further, in an MRAM including two memory blocks and two digit line drivers, each digit line driver including a driver transistor provided corresponding to each digit line, a driver transistor corresponding to one memory block is connected to the other memory. In some cases, the driver transistors corresponding to the other memory block are arranged in one block and arranged in one memory block. In this MRAM, the layout area can be reduced by optimizing the size of the access transistor and disposing the driver transistor in the vacant region (see, for example, Patent Document 1).

JP 2010-67309 A

2004 Symposium on VLSI Circuits Digest of Technical Papers p.450-453 A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture

  However, in Patent Document 1, as shown in FIG. 6, an empty area that cannot be used for either the driver transistor or the access transistor is generated on the surface of the silicon substrate, and the size of the driver transistor and the access transistor is sufficiently increased. There was a problem that I couldn't.

  If the size of the driver transistor is small, the magnetizing current is insufficient and the yield decreases. If the size of the access transistor is small, the parasitic resistance value connected in series with the magnetoresistive element during the read operation increases, and the access time becomes long, leading to deterioration in read performance and insufficient margin.

  Therefore, a main object of the present invention is to provide a semiconductor memory device having a small free area on the surface of a semiconductor substrate.

  A semiconductor memory device according to the present invention is a semiconductor memory device formed on the surface of a semiconductor substrate, and a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of memory cells provided corresponding to the plurality of rows, respectively. Word lines, a plurality of digit lines provided corresponding to a plurality of rows, a plurality of bit lines provided corresponding to a plurality of columns, and a plurality of bit lines provided corresponding to a plurality of digit lines, respectively. A memory array including auxiliary wiring is provided. One end of each digit line is connected to a corresponding auxiliary wiring. Each memory cell has a first electrode connected to a corresponding bit line, and a magnetoresistive element that stores a data signal according to a change in the resistance value level, and a drain connected to the second electrode of the magnetoresistive element. The first and second access transistors have their sources connected to the reference voltage line and the corresponding auxiliary wiring, respectively, and their gates connected to the corresponding word line. The semiconductor memory device further includes a write circuit for writing a data signal to a selected memory cell among the plurality of memory cells. This write circuit applies a predetermined voltage between the other end of the selected digit line of the plurality of digit lines and the auxiliary wiring corresponding to the selected digit line to cause a magnetizing current to flow and is selected. A digit line driver for half-selecting the magnetoresistive element of each memory cell corresponding to the digit line, and a bit for supplying a write current in a direction corresponding to the data signal to the selected bit line of the plurality of bit lines Line driver.

  In the semiconductor memory device according to the present invention, each memory cell includes first and second access transistors, the source of the first access transistor is connected to the reference voltage line, and the source of the second access transistor corresponds to Connected to auxiliary wiring. Therefore, the source of the second access transistor and the source of the driver transistor included in the digit line driver can be made common, and an empty area that cannot be used for either the driver transistor or the access transistor can be reduced. Therefore, the size of the driver transistor and the access transistor can be increased, and the yield and reading performance can be improved.

It is a block diagram which shows the structure of MRAM by Embodiment 1 of this invention. It is a block diagram which shows the principal part of MRAM shown in FIG. FIG. 3 is a circuit diagram showing a partial configuration of a memory block and a DL driver shown in FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a remaining part of the memory block and DL driver shown in FIG. 2. FIG. 3 is a circuit diagram illustrating a configuration of a BL driver illustrated in FIG. 2. FIG. 4 is a diagram showing a layout of memory cells and transistors shown in FIG. 3. It is a circuit diagram which shows the structure of a part of memory block and DL driver of MRAM by Embodiment 2 of this invention. FIG. 8 is a circuit diagram showing a configuration of the remaining part of the memory block and DL driver shown in FIG. 7. FIG. 8 is a diagram showing a layout of the memory cell shown in FIG. 7.

[Embodiment 1]
As shown in FIG. 1, the MRAM according to the first embodiment of the present invention includes a memory array 1, a row decoder 2, a column decoder 3, a write circuit 4, and a read circuit 5. Memory array 1 includes two memory blocks MB1 and MB2. Each of memory blocks MB1 and MB2 is arranged in a plurality of rows and a plurality of columns, and each includes a plurality of memory cells that magnetically store data signals.

  The row decoder 2 selects any one of the memory blocks MB1 and MB2 and any one of a plurality of rows of the memory block MB according to the row address signal. The column decoder 3 selects one of a plurality of columns of the memory block MB selected by the row decoder 2 of the memory blocks MB1 and MB2 according to the column address signal.

  Write circuit 4 writes a data signal to a memory cell of memory block MB selected by decoders 2 and 3 during a write operation. Read circuit 5 reads data signals from the memory cells of memory block MB selected by decoders 2 and 3 during a read operation.

  FIG. 2 is a block diagram showing a main part of the MRAM shown in FIG. In FIG. 2, each of memory blocks MB1 and MB2 is arranged in a plurality of rows and a plurality of columns, each of which has a plurality of memory cells MC that magnetically store data signals, and a plurality of memory cells MC respectively provided corresponding to the plurality of rows. It includes a word line WL, a plurality of digit lines DL provided corresponding to a plurality of rows, and a plurality of bit lines BL provided corresponding to a plurality of columns, respectively.

  As shown in FIG. 3, each memory cell MC includes a magnetoresistive element 18 for storing a data signal according to a change in resistance value level, and access transistors (N-channel MOS transistors) 19a and 19b. Access transistors 19a and 19b have their gates connected to corresponding word line WL, their sources connected to source line SL and auxiliary line AL, respectively, and their drains both corresponding to corresponding bit line BL via magnetoresistive element 18. Connected to. Source line SL receives ground voltage VSS. Auxiliary wiring AL receives ground voltage VSS during a read operation and selectively receives ground voltage VSS during a write operation. The auxiliary wiring AL will be described later in detail.

  Returning to FIG. 2, DL driver 10, BL drivers 11, 12 and WL driver 13 are provided corresponding to memory block MB1, and DL driver 14, BL drivers 15, 16 and WL are provided corresponding to memory block MB2. A driver 17 is provided. The DL drivers 10 and 14 and the BL drivers 11, 12, 15, and 16 are included in the write circuit 4 of FIG. 1, and the WL drivers 13 and 17 are included in the read circuit 5 of FIG.

  The DL driver 10 is activated in response to the selection of the corresponding memory block MB1 by the row decoder 2 during the write operation, and causes the magnetizing current to flow through the digit line DL of the row selected by the row decoder 2. The magnetoresistive element 18 of each memory cell MC corresponding to the digit line DL is set to a half-selected state.

  The DL driver 14 is activated in response to the selection of the corresponding memory block MB2 by the row decoder 2 during the write operation, and causes the magnetizing current to flow through the digit line DL of the row selected by the row decoder 2. The magnetoresistive element 18 of each memory cell MC corresponding to the digit line DL is set to a half-selected state.

  The BL drivers 11 and 12 are activated in response to the selection of the corresponding memory block MB1 by the row decoder 2 during the write operation, and the logic of the write data signal is applied to the bit line BL selected by the column decoder 3. A data signal is written to the magnetoresistive element 18 corresponding to the bit line BL among the plurality of magnetoresistive elements 18 in a half-selected state by passing a current in a direction corresponding to the current.

  The BL drivers 15 and 16 are activated in response to the selection of the corresponding memory block MB2 by the row decoder 2 during the write operation, and the logic of the write data signal is applied to the bit line BL selected by the column decoder 3. A data signal is written to the magnetoresistive element 18 corresponding to the bit line BL among the plurality of magnetoresistive elements 18 in a half-selected state by passing a current in a direction corresponding to the current.

  During the read operation, the WL drivers 13 and 17 set the selected word line WL of the memory block MB selected by the row decoder 2 to the “H” level of the selection level, and each memory cell MC corresponding to the word line WL Access transistors 19a and 19b are turned on. The read circuit 5 detects the current flowing from the bit line BL selected by the column decoder 3 to the line of the ground voltage VSS, and reads the data stored in the magnetoresistive element 18 of the selected memory cell MC based on the detection result. .

  3 and 4 are diagrams showing configurations and layouts of the memory blocks MB1 and MB2 and the DL drivers 10 and 14, respectively. 3 and 4, each of memory blocks MB1 and MB2 includes memory cells MC in 4 rows and 4 columns. Actually, each of the memory blocks MB1 and MB2 includes a large number of memory cells MC, but in order to simplify the drawing, memory cells MC of 4 rows and 4 columns are shown.

  A word line WL, a digit line DL, a source line SL, an auxiliary wiring AL, and a gate line GL are provided corresponding to each row, and a bit line BL is provided corresponding to each column. Each word line WL includes a plurality of ring portions. The plurality of ring portions are arranged corresponding to the plurality of memory cells MC in the corresponding row, respectively. Each ring portion of the word line WL forms a common gate of the two access transistors 19a and 19b of the corresponding memory cell MC.

  Each digit line DL is arranged along the plurality of magnetoresistive elements 18 in the corresponding row. One end of each digit line DL of the memory block MB1 is connected to the node N1, and the other end is connected to the auxiliary wiring AL of the corresponding row of the memory block MB2. One end of each digit line DL of the memory block MB2 is connected to the node N2, and the other end is connected to the auxiliary wiring AL of the corresponding row of the memory block MB1.

  Each source line SL is arranged on one side (right side in the drawing) of the corresponding memory cell row, and is connected to the source of the access transistor 19a of each corresponding memory cell MC. The source line SL is also arranged on the other side (left side in the figure) of the leftmost memory cell row in the figure. Each source line SL receives ground voltage VSS. Each auxiliary line AL is arranged on the other side (left side in the figure) of the corresponding memory cell row, and is connected to the source of the access transistor 19b of each corresponding memory cell MC.

  That is, the gates of the access transistors 19a and 19b of each memory cell MC are connected to the corresponding word line WL, their drains are both connected to the bit line BL via the magnetoresistive element 18, and their sources are respectively corresponding to Connected to the source line SL and the auxiliary wiring AL.

  DL driver 10 is provided corresponding to P channel MOS transistor P1, N channel MOS transistor Q1, driver transistor (N channel MOS transistor) 20 provided corresponding to each row, and each memory cell MC of memory block MB2. Driver transistor (N-channel MOS transistor) 21.

  P-channel MOS transistor P1 is connected between a line of power supply voltage VDD1 and node N1, and has its gate receiving signal DLE1n. N-channel MOS transistor Q1 is connected between node N1 and the line of ground voltage VSS, and has its gate receiving signal DLE1.

  Driver transistor 20 is arranged in region A1 on the memory block MB1 side between memory blocks MB1 and MB2. Driver transistor 20 has its drain connected to the other end of corresponding digit line DL of memory block MB1, its source receiving ground voltage VSS, and its gate connected to corresponding gate line GL of memory block MB2. Driver transistor 21 is arranged on the other side (left side in the drawing) of corresponding memory cell MC in memory block MB2, connected between auxiliary line AL and source line SL, and its gate connected to corresponding gate line GL. Connected.

  Note that the resistance value of the source line SL can be reduced by connecting two adjacent source lines SL at a plurality of locations. In this case, it is preferable that the source lines SL are connected to each other by a wiring that is orthogonal to the source line SL and is formed of a wiring layer different from the source line SL.

  When signals DLE1n and DLE1 are both set to "L" level, P channel MOS transistor P1 is turned on and N channel MOS transistor Q1 is turned off, and power supply voltage VDD1 is applied to node N1. When any one of the plurality of gate lines GL of the memory block MB2 is set to the “H” level of the selection level, the driver transistors 20 and 21 corresponding to the gate line GL are turned on. Thereby, a magnetizing current flows from the line of the power supply voltage VDD1 to the line of the ground voltage VSS via the digit line DL and the driver transistors 20 and 21 of the memory block MB1 corresponding to the gate line GL.

  DL driver 14 is provided corresponding to P channel MOS transistor P2, N channel MOS transistor Q2, driver transistor (N channel MOS transistor) 22 provided corresponding to each row, and each memory cell MC of memory block MB1. Driver transistor (N-channel MOS transistor) 23.

  P-channel MOS transistor P2 is connected between a line of power supply voltage VDD1 and node N2, and has its gate receiving signal DLE2n. N channel MOS transistor Q2 is connected between node N2 and the line of ground voltage VSS, and has its gate receiving signal DLE2.

  Driver transistor 22 is arranged in area A2 on the memory block MB2 side between memory blocks MB1 and MB2. Driver transistor 22 has its drain connected to the other end of corresponding digit line DL of memory block MB2, its source receiving ground voltage VSS, and its gate connected to corresponding gate line GL of memory block MB1. Driver transistor 23 is arranged on the other side (left side in the figure) of corresponding memory cell MC in memory block MB1, connected between auxiliary line AL and source line SL, and its gate connected to corresponding gate line GL. Connected.

  When signals DLE2n and DLE2 are both set to "L" level, P channel MOS transistor P2 is turned on and N channel MOS transistor Q2 is turned off, and power supply voltage VDD1 is applied to node N2. Further, when any one of the plurality of gate lines GL of the memory block MB1 is set to the “H” level of the selection level, the driver transistors 22 and 23 corresponding to the gate line GL are turned on. As a result, a magnetizing current flows from the line of the power supply voltage VDD1 to the line of the ground voltage VSS via the digit line DL and the driver transistors 22 and 23 of the memory block MB2 corresponding to the gate line GL.

  FIG. 5 is a circuit diagram showing the configuration of the BL drivers 11 and 12. In FIG. 5, the BL driver 11 includes an inverter 25 provided corresponding to each bit line BL. Inverter 25 includes a P channel MOS transistor 26 and an N channel MOS transistor 27. P channel MOS transistor 26 is connected between a line of power supply voltage VDD2 and one end of corresponding bit line BL, and has a gate receiving signal φ1. N-channel MOS transistor 27 is connected between one end of corresponding bit line BL and the line of ground voltage VSS, and the gate thereof receives signal φ1.

  The BL driver 12 includes an inverter 28 provided corresponding to each bit line BL. Inverter 28 includes a P channel MOS transistor 29 and an N channel MOS transistor 30. P channel MOS transistor 29 is connected between the line of power supply voltage VDD2 and the other end of corresponding bit line BL, and has its gate receiving signal φ2. N channel MOS transistor 30 is connected between the other end of corresponding bit line BL and the line of ground voltage VSS, and has its gate receiving signal φ2.

  During standby, signals φ1 and φ2 are both at the “H” level. As a result, transistors 26 and 29 are turned off, transistors 27 and 30 are turned on, and each bit line BL is held at the “L” level.

  When the write data signal is at “H” level during the write operation, for example, signal φ1 of the selected column is lowered to “L” level. As a result, transistor 26 in that column becomes conductive and transistor 27 becomes nonconductive, and writing is performed from the line of power supply voltage VDD2 to the line of ground voltage VSS via transistor 26, bit line BL, and N-channel MOS transistor 30. Current flows.

  When the write data signal is at “L” level, for example, signal φ2 of the selected column is lowered to “L” level. As a result, transistor 29 in that column becomes conductive and transistor 30 becomes nonconductive, and writing is performed from the line of power supply voltage VDD2 to the line of ground voltage VSS via transistor 29, bit line BL, and N-channel MOS transistor 27. Current flows. The BL drivers 15 and 16 have the same configuration as the BL drivers 11 and 12, respectively.

  Next, the operation of the MRAM shown in FIGS. 1 to 5 will be described. In read operation and standby operation, signals DLE1n, DLE1, DLE2n, and DLE2 in FIGS. 3 and 4 are all set to the “H” level. As a result, P channel MOS transistors P1, P2 are rendered non-conductive, N channel MOS transistors Q1, Q2 are rendered conductive, and all digit lines DL and all auxiliary lines AL are at ground voltage VSS. Further, the source line SL is always at the ground voltage VSS. Therefore, the sources of the access transistors 19a and 19b of each memory cell MC are set to the ground voltage VSS. All the gate lines GL are set to the “L” level, and the driver transistors 20 to 23 are turned off.

  In the read operation, one selected word line WL among the plurality of word lines WL belonging to one selected memory block MB among the memory blocks MB1 and MB2 is set to the “H” level of the selection level. Launched. Thereby, the access transistors 19a and 19b of each memory cell MC corresponding to the selected word line WL are turned on. In addition, a predetermined voltage is applied to one selected bit line BL among a plurality of bit lines BL belonging to the selected memory block MB, and a current flows through the magnetoresistive element 18 of the selected memory cell MC. A value is detected. The current value and the reference current value are compared with each other, and the logic of the data stored in the memory cell MC is determined based on the comparison result.

  For example, when the value of the current flowing through memory cell MC is higher than the reference current value, it is determined that the storage data of memory cell MC is at “H” level (1). Conversely, when the value of the current flowing through the memory cell MC is lower than the reference current value, it is determined that the storage data of the memory cell MC is at the “L” level (0).

  During the write operation, the selected memory cell MC (for example, the first leftmost in FIG. 3) among the plurality of memory cells MC belonging to the selected memory block (for example, MB1) of the memory blocks MB1 and MB2. When a data signal is written to the upper memory cell MC), a magnetizing current is passed through the digit line DL (in this case, the leftmost digit line DL in FIG. 3) corresponding to the memory cell MC. In order to pass a magnetizing current through the digit line DL, the gate line GL (in this case, the leftmost gate line GL in FIG. 4) in the corresponding row of the non-selected memory block (in this case, MB2) is activated. To “H” level.

  As a result, the leftmost driver transistor 20 in FIG. 3 and the leftmost driver transistor 21 in FIG. 4 become conductive, and the leftmost auxiliary wiring AL in FIG. 4 is connected to the line of the ground voltage VSS. In this state, when signals DLE1n and DLE1 in FIG. 3 are both set to "L" level, P-channel MOS transistor P1 is turned on and N-channel MOS transistor Q1 is turned off. As a result, a magnetizing current flows from the power supply voltage VDD1 line to the ground voltage VSS line via the P-channel MOS transistor P1, the node N1, the leftmost digit line DL, and the driver transistors 20 and 21 in FIG.

  Next, a selection is made by flowing a write current in a direction corresponding to the logic of the write data signal to the bit line BL (in this case, the bit line BL at the upper end in FIG. 3) corresponding to the selected memory cell MC. A data signal can be written in the memory cell MC.

  6A is a diagram showing a layout of four memory cells MC and four N-channel MOS transistors 23 in the memory block MB1, and FIG. 6B is a VIB-VIB line in FIG. 6A. It is sectional drawing. 6A and 6B, two gate lines GL and two word lines WL are formed in parallel on the surface of the silicon substrate 31. Two gate lines GL and two word lines WL are alternately arranged one by one. Both the gate line GL and the word line WL extend in the Y direction.

  Each word line WL is formed in a ladder shape, and includes two wiring portions WLa and WLb each extending in the Y direction, and a plurality of wiring portions WLc each extending in the X direction. Each wiring portion WLc is arranged between two adjacent memory cell columns and connected between the two wiring portions WLa and WLb. A ring portion of the word line WL is formed by the two adjacent wiring portions WLc and the two wiring portions WLa and WLb on both sides thereof. A gate oxide film (not shown) is formed between each of the gate line GL and the word line WL and the surface of the silicon substrate 31.

  Impurity diffusion regions are formed on the surface of the silicon substrate 31 using the two gate lines GL and the two word lines WL as a mask. A rectangular region surrounded by two adjacent wiring parts WLc and two wiring parts WLa and WLb on both sides thereof serves as a common drain D for the access transistors 19a and 19b. A region between the wiring portion WLa of the word line WL and the gate line GL serves as a region serving as the source S of the access transistor 19a and the source S of the driver transistor 23, and the ground voltage VSS is connected via the corresponding source line SL. Connected to the line.

  A region between the wiring part WLb of the word line WL and the gate line GL serves as a region serving as the source S of the access transistor 19b and the drain D of the driver transistor 23. The memory block MB2 is connected via the corresponding auxiliary wiring AL. To the digit line DL.

  A digit line DL extending in the Y direction is formed above each gate line GL. A rectangular electrode EL is formed from above the drain D of the access transistors 19a and 19b of each memory cell MC to above the left digit line DL. The drains D of the access transistors 19a and 19b are connected to the upper electrode EL by a contact hole CH. In each region where the electrode EL and the digit line DL overlap each other, the magnetoresistive element 18 is formed on the electrode EL. The magnetoresistive element 18 is formed such that a magnetic field is generated in the hard axis direction of the magnetoresistive element 18 when a magnetizing current is passed through the digit line DL. A bit line BL extending in the X direction is formed on each of the two magnetoresistive elements 18 arranged in the X direction.

  When a magnetizing current is passed through the selected digit line DL, the magnetoresistive element 18 thereabove is put in a half-selected state. When a write current is passed through the selected bit line BL, a data signal is written to the magnetoresistive element 18 in the half-selected state below it. When the selected word line WL is set to the “H” level, the access transistors 19a and 19b become conductive, and the magnetoresistive element 18, the electrode EL, the contact hole CH, and the transistors 19a and 19b are connected from the bit line BL to which the read voltage is applied. A current having a value corresponding to the resistance value of the magnetoresistive element 18 flows through the source line SL.

  In the first embodiment, the sources S (or drains D) of the driver transistors 21 and 23 are shared with the sources S of the access transistors 19a and 19b. In the read operation, the source S of one access transistor 19a always receives the ground voltage VSS, and the source S of the other access transistor 19b receives the ground voltage VSS via the digit line DL or the like. Therefore, all of the access transistors 19a and 19b (the gates thereof) operate as transistors. In FIG. 6A, the driver transistor 23 corresponding to one memory cell MC functions as a transistor having a gate width WDR. Therefore, it is possible to eliminate almost all useless empty areas in the memory block MB. Therefore, the size of driver transistors 20-23 and access transistors 19a, 19b can be increased, and the yield and read performance can be improved.

  In the first embodiment, the DL driver 10 is composed of the transistor 20 and the plurality of transistors 21, but the transistor 20 may be omitted if a sufficient magnetizing current can flow only by the plurality of transistors 21. Similarly, the DL driver 14 may be configured by only a plurality of transistors 23 without the transistor 22. In this case, since the regions A1 and A2 in which the transistors 20 and 22 are disposed are not necessary, the layout area can be further reduced.

[Embodiment 2]
7 and 8 are diagrams showing configurations and layouts of the memory blocks MB1 and MB2 and DL drivers 10 and 14 of the MRAM according to the second embodiment of the present invention, which are compared with FIGS. 3 and 4. FIG. is there. 7 and 8, the memory block MB1 is vertically divided into two sub-blocks SB1U and SB1D, and the memory block MB2 is vertically divided into two sub-blocks SB2U and SB2D. Each of sub-blocks SB1U, SB1D, SB2U, and SB2D includes memory cells MC in 4 rows and 2 columns. Each memory cell MC includes a magnetoresistive element 18 and two access transistors 19a and 19b. Actually, each of the sub-blocks SB1U, SB1D, SB2U, and SB2D includes a large number of memory cells MC, but in order to simplify the drawing, the memory cells MC in 4 rows and 2 columns are shown.

  In each of memory blocks MB1 and MB2, digit line DL is provided corresponding to each row, bit line BL is provided corresponding to each column, and each digit line DL includes a plurality of magnetoresistive elements 18 in the corresponding row. It is arranged along. Three source lines SL are arranged on both sides and the center of four memory cell rows.

  Further, in the memory block MB1, two auxiliary wirings ALU and two auxiliary wirings ALD are further provided. The two auxiliary wirings ALU are respectively arranged between the first memory cell row and the second memory cell row of the memory block MB1 and between the third memory cell row and the fourth memory cell row. . Two auxiliary wirings ALD are arranged between the first memory cell row and the second memory cell row of sub-block SB1D, and between the third memory cell row and the fourth memory cell row, respectively. .

  Further, in the memory block MB2, two auxiliary wirings ALU and two auxiliary wirings ALD are further provided. The two auxiliary wirings ALD are arranged between the first memory cell row and the second memory cell row of the memory block MB2, and between the third memory cell row and the fourth memory cell row, respectively. . The two auxiliary wirings ALU are arranged between the first memory cell row and the second memory cell row of the sub-block SB1D, and between the third memory cell row and the fourth memory cell row, respectively. .

  One end of the odd-numbered digit line DL of the memory block MB1 is connected to the node N1, and the other end is connected to the auxiliary wiring ALU adjacent to the corresponding row of the memory block MB2. One end of the even-numbered digit line DL of the memory block MB1 is connected to the node N1, and the other end is connected to the auxiliary wiring ALD adjacent to the corresponding row of the memory block MB2.

  One end of the odd-numbered digit line DL of the memory block MB2 is connected to the node N2, and the other end is connected to the auxiliary wiring ALU adjacent to the corresponding row of the memory block MB1. One end of the even-numbered digit line DL of the memory block MB2 is connected to the node N2, and the other end is connected to the auxiliary wiring ALD adjacent to the corresponding row of the memory block MB1.

  In each of sub-blocks SB1U and SB2U, a word line WLU is provided corresponding to each row. In each of sub-blocks SB1D and SB2D, a word line WLD is provided corresponding to each row. Each word line WL (WLU or WLD) includes a plurality of ring portions. The plurality of ring portions are arranged corresponding to the plurality of memory cells MC in the corresponding row, respectively. Each ring portion of the word line WL forms a common gate of the two access transistors 19a and 19b of the corresponding memory cell MC.

  The leftmost source line SL is connected to the source of the access transistor 19b of each adjacent memory cell MC. The center source line SL is connected to the sources of the access transistors 19a and 19b of each adjacent memory cell MC. The rightmost source line SL is connected to the source of the access transistor 19a of each adjacent memory cell MC. Each source line SL receives ground voltage VSS.

  In each of the sub-blocks SB1U and SB2U, each auxiliary wiring ALU is connected to the sources of the access transistors 19a and 19b of each adjacent memory cell MC. In each of the sub blocks SB1D and SB2D, each auxiliary wiring ALD is connected to the sources of the access transistors 19a and 19b of each adjacent memory cell MC.

  That is, the gates of the access transistors 19a and 19b of each memory cell MC are connected to the corresponding word line WL, their drains are both connected to the corresponding bit line BL via the magnetoresistive element 18, and their sources are adjacent. Connected to the source line SL or the auxiliary wiring AL.

  The DL driver 10 includes a P-channel MOS transistor P1, an N-channel MOS transistor Q1, a driver transistor (N-channel MOS transistor) 20U provided corresponding to each auxiliary wiring ALU, and a driver provided corresponding to each auxiliary wiring ALD. It includes a transistor (N-channel MOS transistor) 20D and access transistors 19a and 19b of memory block MB2. That is, the access transistors 19a and 19b of the memory block MB2 also serve as driver transistors of the DL driver 10.

  P-channel MOS transistor P1 is connected between a line of power supply voltage VDD1 and node N1, and has its gate receiving signal DLE1n. N-channel MOS transistor Q1 is connected between node N1 and the line of ground voltage VSS, and has its gate receiving signal DLE1.

  Driver transistors 20U and 20D are arranged in area A2 on the memory block MB2 side between memory blocks MB1 and MB2. The drain of driver transistor 20U is connected to corresponding auxiliary wiring ALU of memory block MB2, and its source receives ground voltage VSS. The drain of the driver transistor 20D is connected to the corresponding auxiliary wiring ALD of the memory block MB2, and the source thereof receives the ground voltage VSS.

  When signals DLE1n and DLE1 are both set to "L" level, P channel MOS transistor P1 is turned on and N channel MOS transistor Q1 is turned off, and power supply voltage VDD1 is applied to node N1. In addition, the driver transistor 20 (20U or 20D) connected to the auxiliary wiring AL (ALU or ALD) corresponding to the selected digit line DL of the memory block MB1 is turned on.

  Further, the word line WL (WLU or WLD) of the memory cell row connected to the auxiliary line AL and corresponding to the selected digit line DL is set to the “H” level of the selection level and corresponds to the word line WL. The access transistors 19a and 19b of each memory cell MC to be conducted become conductive, and the auxiliary wiring AL is connected to the source line SL via the access transistors 19a and 19b. As a result, the magnetizing current flows from the line of the power supply voltage VDD1 to the line of the ground voltage VSS via the selected digit line DL and the transistors 20 (20U or 20D), 19a, 19b of the memory block MB1.

  The DL driver 14 includes a P-channel MOS transistor P2, an N-channel MOS transistor Q2, a driver transistor (N-channel MOS transistor) 22U provided corresponding to each auxiliary wiring ALU, and a driver provided corresponding to each auxiliary wiring ALD. It includes a transistor (N channel MOS transistor) 22D and access transistors 19a and 19b of memory block MB1. That is, the access transistors 19a and 19b of the memory block MB1 also serve as driver transistors of the DL driver 14.

  P-channel MOS transistor P2 is connected between a line of power supply voltage VDD1 and node N2, and has its gate receiving signal DLE2n. N channel MOS transistor Q2 is connected between node N2 and the line of ground voltage VSS, and has its gate receiving signal DLE2.

  Driver transistors 22U and 22D are arranged in area A1 on the memory block MB1 side between memory blocks MB1 and MB2. The drain of the driver transistor 22U is connected to the corresponding auxiliary wiring ALU of the memory block MB1, and the source thereof receives the ground voltage VSS. The drain of the driver transistor 22D is connected to the corresponding auxiliary wiring ALD of the memory block MB1, and the source thereof receives the ground voltage VSS.

  When signals DLE2n and DLE2 are both set to "L" level, P channel MOS transistor P2 is turned on and N channel MOS transistor Q2 is turned off, and power supply voltage VDD1 is applied to node N2. In addition, the driver transistor 22 (22U or 22D) connected to the auxiliary wiring AL (ALU or ALD) corresponding to the selected digit line DL of the memory block MB2 is turned on.

  Further, the word line WL (WLU or WLD) of the memory cell row adjacent to the auxiliary line AL and corresponding to the selected digit line DL is set to the “H” level of the selection level and corresponds to the word line WL. The access transistors 19a and 19b of each memory cell MC to be conducted become conductive, and the auxiliary wiring AL is connected to the source line SL via the access transistors 19a and 19b. As a result, a magnetizing current flows from the line of the power supply voltage VDD1 to the line of the ground voltage VSS via the selected digit line DL and the transistors 22 (22U or 22D), 19a, 19b of the memory block MB1.

  Next, the operation of this MRAM will be described. In read operation and standby operation, signals DLE1n, DLE1, DLE2n, and DLE2 in FIGS. 7 and 8 are all set to "H" level. As a result, P channel MOS transistors P1, P2 are rendered non-conductive, N channel MOS transistors Q1, Q2 are rendered conductive, and all digit lines DL and all auxiliary lines AL are at ground voltage VSS. Further, the source line SL is always at the ground voltage VSS. Therefore, the sources of the access transistors 19a and 19b of each memory cell MC are set to the ground voltage VSS.

  In the read operation, one selected word line WL among the plurality of word lines WL belonging to one selected sub-block SB among the sub-blocks SB1U, SB1D, SB2U, and SB2D is selected at “ Launched to “H” level. Thereby, the access transistors 19a and 19b of each memory cell MC corresponding to the selected word line WL are turned on. In addition, when a predetermined voltage is applied to one selected bit line BL among the plurality of bit lines BL belonging to the selected sub-block SB, the current flowing in the magnetoresistive element 18 of the selected memory cell MC A value is detected. The current value and the reference current value are compared with each other, and the logic of the data stored in the memory cell MC is determined based on the comparison result.

  For example, when the value of the current flowing through memory cell MC is higher than the reference current value, it is determined that the storage data of memory cell MC is at “H” level (1). Conversely, when the value of the current flowing through the memory cell MC is lower than the reference current value, it is determined that the storage data of the memory cell MC is at the “L” level (0).

  During the write operation, the selected memory cell MC (for example, the topmost left end in FIG. 7) of the plurality of memory cells MC belonging to the selected sub block of the sub blocks SB1U, SB1D, SB2U, and SB2D. When a data signal is written into the memory cell MC), a magnetizing current is passed through the digit line DL (in this case, the leftmost digit line DL in FIG. 7) corresponding to the memory cell MC.

  In this case, the driver transistor 20U corresponding to the digit line DL is turned on, and the word line WLU corresponding to the digit line DL (the leftmost word line WLU of the sub-block SB2U of the unselected memory block MB2) is set. The selected level is set to “H” level, and the access transistors 19a and 19b of each memory cell MC connected to the word line WLU are made conductive. At this time, in addition to the leftmost word line WLU of the sub-block SB2U, the right word line WLU may also be set to the “H” level to increase the current driving capability. As a result, the auxiliary wiring ALU at the left end in FIG. 8 is connected to the line of the ground voltage VSS.

  In this state, when signals DLE1n and DLE1 in FIG. 3 are both set to "L" level, P-channel MOS transistor P1 is turned on and N-channel MOS transistor Q1 is turned off. As a result, a magnetizing current flows from the power supply voltage VDD1 line to the ground voltage VSS line via the P-channel MOS transistor P1, the node N1, the leftmost digit line DL in FIG. 7, and the leftmost auxiliary line ALU in FIG.

  Next, a selection is made by flowing a write current in a direction according to the logic of the write data signal to the bit line BL (in this case, the bit line BL at the upper end of FIG. 7) corresponding to the selected memory cell MC. A data signal can be written in the memory cell MC.

  FIG. 9A is a diagram showing a layout of four memory cells MC in the sub-block SB1U, and FIG. 9B is a cross-sectional view taken along the line IXB-IXB in FIG. 9A. 9A and 9B, two word lines WLU are formed on the surface of the silicon substrate 31 in parallel. Each word line WLU extends in the Y direction.

  Each word line WLU is formed in a ladder shape and includes two wiring parts WLa and WLb each extending in the Y direction and a plurality of wiring parts WLc each extending in the X direction. Each wiring portion WLc is arranged between two adjacent memory cell columns and connected between the two wiring portions WLa and WLb. A ring portion of the word line WLU is formed by the two adjacent wiring portions WLc and the two wiring portions WLa and WLb on both sides thereof. A gate oxide film (not shown) is formed between the word line WLU and the surface of the silicon substrate 31.

  An impurity diffusion region is formed on the surface of the silicon substrate 31 using the two word lines WLU as a mask. In each word line WLU, a rectangular region surrounded by two adjacent wiring portions WLc and two wiring portions WLa and WLb on both sides thereof is a common drain D of the access transistors 19a and 19b of one memory cell MC. It becomes.

  An area between the wiring part WLa of one word line WLU and the wiring part WLb of the other word line WLU of two adjacent word lines WLU is a memory of one of the two adjacent memory cells MC. This region serves as both the source S of the access transistor 19a of the cell MC and the source S of the access transistor 19b of the other memory cell MC, and is connected to the ground voltage VSS line via the corresponding source line SL.

  The area on the left side of the leftmost word line WLU becomes the source S of the access transistor 19b and is connected to the digit line DL of the memory block MB2 via the corresponding auxiliary wiring ALU. The area on the right side of the rightmost word line WLU becomes the source S of the access transistor 19a, and is connected to the digit line DL of the memory block MB2 via a corresponding auxiliary wiring (not shown).

  A digit line DL extending in the Y direction is formed above a region between each adjacent two word lines WL. A square electrode EL is formed from above the drain D of each access transistor 19a, 19b to above the left digit line DL. The drain D of each access transistor 19a, 19b and the electrode EL thereabove are connected by a contact hole CH. In each region where the electrode EL and the digit line DL overlap each other, the magnetoresistive element 18 is formed on the electrode EL. The magnetoresistive element 18 is formed such that a magnetic field is generated in the hard axis direction of the magnetoresistive element 18 when a magnetizing current is passed through the digit line DL. A bit line BL extending in the X direction is formed on each of the two magnetoresistive elements 18 arranged in the X direction.

  When a magnetizing current is passed through the selected digit line DL, the magnetoresistive element 18 thereabove is put in a half-selected state. When a write current is passed through the selected bit line BL, a data signal is written to the magnetoresistive element 18 in the half-selected state below it. When the selected word line WL is set to the “H” level, the access transistors 19a and 19b become conductive, and the magnetoresistive element 18, the electrode EL, the contact hole CH, and the transistors 19a and 19b are connected from the bit line BL to which the read voltage is applied. A current having a value corresponding to the resistance value of the magnetoresistive element 18 flows through the source line SL.

  In the second embodiment, the same effect as in the first embodiment can be obtained, and the access area 19a, 19b of the memory cell MC can also serve as the driver transistor of the DL driver 10, 14, thereby reducing the layout area. .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 memory array, 2 row decoder, 3 column decoder, 4 write circuit, 5 read circuit, 10, 14 DL driver, 11, 12, 15, 16 BL driver, 13, 17 WL driver, 18 magnetoresistive element, 19a, 19b access transistor, 20-23 driver transistor, 25, 28 inverter, P, 26, 29 P channel MOS transistor, Q, 27, 30 N channel MOS transistor, 31 silicon substrate, A1, A2 region, AL auxiliary wiring, BL bit Line, CH contact hole, D drain, DL digit line, EL electrode, GL gate line, MB memory block, MC memory cell, S source, SB sub-block, SL source line, WL word line.

Claims (1)

A semiconductor memory device formed on the surface of a semiconductor substrate,
A plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, a plurality of digit lines provided corresponding to the plurality of rows, respectively, A memory array including a plurality of bit lines provided corresponding to a plurality of columns and a plurality of auxiliary wirings provided corresponding to the plurality of digit lines respectively.
One end of each digit line is connected to the corresponding auxiliary wiring,
Each memory cell
A magnetoresistive element whose first electrode is connected to a corresponding bit line and stores a data signal by a change in level of a resistance value;
Their drains are both connected to the second electrode of the magnetoresistive element, their sources are connected to the reference voltage line and the corresponding auxiliary wiring, respectively, and their gates are both connected to the corresponding word line. 1 and a second access transistor,
And a write circuit for writing a data signal to a selected memory cell of the plurality of memory cells.
The writing circuit includes:
Applying a predetermined voltage between the other end of the selected digit line of the plurality of digit lines and the auxiliary wiring corresponding to the selected digit line to flow a magnetizing current, and the selected digit line A digit line driver that makes the magnetoresistive element of each memory cell corresponding to the half-selected state,
And a bit line driver that causes a write current in a direction according to the data signal to flow through a selected bit line of the plurality of bit lines.

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