JP5316608B2 - Nonvolatile memory cell and nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory cell and a nonvolatile memory which can operate with a super low voltage and low power consumption without needing an internal booster circuit. <P>SOLUTION: The nonvolatile memory cell is configured by serially connecting a resistance change type element R1 and a switch SW for selection comprising an N channel field effect transistor TN and a P channel field effect transistor TP connected in parallel, between a bit line and a source line. The nonvolatile memory has a memory cell array in which such nonvolatile memory cells are arranged in a matrix. Since the switch for selection comprises the N channel field effect transistor TN and the P channel field effect transistor TP in this way, the problem of a threshold drop does not occur without being affected by voltage applied between the bit line and the source line. It is possible to realize a nonvolatile memory cell and a nonvolatile memory which can operate with a super low voltage and low power consumption without needing an internal booster circuit. <P>COPYRIGHT: (C)2013,JPO&amp;INPIT

Description

  The present invention relates to a nonvolatile memory cell using a resistance variable element and a nonvolatile memory including the nonvolatile memory cell.

  In recent years, a resistance change type memory for storing data using a resistance change type element has attracted attention as a next-generation non-volatile memory in place of a flash memory or a DRAM that has become limited in miniaturization. Examples of the resistance change element include MRAM (Magnetoretic Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistance Random Access Memory). The thing that is. A memory using such a resistance variable element does not require a complicated process like a flash memory, is compatible with a standard logic process, is suitable for miniaturization, and operates at a low voltage. The future is promising. An element configuration, characteristics, and array configuration of a memory using this type of variable resistance element are disclosed in Patent Document 1 or Non-Patent Document 1, for example.

  FIGS. 18A and 18B are diagrams showing the configuration and operation of a memory cell using a typical MTJ (Magnetic Tunnel Junction) element as a resistance variable element. As shown in FIGS. 18A and 18B, the MTJ element includes a pinned layer having a constant magnetic direction, a tunnel barrier film, and a free layer having a changed magnetic direction. As shown in FIG. 18A, when a current in the direction from the free layer to the pinned layer is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element becomes low resistance, and data “0” is stored. It becomes a state. Conversely, as shown in FIG. 18B, when a current in the direction from the pinned layer toward the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored. When a memory cell is configured with such an MTJ element, an N-channel transistor Ts is connected in series with the MTJ element as a switch for selecting the MTJ element, as illustrated in FIGS. 18 (a) and 18 (b). Is done. The configuration of such a nonvolatile memory cell is disclosed in Patent Document 1, for example.

  FIG. 19 is a diagram illustrating a cross-sectional structure of a conventional memory cell array configured by nonvolatile memory cells as shown in FIGS. 18A and 18B. In the example shown in FIG. 19, the N-channel transistor Ts for selection shown in FIGS. 18A and 18B is formed on the semiconductor substrate. A selection voltage WL is applied to the gates of the two N-channel transistors Ts constituting one memory cell. The sources of these N-channel transistors Ts are connected to the source line SL of the second metal layer 2M through the through holes and the first metal layer 1M. The drain shared by the two N-channel transistors Ts is connected to the pin layer of the MTJ element through a through hole, and the free layer of the MTJ element is connected to the bit line BL formed by the second metal layer 2M through the through hole. It is connected.

  FIG. 20 is a diagram showing a circuit configuration of a conventional memory cell array, and FIG. 21 is a diagram showing a layout example of the memory cell array. In FIGS. 20 and 21, a region surrounded by an alternate long and short dash line indicates one nonvolatile memory cell. The memory cell array is an array of these non-volatile memory cells. As shown in FIG. 21, in the memory cell array, row selection lines WL00, WL01, WL10, WL11, WL20, and WL21 made of a polysilicon layer are wired in the horizontal direction. In the memory cell array, a plurality of rectangular N-type impurity regions extending in the vertical direction are formed in parallel in the horizontal direction. The intersection of the row selection line which is a polysilicon layer and these N-type impurity layers becomes the gate of the N-channel transistor shown in FIGS. 18 and 19, and the N-type impurity layers on both sides of this gate are the N-channel transistor. Source or drain.

  In the memory cell array, source lines SL0, SL1, SL2, and SL3 formed by the second metal layer M2 extending in the vertical direction and bit lines BL0, BL1, BL2, and BL3 formed by the second metal layer M2 are alternately arranged in the horizontal direction. ing. In the illustrated example, in the nonvolatile memory cell surrounded by the alternate long and short dash line, the source line SL1 is connected to the source of the N-channel transistor whose gate is the row selection line WL10 and the source of the N-channel transistor whose gate is the row selection line WL11. It is connected. An MTJ element is interposed between the common drain of the N-channel transistor whose gate is the row selection line WL10 and the N-channel transistor whose gate is the row selection line WL11, and the bit line BL1 formed by the second metal layer M2. ing.

  FIG. 22 is a diagram showing operating conditions of the nonvolatile memory cell described above. When “0” is written in the MTJ element of a desired nonvolatile memory cell, a selection voltage WL of 1.2 V is applied to the gate of the N-channel transistor of the nonvolatile memory cell, 1.2 V is applied to the bit line BL, and the source line Apply 0V to SL. As a result, a current of about 49 μA in the direction from the free layer to the pinned layer flows through the MTJ element of the nonvolatile memory cell, the MTJ element becomes low resistance, and “0” is stored. On the other hand, when “1” is written to the MTJ element of a desired nonvolatile memory cell, a selection voltage WL of 1.2 V is applied to the gate of the N-channel transistor of the nonvolatile memory cell, 0 V is applied to the bit line BL, and the source line Apply 1.2V to SL. As a result, a current of about 49 μA in the direction from the pinned layer to the free layer flows through the MTJ element of the nonvolatile memory cell, the MTJ element becomes high resistance, and “1” is stored.

  When data is read from a desired nonvolatile memory cell, a selection voltage WL of 1.2 V is applied to the gate of the N-channel transistor of the nonvolatile memory cell, 0.15 V is applied to the bit line BL, and 0 V is applied to the source line SL. give. Then, a current flowing from the bit line BL to the MTJ element of the nonvolatile memory cell is detected. When the MTJ element stores “0” and has a low resistance, a current of about 15 μA flows through the MTJ element. On the other hand, when the MTJ element stores “1” and has a high resistance, a current of about 10 μA flows through the MTJ element. Therefore, it is possible to determine whether the MTJ element stores “0” or “1” by detecting the current flowing into the MTJ element and comparing it with a threshold value. Note that the configuration of such a memory cell array and the operating conditions of the nonvolatile memory cells constituting the memory cell array are disclosed in Non-Patent Document 2, for example.

JP 2009-187631 A

ISSCC Digest of Technical Papers, pp. 258, Feb. 2010. Non-Patent Literature IEICE IEICE Technical Report ICD Technical Report ICD2010-7 p35-p40

  By the way, in the conventional nonvolatile memory cell described above, since the voltage between the bit line and the source line is applied to the resistance variable element via the N channel transistor, a so-called threshold drop occurs in the N channel transistor, and the resistance change The voltage applied to the type element decreases from the voltage between the bit line and the source line by the threshold value of the N-channel transistor. Therefore, although the variable resistance element itself can be written at 0.6 V, a voltage of 1.2 V is required for data writing as shown in FIG. 22, and therefore, the power supply line pressure of the nonvolatile memory is reduced. It was necessary to make it 1.2V. Further, if the gate voltage of the N-channel transistor is generated using the booster circuit, it is possible to take measures against the threshold drop. However, the provision of the booster circuit causes a problem that the power consumption of the nonvolatile memory increases.

  The present invention has been made in view of the circumstances described above, and it is an object of the present invention to provide a nonvolatile memory cell and a nonvolatile memory that can operate with an ultra-low voltage and low power consumption without requiring an internal booster circuit. And

  According to the present invention, a variable resistance element and a selection switch composed of an N-channel field effect transistor and a P-channel field effect transistor connected in parallel are connected in series between a bit line and a source line. A memory cell is provided.

  According to this invention, since the selection switch is configured by the N-channel field effect transistor and the P-channel field effect transistor connected in parallel, the threshold value can be used regardless of the polarity of the voltage applied between the bit line and the source line. The problem of dropping does not occur. Therefore, data can be written to the resistance variable element via the selection switch with a low power supply voltage.

  The present invention also provides various nonvolatile memories having a memory cell array in which the nonvolatile memory cells are arranged in a matrix. Even in these nonvolatile memories, the selection switch of the nonvolatile memory cells constituting the memory cell array is composed of an N-channel field effect transistor and a P-channel field effect transistor connected in parallel. do not do. Therefore, it is possible to realize a nonvolatile memory that does not require an internal booster circuit and can operate with an ultra-low voltage and low power consumption.

1 is a circuit diagram showing a configuration of a nonvolatile memory cell according to a first embodiment of the present invention. FIG. It is a figure which shows the operating condition of the embodiment. It is a circuit diagram which shows the structure of the non-volatile memory cell which is 2nd Embodiment of this invention. It is a figure which shows the operating condition of the embodiment. It is a circuit diagram which shows the structure of the non-volatile memory which is 3rd Embodiment of this invention. 2 is a diagram showing a layout example of a memory cell array in the same embodiment. FIG. It is a circuit diagram which shows the structure of the non-volatile memory which is 4th Embodiment of this invention. It is a figure which shows the operating condition of the embodiment. FIG. 3 is a circuit diagram showing a configuration example of a row selection circuit in the same embodiment. 2 is a diagram showing a layout example of a memory cell array in the same embodiment. FIG. It is a circuit diagram which shows the structure of the non-volatile memory which is 5th Embodiment of this invention. It is a figure which shows the operating condition of the embodiment. FIG. 3 is a circuit diagram showing a configuration example of a row selection circuit in the same embodiment. It is a circuit diagram which shows the structure of the non-volatile memory which is 6th Embodiment of this invention. 4 is a diagram illustrating a connection relationship between a plurality of source decoders and a plurality of source lines in the embodiment. FIG. 2 is a diagram showing a layout example of a memory cell array in the same embodiment. FIG. It is a figure which shows the rough layout of the wiring which connects the element which comprises each non-volatile memory in the memory cell array. It is a figure which shows the structure and operation | movement of an MTJ element. It is a figure which illustrates the cross-sectional structure of the non-volatile memory cell using an MTJ element. It is a figure which illustrates the circuit structure of the memory cell array using the non-volatile memory cell. It is a top view which shows the layout of the memory cell array. It is a figure which shows the operating condition of the non-volatile memory cell.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the transistor refers to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field-effect transistor having a metal-oxide film-semiconductor structure).

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a nonvolatile memory cell according to the first embodiment of the present invention. As shown in FIG. 1, the nonvolatile memory cell according to the present embodiment includes a resistance change element R1 and a CMOS switch SW composed of an N-channel transistor TN and a P-channel transistor TP connected in parallel and a bit line connection end and a source. The line connection ends are connected in series. More specifically, in the present embodiment, the resistance change element R1 is an MTJ element, the free layer is connected to the bit line BL, the pinned layer is connected to one end of the CMOS switch SW, and the CMOS switch SW The other end is connected to the source line SL. In the CMOS switch SW, the selection voltage WL is applied to the gate of the N-channel transistor TN, and the inverted selection voltage WLB is applied to the gate of the P-channel transistor TP. The CMOS switch SW functions as a selection switch that selects the resistance variable element R1 at the time of data reading and data writing.

  FIG. 2 is a diagram showing operating conditions of the nonvolatile memory cell according to the present embodiment. First, data writing to the resistance variable element R1 will be described. When “0” is written to the resistance variable element R1, the bit line BL is set to 0.6V, the source line SL is set to 0V, the selection voltage WL is set to 0.6V, and the inversion selection voltage WLB is set to 0V. In this state, a voltage of about 0.6 V is applied to both ends of the resistance variable element R1, and a current of about 49 μA flows from the bit line BL to the source line SL. As a result, the resistance variable element R1 has a low resistance and stores data “0”. When “1” is written to the resistance variable element R1, the bit line BL is set to 0V, the source line SL is set to 0.6V, the selection voltage WL is set to 0.6V, and the inversion selection voltage WLB is set to 0V. As a result, a current flows from the source line SL to the bit line BL. At this time, since a voltage drop corresponding to the threshold value of the transistor (so-called threshold drop) does not occur in the CMOS switch SW, a voltage of about 0.6 V is applied across the resistance variable element R1, and a current of about 49 μA flows. As a result, the resistance variable element R1 changes to a high resistance and stores data “1”.

  Next, data reading from the resistance variable element R1 will be described. In data reading, the bit line BL is set to 0.15V, the source line SL is set to 0V, the selection voltage WL is set to 0.6V, and the inverted selection voltage WLB is set to 0V. Here, when the resistance variable element R1 stores data “0” and has a low resistance, a current of 15 μA flows from the bit line BL to the source line SL. On the other hand, when the resistance variable element R1 stores data “1” and has a high resistance, a current of 10 μA flows from the bit line BL to the source line SL. Therefore, a threshold value (for example, 12.5 μA) is generated between the current 15 μA flowing when reading data “0” and the current 10 μA flowing when reading data “1”, and the bit line BL is switched to the source line SL when reading data. By comparing the current flowing in the direction with this threshold value, it is possible to determine whether the data stored in the resistance variable element R1 is “0” or “1”.

  As described above, according to the present embodiment, since the selection switch for selecting the resistance variable element R1 is the CMOS switch SW, when data “0” is written at the time of data writing, data “1” is written. In both cases, the threshold value drop does not occur in the selection switch, and accurate data writing to the resistance variable element R1 can be performed.

Second Embodiment
FIG. 3 is a circuit diagram showing a configuration of a nonvolatile memory cell according to the second embodiment of the present invention. In the present embodiment, the positional relationship between the CMOS switch SW and the resistance variable element R1 is switched with respect to the first embodiment, the resistance variable element R1 is on the source line SL side, and the CMOS switch SW is on the bit line BL. On the side.

  FIG. 4 is a view showing operating conditions of the nonvolatile memory cell according to the present embodiment. The data write operation for the resistance variable element R1 is the same as that in the first embodiment. Therefore, data reading will be described. In this embodiment, at the time of data reading, the bit line BL is set to 0.6 V, which is the same as the power supply voltage, the selection voltage WL is set to 0.3 V, and the inverted selection voltage WLB is set to 0.6 V. As a result, the P channel transistor TP is turned OFF. In the N-channel transistor TN, a threshold drop occurs, and the potential at the connection point between the N-channel transistor TN and the resistance variable element R1 is 0.15V. As a result, as in the first embodiment, the voltage applied to the resistance variable element R1 during data reading is 0.15V.

  In the first embodiment, a constant voltage circuit that generates a voltage of 0.15 V to be applied to the bit line BL at the time of data reading is required. However, in the present embodiment, the constant voltage circuit of 0.15 V is not necessary. There is an advantage that control is easy.

<Third Embodiment>
FIG. 5 is a circuit diagram showing a configuration of a nonvolatile memory according to the third embodiment of the present invention. In FIG. 5, the memory cell array 100 is configured by arranging memory cells Mkj in a matrix of m + 1 rows and n + 1 columns. In the illustrated example, each memory cell Mkj is the nonvolatile memory cell of the first embodiment (FIG. 1), but may be replaced with the nonvolatile memory cell of the second embodiment (FIG. 3). A source line SLj and a bit line BLj are respectively wired on the left and right sides of m + 1 memory cells Mkj (k = 0 to m) forming one column. Here, between the source line SLj and the bit line BLj, the CMOS switch SW and the resistance variable element R1 of the memory cell Mkj (k = 0 to m) in the j-th column are respectively inserted. A row selection line WLk and an inversion row selection line WLkB are wired on the upper and lower sides of n + 1 memory cells Mkj (j = 0 to n) forming one row. Here, the row selection line WLk is a wiring that supplies the selection voltage WL to the N-channel transistor TN of the memory cell Mkj (k = 0 to m) in the k-th row, and the inversion row selection line WLkB is the k-th row. This is a wiring for supplying the inversion selection voltage WLB to the P-channel transistor TP of the memory cell Mkj (k = 0 to m) (see FIG. 1 above).

  The row decoder 200 is a circuit that selects one row of memory cells Mkj (j = 0 to n) in the memory cell array 100 according to a row address at the time of data writing or data reading. More specifically, when the row address indicates the k′th row, the row decoder 200 sets the selection voltage WL for the row selection line WLk ′ corresponding to the k′th row to 0.6 V and corresponds to the k′th row. The inverted selection voltage WLB for the inverted row selection line WLk′B is set to 0V. Further, the selection voltage WL for the row selection line WLk (k ≠ k ′) corresponding to each row other than the k′th row is set to 0V, and the inverted row selection line WLkB (k ≠ k ′) corresponding to each row other than the k′th row. ) Is set to 0.6V. As a result, each resistance variable element R1 of the memory cell Mk′j (j = 0 to n) in the k′th row is connected to the source line SLj (j = 0 to n), and the memory cell Mkj (k) in the other row. ≠ k ′, j = 0 to n), each variable resistance element R1 is disconnected from the source line SLj (j = 0 to n).

  The data line DL and the inverted data line DLB are signal lines for transmitting data to be written to the memory cell array 100 or data read from the memory cell array 100. A CMOS switch COLBj (j = 0 to n) for column selection is interposed between the data line DL and each of the bit lines BLj (j = 0 to n). Also, CMOS switches COLSj (j = 0 to n) for column selection are respectively inserted between the inverted data lines DLB and the source lines SLj (j = 0 to n). These CMOS switches COLBj (j = 0 to n) and CMOS switches COLSj (j = 0 to n) constitute a column selection unit 400.

  The column decoder 300 is a circuit that selects one column of memory cells Mkj (k = 0 to m) in the memory cell array 100 according to a column address at the time of data writing or data reading. More specifically, when the column address indicates the j'th column, the column decoder 300 turns on only the CMOS switches COLBj 'and COLSj', and sets the other CMOS switches COLBj (j ≠ j ') and COLSj (j ≠ j ′) is turned OFF. As a result, only the bit line BLj 'and the source line SLj' in the j'th column are connected to the data line DL and the inverted data line DLB via the CMOS switches COLBj 'and COLSj', respectively. As a result, it becomes possible to access the memory cell Mkj 'in the j'th column via the data line DL and the inverted data line DLB.

  The write control circuit 800 is a circuit that delivers the write data Din to the write driver 500 when the write data Din is given together with the write enable signal WE. Write driver 500 has a three-state buffer for driving data line DL and a three-state buffer for driving inverted data line DLB.

  At the time of data writing, the write driver 500 sets two 3-state buffers that drive the data line DL and the inverted data line DLB to an output enable state. When the write data Din is “0”, the write driver 500 outputs 0.6 V to the data line DL and 0 V to the inverted data line DLB. On the other hand, at the time of data writing, the row address and column address of the memory cell Mkj to be accessed are given to the row decoder 200 and the column decoder 300, and 1 belonging to the column specified by the row and column address specified by the row address. Memory cells Mkj are connected to data line DL and inverted data line DLB. When 0.6 V is output to the data line DL and 0 V is output to the inverted data line DLB, a current flows from the bit line BLj to the source line SLj through the memory cell Mkj. As a result, the resistance variable element R1 of the memory cell Mkj has a low resistance and stores data “0”.

  When the write data Din is “1”, the write driver 500 outputs 0V to the data line DL and 0.6V to the inverted data line DLB. As a result, a current flows from the source line SLj to the bit line BLj through the memory cell Mkj. As a result, the resistance variable element R1 of the memory cell Mkj becomes high resistance, and the data “1” is stored.

  A sense amplifier 600 is connected to the data line DL. Further, an output circuit 700 is provided after the sense amplifier 600. These sense amplifier 600 and output circuit 700 are circuits for reading data.

  In addition to the sense amplifier 600 and the output circuit 700, the above-described write driver 500 also performs an operation for reading data. That is, at the time of data reading, the write driver 500 sets the 3-state buffer that drives the data line DL to the output disabled state (floating state), and sets the 3-state buffer that drives the inverted data line DLB to the output enabled state. 0V is output from the 3-state buffer to the inverted data line DLB.

  The operation of row selection and column selection at the time of data reading is the same as that at the time of data writing. That is, the row address and column address of the memory cell Mkj to be accessed are given to the row decoder 200 and the column decoder 300, and one memory cell Mkj belonging to the column specified by the row and column address specified by the row address. Are connected to the data line DL and the inverted data line DLB. At that time, the sense amplifier 600 applies a voltage of 0.15 V to the data line DL, and detects and amplifies a current flowing from the sense amplifier 600 into the data line DL.

  Here, when the memory cell Mkj to be accessed stores data “0”, a current of 15 μA (see FIG. 2) is a resistance change type of the sense amplifier 600 → the data line DL → the bit line BLj → the memory cell Mkj. It flows following the path of element R 1 → source line SLj → inverted data line DLB → write driver 500.

  On the other hand, when the memory cell Mkj to be accessed stores data “1”, a current of 10 μA (see FIG. 2) flows along the same path. Therefore, the sense amplifier 600 compares the current I flowing into the data line DL with an intermediate threshold value Ith between 10 μA and 15 μA, and outputs data “0” if I> Ith, and data “1” if I <Ith. . The output circuit 700 outputs the output data of the sense amplifier 600 to the outside.

  6A to 6C are diagrams showing a layout example of the memory cell array 100 in the present embodiment. 6A shows the layout of various wirings and elements without omitting the second metal layer M2, and FIG. 6B shows the layout of various wirings and elements without the second metal layer M2. It is shown. Further, in FIG. 6C, the N-channel transistor TN, the P-channel transistor TP, and the variable resistance element R1 that form one nonvolatile memory cell surrounded by the one-dot chain line in FIG. A rough layout of each polysilicon layer forming the bit line BL1 by the second metal layer M2 connected to the conductive memory cell, the source line SL1 by the second metal layer M2, the row selection line WL1 and the inversion row selection line WL1B is shown. ing.

  The P-channel transistor TP of the nonvolatile memory cell surrounded by the alternate long and short dash line is formed in the NWELL surrounded by the broken line. The source of the P-channel transistor TP is connected to the source line SL1 by the second metal layer M2 wired in the vertical direction in the figure via the P-channel transistor contact CN1. The drain of the P-channel transistor TP is connected to the drain of the N-channel transistor TN by the first metal layer M1. The source of the N-channel transistor TN is connected to the source line SL1 of the second metal layer M2 via the N-channel transistor contact CN2. A resistance change occurs between the first metal layer M1 connecting the drain of the P-channel transistor TP and the drain of the N-channel transistor TN and the bit line BL1 formed by the second metal layer M2 wired in the vertical direction in the drawing. A mold element R1 is inserted.

  The above is the details of the present embodiment. According to the present embodiment, since the non-volatile memory cell having the CMOS switch as the selection switch is used as the memory cell Mkj constituting the memory cell array 100, the selection switch does not drop in threshold when data is written. Data can be written to the resistance variable element R1 of each memory cell with a voltage.

<Fourth embodiment>
FIG. 7 is a circuit diagram showing a configuration of a nonvolatile memory according to the fourth embodiment of the present invention. Similar to the third embodiment, the memory cell array 110 is configured by arranging memory cells Mkj in a matrix of m + 1 rows and n + 1 columns. In the third embodiment, the source line SLj corresponding to each column j of the memory cells Mkj is wired in the direction along the column. On the other hand, in the present embodiment, the source lines are wired in the direction along the rows. Further, in the present embodiment, source lines SL00, SL01, SL12,..., SL (m−1) m, SLmm are wired so as to sandwich each row of the memory cell array 110. In this embodiment, the two source lines sandwiching each row serve to supply the source voltage SL to the CMOS switch SW in the row. Specifically, the source lines SL00 and SL01 serve to supply the source voltage SL to the CMOS switch SW of the memory cell M0j (j = 0 to n) in the 0th row. Next, the source lines SL01 and SL12 serve to supply the source voltage SL to the CMOS switch SW of the memory cell M1j (j = 0 to n) in the first row. Next, the source lines SL12 and SL23 serve to supply the source voltage SL to the CMOS switch SW of the memory cell M2j (j = 0 to n) in the second row. Hereinafter, the same applies, and the source lines SLpq (q = p + 1) and SLqr (r = q + 1) serve to supply the source voltage SL to the CMOS switch SW of the memory cell Mqj (j = 0 to n) in the q-th row. It is.

  Connection relationship between row selection line WLk and inverted row selection line WLkB (k = 0 to m) and each memory cell Mkj (k = 0 to m, j = 0 to n), bit line BLj (j = 0 to n) And the memory cells Mkj (k = 0 to m, j = 0 to n) are the same as those in the third embodiment.

  Unlike the third embodiment, the column selection unit 410 includes only CMOS switches COLBj (j = 0 to n). When the column address indicates the j′th column, the column decoder 300 turns on the CMOS switch COLBj ′ corresponding to the j′th column, turns off the other CMOS switch COLBj (j ≠ j ′), and Bit line BLj ′ is connected to data line DL. The configurations of the sense amplifier 600 and the output circuit 700 are the same as those in the third embodiment.

  The write control circuit 810, the write driver 510, and the row decoder 210 are different from those of the third embodiment. In the present embodiment, it is necessary to switch the voltage supplied to the source lines SLpq and SLqr corresponding to the memory cell Mkj to which data is written according to the write data Din. A circuit for this purpose is provided in the write control circuit 810, the write driver 510 and the row decoder 210.

  FIG. 8 is a diagram showing operating conditions of the nonvolatile memory according to the present embodiment. First, data writing will be described. For example, when the access destination is the memory cell M10, the column decoder 300 turns on the CMOS switch COLB0, and the bit line BL0 is connected to the data line DL. In addition, the first row is selected by the row decoder 210.

  When the write data Din is “0”, the write control circuit 810 outputs 0.6 V to the data line DL from the write driver 510 and the memory cell Mkj to be accessed from the row decoder 210 in between. 0V is output to two sandwiched source lines (in this example, source lines SL01 and SL12), and 0.6V and 0V are output to the row selection line WLk and the inverted row selection line WLkB, respectively. As a result, current flows through the path of the write driver 510 → data line DL → bit line BL0 → memory cell M10 → source lines SL01 and SL12 → row decoder 210, and the resistance variable element R1 of the memory cell M10 becomes low resistance. Data “0” is stored.

On the other hand, when the write data Din is “1”, the write control circuit 810 outputs 0 V from the write driver 510 to the data line DL, and the row decoder 210 sandwiches the memory cell Mkj to be accessed 2 0.6V is output to the two source lines (in this example, source lines SL01 and SL12), and 0.6V and 0V are output to the row selection line WLk and the inverted row selection line WLkB, respectively. As a result, current flows through the path of row decoder 210 → source lines SL01 and SL12 → memory cell M10 → bit line BL0 → data line DL → write driver 510, and resistance change element R1 of memory cell M10 becomes high resistance. Data “1” is stored.
The operation at the time of data reading is the same as that in the third embodiment.

  FIG. 9 is a circuit diagram showing a partial configuration of the write control circuit 810 and the row decoder 210 in the present embodiment. Write control circuit 810 includes a circuit 810A shown in FIG. This circuit 810A includes a NOR gate 811 and inverters 812 and 813. The NOR gate 811 receives a signal WEB obtained by inverting the write enable signal WE and data DINB obtained by inverting the write data Din. When the write enable signal WE is “0” and the signal WEB is “1”, the output signal of the NOR gate 811 is fixed to “0”. In this case, the inverter 813 supplies a source voltage SL of 0V to the row decoder 210. When the write enable signal WE is “1” and the signal WEB is “0”, the output signal of the NOR gate 811 has the same value as that obtained by inverting the signal DINB, that is, the write data Din. Therefore, the inverter 813 supplies the source voltage SL of 0V to the row decoder 210 when the write data Din is “0”, and the source voltage SL of 0.6V when the write data Din is “1”. Is supplied to the row decoder 210.

  The row decoder 210 includes row selection circuits 210-k (k = 0 to m) corresponding to the respective rows of the memory cell array 110. Each row selection circuit 210-k corresponding to each row outputs a selection voltage WL and an inversion selection voltage WLB for turning on a selection switch of each nonvolatile memory in the row when the row address ADDX indicates the row. , A circuit for outputting a source voltage for data writing or data reading to two source lines sandwiching the row. FIG. 9 illustrates the configuration of the row selection circuit 210-1 among the row selection circuits 210-k (k = 0 to m).

  In FIG. 9, the address match detection circuit 211 indicates “0” when the row address ADDX indicates a row corresponding to the row selection circuit 210-1 (in this example, the first row), and “1” otherwise. Is output. The inverter 212 inverts the output signal of the address coincidence detection circuit 211. When the inversion result is “0” (that is, the row address does not coincide), the inverter 212 outputs the selection voltage WL of 0V to the row selection line WL1, and inverts When the result is “1” (that is, the row address coincides), the selection voltage WL of 0.6V is output to the row selection line WL1. Further, the inverter 213 inverts the output signal of the inverter 212, and outputs an inversion selection voltage WLB of 0.6V to the inversion row selection line WL1B when the inversion result is “1” (ie, row address mismatch). When the inversion result is “0” (that is, the row address matches), the inversion selection voltage WLB of 0V is output to the inversion row selection line WL1B.

N-channel transistor 214 and P-channel transistor 215 form a CMOS switch that transmits source voltage SL to source line SL01. N channel transistor 216 and P channel transistor 217 form a CMOS switch that transmits source voltage SL to source line SL12. In these CMOS switches, the row address ADDX indicates the row corresponding to the row selection circuit 210-1 (in this example, the first row), the voltage with respect to the row selection line WL1 is 0.6V, and the inverted row selection line WL1B. When the voltage with respect to becomes 0V, it is turned on, and the source voltage SL is supplied to the source lines SL01 and SL12. As described above, the source voltage SL supplied to the source lines SL01 and SL12 is 0V when the write data Din is "0", and 0.6V when the write data Din is "1".
The row selection circuit 210-1 has been described above as an example, but the configuration of other row selection circuits is the same.

  FIGS. 10A to 10C are diagrams showing layout examples of the memory cell array 110 in this embodiment. FIG. 10A shows the layout of various wirings and elements without omitting the second metal layer M2, and FIG. 10B shows the layout of various wirings and elements without the second metal layer M2. It is shown. Further, in FIG. 10C, the N-channel transistor TN, the P-channel transistor TP, and the variable resistance element R1 that form one nonvolatile memory cell surrounded by the one-dot chain line in FIG. A rough layout of each polysilicon layer forming the bit line BL1 by the second metal layer M2 connected to the volatile memory cell, the source lines SL01 and SL12 by the first metal layer M1, and the row selection lines WL1 and WL1B is shown. .

  The P-channel transistor TP of the nonvolatile memory cell surrounded by the alternate long and short dash line is formed in the NWELL surrounded by the broken line. The source of the P-channel transistor TP is connected to the source line SL01 of the first metal layer M1 wired in the left-right direction in the drawing via a P-channel transistor contact CN3. The drain of the P-channel transistor TP is connected to the drain of the N-channel transistor TN by the first metal layer M1. The N channel transistor TN is connected to the source line SL12 of the first metal layer M1 through an N channel transistor contact CN4. A resistance change occurs between the first metal layer M1 connecting the drain of the P-channel transistor TP and the drain of the N-channel transistor TN and the bit line BL1 formed by the second metal layer M2 wired in the vertical direction in the drawing. A mold element R1 is inserted. By wiring in this way, the horizontal pitch can be basically laid out with the minimum 2F (F is the minimum design rule), so that a very small memory cell size can be realized.

  Also in this embodiment, the same effect as the third embodiment can be obtained. Further, in this embodiment, as shown in FIG. 7, since the wiring in the vertical direction (direction along the column) is only the bit line BLj (j = 0 to n), a memory cell with a small area is realized. Can do.

  In this embodiment, the transistors 214, 215, 216, and 217 shown in FIG. 9 are omitted, and the source lines SL01, SL12, SL23,... Are all connected to a common source line that transmits the source voltage SL. May be. In this case, the row decoder 210 becomes very simple and the area can be reduced. However, this aspect is not suitable for high-speed writing because the parasitic capacitance of the common source line increases. This aspect is effective when designing an inexpensive nonvolatile memory with a reduced area.

<Fifth Embodiment>
FIG. 11 is a circuit diagram showing a configuration of a nonvolatile memory according to the fifth embodiment of the present invention. The present embodiment is a modification of the fourth embodiment. Similar to the fourth embodiment, also in the memory cell array 120 in the present embodiment, source lines SL01 to SL (m−1) m are wired in the direction along the row. However, in this embodiment, in the memory cell array 120, the memory cell array 120 includes a shared source line S01 for the 0th and 1st rows, a shared source line S23 for the 2nd and 3rd rows, and so on. Source lines S (k−1) k (k = 1, 3, 5,..., M) are wired one by one in two consecutive rows of 120. Each source line S (k−1) k corresponds to the upper and lower two rows of memory cells M (k−1) j (j = 0 to n) and Mkj (j = 0 to n) corresponding to the source line. A source voltage SL is supplied.

  In this embodiment, one row selection circuit 250- (k−1) k is provided for each two rows of the memory cell array 120. One row selection circuit 250- (k−1) k includes selection voltages for the row selection lines WL (k−1) and WL (k−1) B corresponding to the k−1th row, and the kth row. The selection voltages for the row selection lines WLk and WLkB corresponding to, and the source voltage for the shared source line SL (k−1) k of the (k−1) th and kth rows are output. The write control circuit 850 controls the source voltage generated by the row selection circuit 250- (k−1) k.

  The configurations of the column selection unit 410, the column decoder 300, the sense amplifier 600, the output circuit 700, and the write driver 510 are the same as those in the fourth embodiment.

  FIG. 12 is a diagram showing operating conditions of the nonvolatile memory according to the present embodiment. In this example, the operating conditions are shown for the case where the memory cells M00 and M10 connected to the common source line S01 are access targets. First, assume that the memory cell M00 is selected. Here, when the write data Din is “0”, the write control circuit 850 outputs a voltage of 0.6 V to the data line DL. As a result, the voltage of the bit line BL0 becomes 0.6V. When the access target is the memory cell M00, the row selection circuit 250-01 outputs 0.6V to the row selection line WL0, 0V to the inverted row selection line WL0B, and outputs a source voltage 0V to the source line SL01. To do. As a result, a current flows from the bit line BL0 to the source line SL01 via the memory cell M00, the resistance variable element R1 of the memory cell M00 becomes low resistance, and data “0” is stored. On the other hand, when the write data Din is “1”, the write control circuit 850 outputs the voltage 0V to the data line DL. As a result, the voltage of the bit line BL0 becomes 0V. The row selection circuit 250-01 outputs 0.6V to the row selection line WL0, 0V to the inverted row selection line WL0B, and outputs a source voltage 0.6V to the source line SL01. As a result, a current flows from the source line SL01 to the bit line BL0 via the memory cell M00, the resistance variable element R1 of the memory cell M00 becomes high resistance, and data “1” is stored.

  In these cases, the row selection circuit 250-01 outputs 0V to the row selection line WL1 and 0.6V to the inverted row selection line WL1B, so that the CMOS switch SW of the memory cell M10 in the first row is turned off. . Therefore, the memory cell M10 is not affected by the data write to the memory cell M00, and the resistance value of the resistance variable element R1 of the memory cell M10 does not change.

  Next, it is assumed that the memory cell M10 is selected. Also in this case, if the write data Din is “0”, the voltage 0.6V is output to the data line DL, and the voltage of the bit line BL0 becomes 0.6V. The row selection circuit 250-01 outputs 0.6V to the row selection line WL1, 0V to the inverted row selection line WL1B, and outputs a source voltage 0V to the source line SL01. As a result, a current flows from the bit line BL0 to the source line SL01 via the memory cell M10, the resistance variable element R1 of the memory cell M10 has a low resistance, and data “0” is stored. On the other hand, when the write data Din is “1”, the voltage 0V is output to the data line DL, and the voltage of the bit line BL0 becomes 0V. The row selection circuit 250-01 outputs 0.6V to the row selection line WL1, 0V to the inverted row selection line WL1B, and outputs a source voltage 0.6V to the source line SL01. As a result, a current flows from the source line SL01 to the bit line BL0 via the memory cell M10, the resistance variable element R1 of the memory cell M10 becomes high resistance, and data “1” is stored.

In these cases, the row selection circuit 250-01 outputs 0V to the row selection line WL0 and 0.6V to the inverted row selection line WL0B, so that the CMOS switch SW of the memory cell M00 in the 0th row is turned off. . Therefore, the memory cell M00 is not affected by the data write to the memory cell M10, and the resistance value of the resistance variable element R1 of the memory cell M00 does not change.
The data reading operation is the same as that in the third embodiment.

  FIG. 13 is a circuit diagram showing a configuration example of the row selection circuit 250- (k-1) k in the present embodiment. In this example, the configuration of the row selection circuit 250-01 is shown, but other row selection circuits have the same configuration.

  The address match detection circuit 251 is a circuit that outputs “0” when the row address ADDX indicates k−1 (0 in this example), and outputs “1” otherwise. The address match detection circuit 252 is a circuit that outputs “0” when the row address ADDX indicates k (1 in this example), and outputs “1” otherwise. The inverter 253 inverts the output signal of the address coincidence detection circuit 251. When the inversion result is “1” (that is, ADDX = 0), the selection voltage WL of 0.6V is applied to the row selection line WL0. Otherwise, the selection voltage WL of 0V is output to the row selection line WL0. The inverter 254 inverts the output signal of the inverter 253. When the inversion result is “0” (that is, ADDX = 0), the inversion selection voltage WLB of 0V is applied to the inversion row selection line WL0B. Outputs an inversion selection voltage WLB of 0.6 V to the inversion row selection line WL0B. The inverter 255 inverts the output signal of the address coincidence detection circuit 252, and when the inversion result is “1” (that is, ADDX = 1), the selection voltage WL of 0.6V is applied to the row selection line WL1. Otherwise, the selection voltage WL of 0V is output to the row selection line WL1. The inverter 256 inverts the output signal of the inverter 255. When the inversion result is “0” (that is, ADDX = 1), the inversion selection voltage WLB of 0V is applied to the inversion row selection line WL1B. Outputs an inversion selection voltage WLB of 0.6 V to the inversion row selection line WL1B.

  The NAND gate 257 outputs “1” when one of the output signals of the address match detection circuit 251 or 252 is “0” (that is, ADDX = 0 or 1), and outputs “0” otherwise. To do. When the signal WEB obtained by inverting the write enable signal WE is “0” (that is, when WE = “1”), the NOR gate 258 inverts and outputs the signal DINB obtained by inverting the write data Din ( That is, a signal having the same logical value as that of the write data Din is output), and when the signal WEB is “1”, “0” is output. When the output signal of the NAND gate 257 is “1” (that is, when ADDX = 0 or 1), the NAND gate 259 inverts and outputs the output signal of the NOR gate 258. The inverter 260 inverts the output signal of the NAND gate 259. When the inversion result is “0”, the inverter 260 outputs the source voltage SL of 0V to the source line SL01, and when the inversion result is “1”. A source voltage SL of 0.6 V is output to the source line SL01. Here, when ADDX = 0 or 1, and the write enable signal WE is “1”, the NAND gate 259 outputs a signal obtained by inverting the write data Din. Therefore, the inverter 260 outputs the source voltage SL of 0V to the source line SL01 when the write data Din is “0”, and the source voltage SL of 0.6V when the write data Din is “1”. Is output to the source line SL01. On the other hand, when ADDX is neither 0 nor 1, or when the write enable signal WE is “0”, the NAND gate 259 outputs “1”. Therefore, the inverter 260 outputs the source voltage SL of 0V to the source line SL01. According to this row selection circuit 250- (k-1) k, the operation under the operation condition shown in FIG. 12 can be realized.

<Sixth Embodiment>
FIG. 14 is a circuit diagram showing a configuration of a nonvolatile memory according to the sixth embodiment of the present invention. This embodiment is a modification of the fifth embodiment. The configuration of the memory cell array 120 is the same as that of the fifth embodiment. Also in this embodiment, the shared source line S01 is used for the 0th and 1st rows of the memory cell array 120, the shared source line S23 is used for the 2nd and 3rd rows, and so on. Source lines S (k−1) k (k = 1, 3, 5,..., M) are wired at a rate of one by one, and each source line S (k−1) k is on each of the upper and lower sides. The source voltage SL is supplied to the memory cells M (k−1) j (j = 0 to n) and the memory cells Mkj (j = 0 to n).

  The row selection circuit 200- (k−1) k (k = 1, 3, 5,..., M) is the row selection circuit 250- (k−1) k (k = 1, 3, 5, m), the circuit for generating the source voltage SL (NOR gate 258, NAND gates 257 and 259, inverter 260 in FIG. 13) is omitted. In the present embodiment, the row selection circuit 250- (k−1) k (k = 1, 3, 5,..., M) to the row selection circuit 200- (k−1) k (k = 1, 3, 5). ,..., M), and source decoders 900-0 to 900-h are added. The source decoders 900-0 to 900-h constitute source line selection means for outputting a source voltage for data writing or data reading to a source line connected to a nonvolatile memory cell in a row indicated by a row address. Yes. In the present embodiment, common source lines COMSL0 to COMSLh that collectively combine a plurality of source lines SL01, SL23,. The source decoders 900-0 to 900-h are connected to these common source lines COMSL0 to COMSLh, respectively. Each source decoder 900-k includes the source line of the set when the source line connected to the nonvolatile memory cell in the row indicated by the row address ADDX is included in the set of source lines associated with the source decoder. A source voltage for data writing or data reading is output to the common source line CMSLk.

  FIG. 15 shows source decoders 900-0 to 900-h and source lines S01, S12,..., S (m−1) m when common source lines COMSL0 to COMSLh are provided to group four source lines in common. It is a circuit diagram which shows these connection relationships. In this example, all the source lines are divided into a set of a predetermined number of source lines, and common source lines COMSL0 to COMSLh for collecting the source lines for each set are provided.

  According to the present embodiment, the configuration of the row selection circuit can be simplified as compared with the fifth embodiment, and the chip area of the nonvolatile memory can be reduced. Further, according to the present embodiment, all source lines are divided into a plurality of groups, and the source voltage is supplied in units of groups. Therefore, each load is applied to the source decoders 900-0 to 900-h. An increase in parasitic capacitance can be suppressed, and an increase in writing speed can be achieved.

  16A to 16C are plan views showing layout examples of the memory cell array 120 in the present embodiment. In this example, wiring between the elements of the memory cell array is performed by a three-layer wiring including a first metal layer M1, a second metal layer M2, and a third metal layer M3. FIG. 16A shows the layout of various wirings and elements without omitting all the metal layers, and FIG. 16B shows the layout of various wirings and elements without the second metal layer M2. In FIG. 16C, the second metal layer M2 and the third metal layer M3 are omitted, and various wirings and element layouts are shown. In FIG. 17, one nonvolatile memory cell surrounded by an alternate long and short dash line in FIG. 16A, a nonvolatile memory cell on the right side of the same row, and a nonvolatile memory cell in the row below, respectively. A rough layout of the N-channel transistor TN, the P-channel transistor TP, and the resistance variable element R1 that constitute the circuit and the wiring between the elements of these nonvolatile memory cells is shown.

  As shown in FIG. 16A, in the nonvolatile memory cell surrounded by the alternate long and short dash line, the row selection lines WL2 and WL2B by the third metal layer M3 and the source line SL23 by the first metal layer M1 cross in the horizontal direction. . The row selection line WL2 formed by the third metal layer M3 is connected to the gate NG of the N-channel transistor TN of the nonvolatile memory cell (see FIG. 16B). Further, the inversion row selection line WL2B formed by the third metal layer M3 is connected to the gate PG of the P-channel transistor TP of the nonvolatile memory cell (see FIG. 16B). The source of the N-channel transistor TN and the source of the P-channel transistor TP are connected to the source line SL23 by the first metal layer M1 (see FIGS. 16B and 16C). Then, the bit line BL0 by the second metal layer M2 crosses the nonvolatile memory cell surrounded by the alternate long and short dash line in the vertical direction, and the bit line BL0, the drain of the P channel transistor TP, and the drain of the N channel transistor TN are connected to each other. The resistance variable element R1 is inserted between the wiring (horizontal wiring) of the first metal layer M1 to be connected (see FIGS. 16A and 16C).

  In this layout example, between two non-volatile memory cells adjacent in the horizontal direction, the P channel transistors TP or the N channel transistors TN are adjacent to each other, and the gates of the two P channel transistors TP are shared. The gates of the two N-channel transistors TN are formed of a common polysilicon wiring. In this layout example, the P-channel transistors TP or the N-channel transistors TN are adjacent to each other between two nonvolatile memory cells adjacent in the vertical direction (see FIG. 17). In this layout example, the bit lines BL0, BL1,... Are wired in the vertical direction using the second metal layer M2. Therefore, the required area of the memory cell array 120 can be reduced.

<Other embodiments>
Although the first to sixth embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:

(1) In the third to sixth embodiments, the variable resistance nonvolatile memory cell of the first embodiment (FIG. 1) is used as the memory cell Mkj. However, the resistance of the second embodiment (FIG. 3) is used. A changeable nonvolatile memory cell may be used as the memory cell Mkj. In this case, as shown in FIG. 4, the selection voltage WL output to the memory cell in the row to be accessed at the time of data reading is set to 0.3V, the inversion selection voltage WLB is set to 0.6V, and the data from the sense amplifier 600 The voltage applied to the line DL may be 0.6V.

(2) The sixth embodiment (FIG. 14) is applied to the fourth embodiment (FIG. 7), the source lines of the memory cell array are grouped into a plurality of groups, and the source voltage is applied to each group from each source decoder. You may make it supply.

(3) As the variable resistance element R1, a CER (Corrosive Electro-Resistance) resistance element used in a ReRAM memory cell may be used.

(4) In each of the embodiments described above, the configuration in which the output is 1 bit has been described. However, when configuring a non-volatile memory having a multi-bit output (for example, × 16 configuration), a plurality of basic configurations in each embodiment are provided. They may be arranged in parallel. In this case, a plurality of row decoders are provided. However, in order to reduce the area, the decoder unit can be shared by adopting a known global decoder / local decoder configuration.

TN: N-channel transistor, TP: P-channel transistor, R1: Variable resistance element, BL, BL0 to BLn: Bit line, SL, SL0 to SLn: Source line, 100, 110, 120: Memory Cell array, 200, 210... Row decoder, 300... Column decoder, 400, 410. 800, 810, 850 ... write control circuit, 500, 510 ... write driver, 600 ... sense amplifier, 700 ... output circuit, 210-0 to 210-n, 250-01 to 250- (m- 1) m, 200-01 to 200- (m-1) m... Row selection circuit, 900-0 to 900-h.

Claims (6)

A resistance variable element and a selection switch composed of an N-channel field effect transistor and a P-channel field effect transistor connected in parallel are connected in series between the bit line and the source line, and the selection switch is on the bit line side, The variable resistance element is provided on the source line side;
At the time of data writing, a selection voltage for turning on the N channel field effect transistor and an inversion selection voltage for turning on the P channel field effect transistor are applied to the gates of the N channel field effect transistor and the P channel field effect transistor, A voltage having a polarity corresponding to write data is applied between the source line and the source line, and at the time of data reading, a selection voltage for turning on the N-channel field effect transistor, which is lower than that at the time of data writing, and the P An inversion selection voltage for turning off the channel field-effect transistor is applied to each gate of the N-channel field-effect transistor and the P-channel field-effect transistor, and a predetermined magnitude of the same magnitude as that during the data write is applied between the bit line and the source line Polarity voltage Applied to, non-volatile memory cells, characterized in that to detect the current flowing between the bit line and the source line.   The nonvolatile memory cell according to claim 1, wherein the resistance change element is a magnetic tunnel junction element or a resistance element in which an electric field induced giant resistance change occurs. A variable resistance element and a selection switch composed of an N-channel field effect transistor and a P-channel field effect transistor connected in parallel are connected in series between the bit line connection end and the source line connection end, respectively, in a matrix form A plurality of nonvolatile memory cells arranged to form a memory cell array;
A plurality of wirings provided for each row of the memory cell array, extending in a direction along each row and crossing the memory cell array, and connected to gates of N-channel field effect transistors of each nonvolatile memory cell in the row. Row selection line
A plurality of wirings provided for each row of the memory cell array, extending in a direction along each row and crossing the memory cell array, and connected to gates of P-channel field effect transistors of each nonvolatile memory cell in the row. Inverted row selection line and
A plurality of source lines that are provided so as to sandwich each row of the memory cell array, extend in the direction along each row, and cross the memory cell array, and each of the nonvolatile memory cells in one row sandwiched between adjacent source lines A plurality of source lines connected to the source line connection ends;
A plurality of bit lines provided for each column of the memory cell array, extending in a direction along each column, crossing the memory cell array, and connected to a bit line connection end of each nonvolatile memory cell in each column;
A selection voltage and an inversion selection voltage for turning on a switch for selecting a nonvolatile memory cell in the row are output to a row selection line and an inversion row selection line corresponding to the row indicated by the row address, and are output to a row other than the row indicated by the row address. The selection voltage and the inversion selection voltage for turning off the selection switch for the nonvolatile memory cell in the row are output to the corresponding row selection line and the inversion row selection line, and the data is supplied to the two source lines sandwiching the row indicated by the row address. A row decoder that outputs a source voltage for writing or reading data;
A column selection unit that selects one bit line from the bit lines provided for each column and connects to the data line;
A column decoder for causing the column selector to select a bit line of a column corresponding to a column address;
A write driver for controlling a bit voltage output to the data line at the time of data writing according to write data;
A non-volatile memory comprising: a sense amplifier that determines data stored in a non-volatile memory cell to be accessed by detecting a current flowing into the data line when reading data. At the time of data writing, the row decoder and the write driver output the source voltage and the bit voltage so that the voltage between the source voltage and the bit voltage has a polarity corresponding to the write data. nonvolatile memory according to claim 3, characterized.   The row decoder includes a plurality of row selection circuits each corresponding to each row of the memory cell array, and each row selection circuit corresponding to each row has a row address indicating the row. 4. A selection voltage for turning on a selection switch and an inversion selection voltage are output, and a source voltage for data writing or data reading is output to two source lines sandwiching the row. Non-volatile memory as described. A variable resistance element and a selection switch composed of an N-channel field effect transistor and a P-channel field effect transistor connected in parallel are connected in series between the bit line connection end and the source line connection end, respectively, in a matrix form A plurality of nonvolatile memory cells arranged to form a memory cell array;
A plurality of wirings provided for each row of the memory cell array, extending in a direction along each row and crossing the memory cell array, and connected to gates of N-channel field effect transistors of each nonvolatile memory cell in the row. Row selection line
A plurality of wirings provided for each row of the memory cell array, extending in a direction along each row and crossing the memory cell array, and connected to gates of P-channel field effect transistors of each nonvolatile memory cell in the row. Inverted row selection line and
A plurality of source lines provided for each set of two consecutive rows of the memory cell array, extending in a direction along the rows and crossing the memory cell array, each row of nonvolatile memory cells corresponding to each source line A plurality of source lines connected to each source line connection end of
A plurality of bit lines provided for each column of the memory cell array, extending in a direction along each column, crossing the memory cell array, and connected to each bit line connection end of each nonvolatile memory cell in each column;
A selection voltage and an inversion selection voltage for turning on a switch for selecting a nonvolatile memory cell in the row are output to a row selection line and an inversion row selection line corresponding to the row indicated by the row address, and are output to a row other than the row indicated by the row address. A selection voltage and an inversion selection voltage for turning off the switch for selecting a nonvolatile memory cell in the corresponding row are output to the corresponding row selection line and inversion row selection line, and corresponding to a set of two rows including the row indicated by the row address A row decoder for outputting a source voltage for data writing or data reading to one source line;
A column selection unit that selects one bit line from the bit lines provided for each column and connects to the data line;
A column decoder for causing the column selector to select a bit line of a column corresponding to a column address;
A write driver for controlling a bit voltage output to the data line at the time of data writing according to write data;
A sense amplifier that determines data stored in a nonvolatile memory cell to be accessed by detecting a current flowing into the data line when reading data;
The row decoder includes a plurality of row selection circuits provided for each set of two consecutive rows of the memory cell array, and each row selection circuit is configured so that each non-volatile in each row when the row address indicates the row. A circuit corresponding to each row of the set that outputs a selection voltage and an inversion selection voltage for turning on the selection switch of the memory, and a source line corresponding to the set when the row address indicates any row of the set A nonvolatile memory comprising a circuit for outputting a source voltage for data writing or data reading.

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